Abstract: The present method prevents malfunctions in switching caused by a light leakage current in an active matrix type thin film transistor substrate for a liquid crystal display and prevents display failures, by selectively disposing a self assembled monolayer film in a gate electrode-projected region of the surface of an insulator film with high definition, and by selectively improving the orientation order of an organic semiconductor film only in the gate electrode-projected region without improving the order at an irradiated portion with light outside the gate electrode-projected region.

Abstract: A semiconductor device and a process for producing the same, the semiconductor device comprising two conductive layers provided as separate layers, and an insulating layer sandwiched by the two conductive layers, in which the two conductive layers are electrically connected to each other with an embedded conductive layer or an oxide conductive layer provided as filling an opening formed in the insulating layer, and the embedded conductive layer comprises an organic resin film containing a conductive material dispersed therein or an inorganic film containing a conductive material dispersed therein.

Abstract: A thin film transistor array panel is provided, which includes: a gate line formed on an insulating substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line formed on the gate insulating layer; a drain electrode formed at least in part on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode; a color filter formed on the data line and the drain electrode; a second passivation layer formed on the color filter; and a pixel electrode formed on the color filter, connected to the drain electrode, overlapping the second passivation layer, and enclosed by the second passivation layer.

Abstract: An object of the present invention is to provide a TFT of new structure in which the gate electrode overlaps with the LDD region and a TFT of such structure in which the gate electrode does not overlap with the LDD region. The TFT is made from crystalline semiconductor film and is highly reliable. The TFT of crystalline semiconductor film has the gate electrode formed from a first gate electrode 113 and a second gate electrode in close contact with said first gate electrode and gate insulating film. The LDD is formed by ion doping using said first gate electrode as a mask, and the source-drain region is formed using said second gate electrode as a mask. After that the second gate electrode in the desired region is selectively removed. In this way it is possible to form LDD region which overlaps with the second gate electrode.

Abstract: A thin film transistor array substrate includes a gate pattern on a substrate. The gate pattern includes a gate electrode, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line. A source/drain pattern includes a source electrode and a drain electrode, a data line connected to the source electrode, and a lower data pad electrode connected to the data line. A semiconductor pattern is formed beneath the source/drain pattern. A transparent electrode pattern includes a pixel electrode connected to the drain electrode, an upper gate pad electrode connected to the lower gate pad electrode, and an upper data pad electrode connected to the lower data pad electrode. The thin film array substrate further includes a gate insulating pattern and a passivation film pattern stacked at remaining areas excluding areas within which the transparent electrode pattern is formed.

Abstract: A thin film transistor formed by using a Metal Induced Lateral Crystallization process and method for fabricating the same. The thin film transistor comprises an active layer having source/drain regions and a channel region, a gate electrode, an insulating layer having contact holes for exposing a portion of each of the source/drain regions, and a crystallization inducing pattern exposing a portion of the active layer. The source/drain electrodes are coupled to the source/drain regions through the contact holes, and the crystallization inducing pattern does not couple the source/drain regions to the source/drain electrodes.

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position.

Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III–V elements and a combination of II–VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer (passivation film) such as SiN provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. According to the present invention, a light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air.

Abstract: In a light-emitting diode package made in accordance with the present invention, a light-emitting diode assembly is positioned above a spacer assembly. In the light-emitting diode assembly, a die containing a light-emitting diode is positioned above a substrate. During operation, both the combination of at least one conductive plate adjacent to the die and a plurality of castellated side holes positioned on sides of the substrate, and a substrate thermal via positioned beneath the die, conduct thermal energy from the die to a light-emitting diode assembly pad on which the substrate is mounted. The light-emitting diode assembly pad conducts thermal energy to a top pad of the spacer assembly. A plurality of castellated side holes formed in sides of a spacer of the spacer assembly and a plurality of thermal vias positioned within the spacer conduct thermal energy from the top pad of the spacer assembly to a base pad of the spacer assembly.

Abstract: A light emitting diode (LED) grown on a substrate doped with one or more rare earth or transition element. The dopant ions absorb some or all of the light from the LED's active layer, pumping the electrons on the dopant ion to a higher energy state. The electrons are naturally drawn to their equilibrium state and they emit light at a wavelength that depends on the type of dopant ion. The invention is particularly applicable to nitride based LEDs emitting UV light and grown on a sapphire substrate doped with chromium. The chromium ions absorb the UV light, exciting the electrons on ions to a higher energy state. When they return to their equilibrium state they emit red light and some of the red light will emit from the LED's surface. The LED can also have active layers that emit green and blue and UV light, such that the LED emits green, blue, red light and UV light which combines to create white light.

Abstract: An optical semiconductor device includes an optical semiconductor chip and a light permeable member covering the optical semiconductor chip. The light permeable member has a light emitting surface for emitting light coming out from the optical semiconductor chip to the outside. The light emitting surface includes a plurality of standing surfaces standing in a second direction which intersects a first direction in which the light emitting surface spreads.

Abstract: A liquid crystal device is provided that comprises a plurality of R colored layers, a plurality of G colored layers, and a plurality of B colored layers that are formed on either one of a pair of substrates and are aligned in a predetermined arrangement in plan view, a light-shielding layer formed between the colored layers, and a plurality of spacers formed on either one of the pair of substrates and protruding toward the other substrate. The plurality of spacers is formed around the B colored layers and/or the R colored layers, but is not formed around the G colored layers. Thus, even if a positional deviation occurs between the substrates, the spacers do not get into the G colored layers.

Abstract: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 ?·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.

Abstract: A first principal plane faces a second principal plane of a p-type Ga N compound semiconductor that is in contact with an MQW luminescent layer. On the surface of the first principal plane, a first region made up of the p-type Ga N compound semiconductor including at least Ni is formed. On the surface of the first region, an electrode composed of an alloy including Ni and Aluminum is formed. On the electrode, a pad electrode for external connection consisting of Al or Au is formed.

Abstract: Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semiconducting blocking region of an impurity band semiconducting device included in a solid state photon detector.

Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.

Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.

Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.

Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.

Abstract: A trench type power semiconductor device includes a channel region atop an epitaxially silicon layer and a plurality of shallow gate electrode trenches within the channel region such that the bottom of each trench extends to a distance above the junction defined by the channel region and epitaxially silicon layer. Formed at the bottom of each trench within the channel region are trench tip implants of the same conductivity as the epitaxial silicon layer. The trench tip implants extend through the channel region and into the epitaxially silicon layer. The tips effectively pull up the drift region of the device in a localized fashion. In addition, an insulation layer lines the sidewalls and bottom of each trench such that the insulation layer is thicker along the trench bottoms than along the trench sidewalls. Among other benefits, the shallow trenches, trench tips, and variable trench insulation layer allow for reduced on-state resistance and reduced gate-to-drain charge.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer. 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from the drain area and having a doping of the second conductivity type, and a channel area in the substrate that is arranged between the source area and the drain area. In a portion of the substrate bordering the drain area, an area having a doping of the second conductivity type, which is connected to the drain area, is arranged such that in the portion alternating regions having the first conductivity type and having the second conductivity type are arranged.

Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor film is formed on a substrate surface, and a recess is created beneath the film. A portion of the film is influenced into the void and strained. In various embodiments, the naturally-occurring Van der Waal's force is sufficient to influence the film into the void. In various embodiments, a nano-imprint mask is used to assist with influencing the film into the void. In various embodiments, an oxide region is formed in a silicon substrate, and a single crystalline silicon film is formed on the semiconductor substrate and on at least a portion of the oxide region. The oxide region is removed allowing the Van der Waal's force to bond the film to the silicon substrate. Other aspects are provided herein.

Abstract: A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type.

Abstract: An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region.

Abstract: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.

Abstract: A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (7a). The lightly-doped shallow impurity region (7a) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion (70) is provided to the heavily-doped impurity region (7b) to reduce the contact resistance at the drain (7).

Abstract: An apparatus for transverse characterization of materials includes a lower pattern of contacts, separated by spacings, a material, and an upper pattern of a multiplicity of contacts, separated by spacings differing from the spacings of the lower pattern. The transverse characterization method includes receiving lower pattern of a multiplicity of contacts, separated by spacings along a surface, with a material above the surface, successively placing an upper contact near the upper surface of the material in an upper pattern of locations separated by spacings differing from the spacings of the lower pattern, measuring the characteristics between the upper contact and one or more contacts of the lower pattern and evaluating the measured characteristics to previous measurements, wherein the evaluation provides the transverse characterization.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor active region, a semiconductor contact layer, at least one metal migration semiconductor barrier layer, and a metal contact. The metal migration semiconductor barrier layer may be embedded within the semiconductor contact layer. Furthermore, the metal migration semiconductor barrier layer may be located underneath or above and in intimate contact with the semiconductor contact layer. The metal migration semiconductor barrier layer and the semiconductor contact layer form a contact structure that prevents metals from migrating from the metal contact into the semiconductor active layer during long-term exposure to high temperatures.

Abstract: Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away and disposed of as waste during fabrication are left as conserved sections. These conserved sections are used to amend the properties and performance of the imager array. In the resulting structure, the conserved sections absorb incident light. The patterned portions of conserved material provide additional light shielding for array pixels.

Abstract: The present invention relates to a method for producing a GMR structure in which a metallic multiple layer is applied onto a carrier and in which the metallic multiple layer is patterned to produce the GMR structure, the carrier having a structure before the metallic multiple layer is applied and the patterning of the metallic multiple layer is performed by CMP. The present invention also relates to a GMR structure having a carrier and a patterned metallic multiple layer positioned on the carrier, the patterned metallic multiple layer being situated in one or more depressions of the carrier. In addition, the present invention relates to a use of GMR structures.

Abstract: A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is formed with the aid of two leads that can be driven by external contacts of the printed circuit board, and with the aid of connection lines between in each case two semiconductor memory chips. By means of the series circuit, individual semiconductor memory chips can be driven selectively with respect to the rest of the semiconductor memory chips without having to interrupt the regular data transport via the address and control lines. During normal memory operation, chip-specific test data or other data can be interrogated and be read out via an electric loop formed between the further external contacts.