Abstract: The invention provides a display device including an insulating substrate, a photosensor formed on the insulating substrate and including a semiconductor layer, an input terminal and an output terminal electrically connected to the semiconductor layer, a first insulating layer formed on the photosensor, a pixel electrode, an organic layer, and a common electrode layer sequentially formed on the first insulating layer, and a controller that controls an input to the pixel electrode based on an output of the photosensor.

Abstract: Provided are a WLCSP of an image sensor and a method of manufacturing the same. The WLCSP includes a wafer, support members, glass, and metal bumps. The wafer has an image sensor and a pair of pads disposed thereon, a portion of the bottom surface of the image sensor being exposed outward from the both ends of the wafer. The support members are disposed on the pads to support the both bottom sides of the glass, the support members being formed to a predetermined thickness to provide a space for forming an air cavity. The glass is safely seated on the support members such that the air cavity is formed on the wafer. The metal bumps are disposed on the both sides of the wafer corresponding to the pads such that the bottom surfaces of the metal bumps protrude beyond the bottom surface of the wafer and form conductive lines electrically connected to the pads. Therefore, the package can be directly attached to a camera module even without using a separate PCB or ceramic substrate.

Abstract: A MOS type solid-state image pickup apparatus comprises: a semiconductor substrate having a light receiving surface; a plurality of photoelectric conversion elements arranged in an array manner on the light receiving surface; a plurality of layers of wirings that goes across the light receiving surface and are stacked above the semiconductor substrate, the wirings being connected to signal reading circuits each of which is provided in association with each of the photoelectric conversion elements; and an insulation layer interposed with the layers of wirings, wherein a first wiring, which connects to a gate of a MOS transistor forming a part of each of the signal reading circuits, is provided in a lower one of the layers of wirings, and a second wiring, which connects to a source or drain of the MOS transistor, is provided in an upper one of the layers of wirings.

Abstract: A submount substrate for mounting a light emitting device and a method of fabricating the same, wherein since a submount substrate for mouthing a light emitting device in which a Zener diode device is integrated can be fabricated by means of a silicon bulk micromachining process without using a diffusion mask, some steps of processes related to the diffusion mask can be eliminated to reduce the manufacturing costs, and wherein since a light emitting device can be flip-chip bonded directly to a submount substrate for a light emitting device in which a Zener diode device is integrated, a process of packaging the light emitting device and the voltage regulator device can be simplified.

Abstract: In an embodiment, a memory device, with a highly integrated cell stricture, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern.

Abstract: A semiconductor component with a pn junction comprises a semiconductor body comprising a front side and an edge region. A pn junction is formed fashion in curved fashion in the edge region of the semiconductor body. An edge structure comprising depressions is also provided in the edge region of the semiconductor body. The depressions may comprise, for example, a number of capillaries which extend into the semiconductor body proceeding from the front side of the semiconductor body.

Abstract: A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Abstract: MIMCAP semiconductor devices and methods for fabrication MIMCAP semiconductor devices that include a grown capacitor dielectric are provided. Exemplary MIMCAP semiconductor devices can include a bottom electrode, a grown capacitor dielectric on the bottom electrode, and a top electrode on the capacitor dielectric. The grown layer can have a k-value greater than 1 and can be formed of, for example, an oxide or nitride that is chemically or thermally grown from the bottom electrode.

Abstract: A semiconductor device includes semiconductor substrate, a plurality of element forming regions formed on the semiconductor substrate, and an interconnect for connecting the plurality of element forming regions to one another. A concave portion whose upper surface is lower than that of the surfaces of the element forming regions connected by use of the interconnect is formed in the surface of the semiconductor substrate under the interconnect.

Abstract: A semiconductor film composition includes an oxide semiconductor material. At least one polyatomic ion is incorporated into the oxide semiconductor material.

Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Abstract: A semiconductor device in which the threshold voltage of transistors is controlled through the applied substrate bias and having relatively small size. The semiconductor device includes: a clock signal line; a shield wiring for shielding the clock signal line from another interconnection; and a substrate bias generating circuit. The substrate bias is applied through the shield wiring to a region on which a transistor is formed. The threshold voltage of the transistor depends to the substrate bias applied to the transistor.

Abstract: A lead frame package structure with high density of lead pins arrangement is formed. The lead frame structure includes a die, a plurality of first lead pins and a plurality of second lead pins, wherein the first lead pins and the second lead pins are positioned on at least one side of the die, and are electrically connected to the die. The first lead pins and the second lead pins are selected from a group consisting of J-leads, L-leads and I-leads, and terminals of the first lead pins and terminals of the second lead pins are staggered so that the high density of lead pins arrangement is formed without risking a short circuit.

Abstract: The present invention provides a flexible substrate for a package of a die which has an active surface and a plurality of first bond pads arranged in a form of a row and formed on the active surface. The flexible substrate includes a flexible insulating film and a plurality of first leads formed on the flexible insulating film. Each of the first leads corresponds to one of the first bond pads and has a respective first body portion, a respective first bond portion and a respective first extension portion. For each of the first leads, the width of the first bond portion is larger than those of the first body portion and the first extension portion.

Abstract: A display panel comprising a substrate, signal lines, bonding pads, connecting leads, and capacitance compensating devices. The signal lines are disposed on the substrate. The bonding pads are disposed in a bonding area on the substrate and connected to a driver. The connecting leads are arranged in a fan configuration. Lengths of the connecting leads gradually decrease from the outside to the inside of the fan configuration. Each connecting lead is connected between the bonding pad and the signal line and has a compensating section, and lengths of the compensating sections are equal. Each capacitance compensating device is coupled to the compensating section of the corresponding connecting lead. The compensating values of the capacitance compensating devices gradually increase from the outside to the inside of the fan configuration.

Abstract: A semiconductor package has a substrate (8) and a semiconductor die (2). The substrate (8) includes a plurality of contact pads (9) on its upper surface and a second plurality of external contact areas (10) on its bottom surface. The semiconductor die (2) includes an active surface with a plurality of die contact pads (3) electrically connected by conducting means (4) to contact pads (9) on the substrate (8) and a layer of first adhesive means (5) on the upper surface (18) of the die (2). Mold material (15) covers the first adhesive means (5), the die (2) and the upper surface of the substrate (8).

Abstract: A semiconductor packaging process comprising following steps is provided. First, a wiring substrate with a first surface and a second surface is provided. Next, a non-solvent type two-stage thermosetting compound is formed on the first surface of the wiring substrate. The non-solvent type two-stage thermosetting compound is then partially-cured such that a non-solvent type B-stage adhesive layer is formed on the first surface of the wiring substrate to provide a carrier for semiconductor packages. Thereafter, a chip is attached on the first surface of the wiring substrate via the B-stage adhesive layer. Ultimately, the chip is electrically connected to the wiring substrate and an encapsulating material is then formed to seal the chip. A carrier for semiconductor packages used the above mentioned packaging process is also provided.

Abstract: A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

Abstract: An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.

Abstract: A semiconductor light-emitting device according to an embodiment of the present invention includes chip LEDs formed on a silicon submount, in which a wiring pattern having a chip connecting terminal portion connecting the chip LEDs, an external connecting terminal portion connecting an external unit, and a plurality of lead portions connecting a corresponding chip connecting terminal portion and a corresponding external connecting terminal portion is formed on the silicon submount, and an area of the chip connecting terminal portions is made larger than an area of a region where the chip connecting terminal portion overlaps with the chip LEDs. Accordingly, a semiconductor light-emitting device of high heat radiation property and heat resistance can be provided.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion.

Abstract: An apparatus and method for connecting one substrate, such as a semiconductor die, to an opposing substrate, such as a semiconductor package or circuit board, through a plurality of intermediate thermal compensator devices, each of which can incrementally and/or locally mitigate the stresses imposed by differences in the two substrate's thermal expansion characteristics. The compensator devices can be coupled to one another, with the resulting assembly attached to the first substrate on one side, and to the second substrate on the other side, through solder bump attach, or some equivalent method. The method of the invention provides electrical connection and thermal dissipation between the two substrates as well as providing mechanical protection by absorbing the stresses imposed by the difference in thermal expansion characteristics of the two substrates.

Abstract: A semiconductor module (4) has a coupling substrate which is used for the internal electrical coupling of an integrated circuit on adjacent semiconductor chips (2, 3). The semiconductor chips (2, 3) have integrated circuits and are arranged on a mount structure. The semiconductor chips (2, 3) are externally connected to external contacts (22). The coupling substrate (1) overlaps edge areas (6, 7) of the adjacent semiconductor chips (2, 3).

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: An insulating layer 12 is formed as a surface layer of electronic circuit chip 10. A conductor interconnect 14 is formed in the insulating layer 12. The conductor interconnect 14 is exposed in the surface of the insulating layer 12. A solder wetting metallic film 16 (a metallic film) is formed on a portion of the conductor interconnect 14 to be exposed in the surface of the insulating layer 12. Typical metallic material (second metallic material) available for composing the solder wetting metallic film 16 includes a material that requires higher free energy for forming an oxide thereof, as compared with a free energy required for forming an oxide of the metallic material composing the conductor interconnect 14.

Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film, a tungsten film, a first barrier metal film, a second barrier metal film and a metal wiring film. The interlayer insulating film is formed on the semiconductor substrate, and has an opening. The tungsten film is embedded in the opening. The first barrier metal film is formed on the tungsten film and excludes a Ti film. The second barrier metal film is formed on the first barrier metal film and is a Ti-containing film. The metal wiring film is formed on the secondbarrier metal film.

Abstract: A protective enclosure for use with a handheld electronic device having a casing with controls. The protective enclosure includes an inner skin shaped to receive and form fit a major portion of the casing of the electronic device, and an outer skin shaped to receive and form fit the inner skin, having openings located to allow access to the selected controls. The inner skin and the outer skin are made from an elastomeric material, preferably silicone. Together, the skins protect the electronic device from impacts, dust, debris, perspiration or other external factors, while permitting normal function of the controls of the electronic device. The inner skin may include control portions that register with at least some of the selected controls having tactile surfaces that facilitate the operation of the controls.

Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate, an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.

Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

Abstract: An interconnect substrate 10 includes an insulating resin layer 12 (base material), an interconnect 14 and an electrode pad 16. On the insulating resin layer 12, the interconnect 14 and the electrode pad 16 are provided. The interconnect 14 and the electrode pad are integrally formed. A first metal material, exposed in the surface S1 of the electrode pad 16 opposite to the insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material, exposed in the surface S2 of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

Abstract: A wafer level marking system is provided including: providing a wafer, a wafer frame, and a support tape; mounting the wafer and the wafer frame on the support tape; and marking the wafer through the support tape.

Abstract: Embodiments of the invention provide a low-melting temperature comprised primarily of a bulk intermetallic phase material. This solder may allow reflow with less of a chance to damage microelectronic devices due to coefficient of thermal expansion mismatches, and may be creep resistant even at high homologous temperatures.

Abstract: A bump structure mainly includes a metal core, a buffer encapsulant, and a metal cap where the metal core is a stud bump formed by wire bonding. The buffer encapsulant encapsulates the metal core. A metal cap is formed on the top surface of the buffer encapsulant and is electrically connected to the metal core. Therefore, the bump structure possesses excellent resistance of thermal stress to reduce or even eliminate metal fatigue in the bump without causing electrical shorts in the package.

Abstract: A semiconductor chip includes a plurality of chip pads and a plurality of bumps formed on respective chip pads, each bumps including a bump main body and a conductive particle disposed on the bump main body and exposed to the air, the conductive particle including an elastic portion made of an elastic material and a conductive layer enclosing the elastic portion.

Abstract: A structure for sufficiently alleviating the thermal stress between an LSI and substrate and allowing the LSI to be detached from a substrate easily is provided. In a flip-chip type assembly according to the present invention, an interposer made of silicon intervenes between the device and the substrate. The LSI and the interposer are connected with a solder and, the interposer and the substrate are connected with a conductive resin. The conductive resin alleviates the thermal stress between the substrate and the interposer. The LSI can be detached easily by heating the solder. The thermal stress between the LSI and the interposer can be reduced because both of them are made of silicon.

Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.

Abstract: The present invention discloses a dense arrangement in the conductors of a package and the corresponding conductive pads of a circuit board. The conductors and the corresponding conductive pads are separated into at least a first group in a peripheral region of the grid array package, and a second group in another region of the grid array package. Most in the first group of conductive pads are apart at a first pitch, most in the second group of conductive pads are apart at a second pitch which is less than the first pitch. According to the shrinking in the conductive trace on a conductive layer and the shrinking in the through hole, the first pitch and the second pitch are optimized for the maximum conductors and the corresponding conductive pads.

Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.

Abstract: A hybrid module includes a silicon substrate having a plurality of part mounting openings formed therein, the plurality of part mounting openings composed of through holes, a plurality of mounted parts that are mounted in the part mounting openings such that input/output portion forming surfaces are substantially flush with a first main surface of the silicon substrate, a sealing layer that is formed of a sealing material filled into the part mounting openings and covers the mounted parts, with the input/output portion forming surfaces exposed from the first main surface of the silicon substrate, to fix the mounted parts in the part mounting openings, and a wiring layer that is formed on the first main surface of the silicon substrate, and has a wiring pattern connected to input/output portions that are provided on the input/output portion forming surfaces of the mounted parts exposed from the first main surface.

Abstract: Disclosed are a method for forming a metal interconnection and a semiconductor device including the metal interconnection. The method includes the steps of forming a slope by etching a corner of a contact hole, which exposes a predetermined pattern formed on a substrate, forming a barrier metal layer on an interlayer dielectric layer, plasma-treating the barrier metal layer with hydrogen and nitrogen gases for about 27 to 37 seconds, heat-treating the substrate in a nitrogen atmosphere, forming a tungsten layer on the barrier metal layer through a two-step nucleation process and bulk deposition process, and performing a chemical mechanical polishing process on the tungsten layer until the interlayer dielectric layer is exposed. The method and the semiconductor device prevent defects of the metal interconnection, such as a volcano defect caused by fluorine penetration.

Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.

Abstract: A semiconductor structure includes a first dielectric layer having a k value of less than about 2.7, a second dielectric layer over the first dielectric layer, a via in the first dielectric layer, a conductive line in the second dielectric layer, wherein the conductive line extends from a top surface of the second dielectric layer into the second dielectric layer and electrically coupled to the via, a third dielectric layer on the second dielectric layer, and a fourth dielectric layer between the second dielectric layer and the conductive line. The second dielectric layer is preferably a porous material and has an ultra low k value. The k value of the second dielectric layer is lower than the k values of the first, the third and the fourth dielectric layers.

Abstract: An electrode and a method for forming the electrode. The electrode comprises: a substrate; and a plurality of metal particles adhering to the substrate. The method comprises steps of: providing a substrate; providing a solution including a solvent and a plurality of metal particles on the substrate; removing the solvent; and making the plurality of metal particles adhere to the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a lower insulating film formed on the semiconductor substrate, an interconnect-forming metal film provided so as to fill a recess formed in the surficial portion of the lower insulating film, and containing copper as a major constituent, an upper insulating film formed on the lower insulating film, and a metal-containing layer formed between the lower insulating film and the upper insulating film, and containing a metal different from copper. The metal-containing layer includes a first region in contact with the interconnect-forming metal film, and a second region in contact with the lower insulating film, and having a composition different from that of the first region, and contains substantially no nitrogen at least in the first region.

Abstract: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.

Abstract: A printed board having wiring patterns laminated with insulating layers therebetween is provided. The printed board has a through hole and via holes. A terminal of an electronic component can be inserted into the through hole and a conducting layer is formed on the through hole for connecting wiring patterns of outer layers. A wiring pattern of an inner layer is not connected electrically to the conducting layer. The via holes are provided around the through hole for electrically connecting the wiring pattern of the inner layer and the wiring patterns of the outer layers.

Abstract: A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.