Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.

Abstract: In a nitride semiconductor laser bar including a group III-V nitride semiconductor layer, on the front-side cavity end face, a separation layer of aluminum nitride is laid, and further on the separation layer, an end face coating film of aluminum oxide is laid. Likewise, on the rear-side cavity end face, a separation layer of aluminum nitride is laid, and further on the separation layer, an end face coating film of an aluminum oxide/TiO2 multilayer film is laid.

Abstract: An object of the present invention is to provide a group III nitride semiconductor stacked structure having a high-quality A-plane group III nitride semiconductor layer on an R-plane sapphire substrate. The inventive group III nitride semiconductor stacked structure comprises a substrate composed of R-plane sapphire (?-Al2O3), a buffer layer composed of aluminum gallium nitride (AlxGa1?xN: 0?X?1) formed on said substrate and an underlying layer composed of an A-plane group III nitride semiconductor (AlxGayInzN1?aMa: 0?X?1, 0?Y?1, 0?Z?1, and X+Y+Z=1; wherein, M represents a group V element other than nitrogen (N), and 0?a?1) formed on said buffer layer, wherein the pit density of the surface of said underlying layer is 1×1010 cm?2 or less.

Abstract: A plurality of display elements each includes two signal lines: S1 and S2. An electrode 4, which is one of the electrodes constituting an element capacitor Cp, is connected to the signal line S1 via a switching element TFT1, while the other electrode 5 is connected to the signal line S2 via a switching element S2. The gate electrodes of the switching elements TFT1 and TFT2 are connected to a single common scanning line G. With this structure the drive voltage applied to the element capacitor can be increased even when a TFT has a limited withstand pressure.

Abstract: A display device which may include a first substrate and a second substrate facing each other to form a plurality of cells between the first and second substrates, a plurality of first electrodes and a plurality of second electrodes disposed between the first substrate and the second substrate, electron accelerating layers formed on side surfaces of the first electrodes for accelerating and emitting electrons toward the side surfaces when voltages are applied to the first and second electrodes, a gas filled in the cells and excited by the electrons, and a light emitting layer disposed between the first substrate and the second substrate, or on an outer side surface of the first substrate or the second substrate.

Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.

Abstract: In a semiconductor device including a core transistor and an I/O transistor on the same semiconductor substrate, the core transistor includes a gate insulating film, a gate electrode, sidewalls, extension diffusion layers, and source/drain diffusion layers. The I/O transistor includes a gate insulating film, a gate electrode, sidewalls, and source/drain diffusion layers. In the I/O transistor, the source/drain diffusion region is offset relative to a channel region located beneath the gate insulating film in regions below the sidewalls.

Abstract: Since a power source voltage is generated from a communication signal in a wireless chip, there is a risk that a large amount of voltage be generated in the wireless chip to electrically destroy a circuit in the case of supplying a strong communication signal. Therefore, the present invention is made with an aim to provide a wireless chip having resistance to a strong communication signal. A wireless chip of the present invention has an element in which a power source wire and a grounding wire are electrically short-circuited if a power source voltage exceeds a voltage at which an electric circuit is destroyed, i.e., exceeds the specified voltage range. Accordingly, a wireless chip of the present invention has resistance to a strong communication signal.

Abstract: A main object of the present invention is to provide a solid-state image sensor capable of efficiently collecting a light beam when the central position of the light receiving element and the central position of the micro lens do not coincide with each other in the plan view owing to a plural pixel sharing structure.

Abstract: A solid-state image pickup device includes a pixel array section including a plurality of unit pixels, a reference signal production section configured to generate a reference signal and output a detection value, a comparison section configured to compare a reset level upon resetting, a counter configured to start a counting action and continue the counting action to measure a comparison time period in order to obtain count values corresponding to the reset level and the signal level, a detection section configured to retain a result of the comparison of said comparison section when the reset level reaches the detection value as a result of the detection of a black sun phenomenon for a fixed period of time, and a prevention section configured to prevent a black sun phenomenon based on a result of the detection of said detection section.

Abstract: A display device, and method for making the same, comprising a thin film transistor formed on a first insulating substrate, a pixel electrode electrically connected to the thin film transistor, an organic layer formed on the pixel electrode, a common electrode formed on the organic layer, a conductive layer formed on the common electrode, a transparent electrode layer formed on the conductive layer, the transparent electrode being applied with a common voltage, and a second insulating substrate located on the transparent electrode layer. Thus, the present invention provides a display device to which common voltage is applied effectively.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel region (30) extending in the body region (6) from a source end adjacent to the source region (8) to a drain end adjacent to a drain end part (26) of the drain region (4). A conductive shield plate (22) is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension (32) extending over the drain region from the shield plate (22) towards the gate (14).

Abstract: Embodiments of the invention include a circuit with a transistor having a self-aligned gate. Insulating isolation structures may be formed, self-aligned to diffusions. The gate may then be formed self-aligned to the insulating isolation structures.

Abstract: MTJ devices commonly degrade when subjected to the heat treatments required by subsequent further processing. This problem has been overcome by protecting the MTJ's sidewalls with a two layer laminate. The first layer is laid down under oxygen-free conditions, no attempt being made to replace any oxygen that is lost during the deposition. This is followed immediately by the deposition of the second layer (usually, but not mandatorily, of the same material as the first layer) in the presence of some oxygen.

Abstract: A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.

Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a ferroelectric capacitor arranged above the semiconductor substrate; an insulating protecting film covering a side surface of the ferroelectric capacitor; and a side wall film formed on a side surface of the ferroelectric capacitor through the protecting film and giving tensile stress to the ferroelectric capacitor in a direction of an electric field applied to the ferroelectric capacitor.

Abstract: A phase change memory device includes a substrate, a switching element formed in the substrate and a storage node connected to the switching element. The storage node may include a lower electrode connected to the switching element, a first phase change layer formed on the lower electrode, a magnetic resistance layer formed on the first phase change layer, a second phase change layer formed on the magnetic resistance layer and an upper electrode formed on the second phase change layer.

Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.

Abstract: A dual damascene structure is described, including a substrate, a dielectric layer, a hard mask layer, a contact and a conductive line. The dielectric layer is located on the substrate, the hard mask layer is on the dielectric layer, the contact is located in the dielectric layer, and a horizontal cross-section of the contact has an asymmetrically rounded outline. The conductive line is in the hard mask layer and the dielectric layer, and is located on and electrically connected to the contact. The conductive line has a laterally swelling portion on an edge portion of the first contact, wherein the borders of the laterally swelling portion and the edge portion are contiguous.

Abstract: A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET transistor and MIM capacitor are formed in a memory region and an asymmetric processing method is disclosed, which allows planar MOSFET transistors to be formed in another region of a single device. In some embodiments, the 1T-RAM cell and additional transistors may be combined to form a macro cell, multiple macro cells may form an integrated circuit. The MIM capacitors may include nanoparticles or nanostructures to increase the effective capacitance. The finFET transistors may be formed over an insulator. The MIM capacitors may be formed in interlevel insulator layers above the substrate. The process provided to manufacture the structure may advantageously use conventional photomasks.

Abstract: A capacitor assembly includes a semiconductor substrate having an interlayer insulation film on a first main surface of the semiconductor substrate, and a conductive barrier layer formed on the interlayer insulation film. The capacitor assembly also includes a contact plug electrically connected to the conductive barrier layer through the interlayer insulation film, and a lower electrode formed on the barrier layer. The capacitor assembly also includes a capacitor insulation film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The capacitor insulation film is made from a ferroelectric material. The barrier layer is an amorphous film which includes titanium and aluminum.

Abstract: A field effect device includes at least one segmented field plate, each of the at least one segmented field plates having a plurality of segments that each form a plate of a capacitor, wherein the field effect device is connected to an electronic element that dynamically connects selected segments to selectively set a gate-to-drain and a drain-to-source capacitance. An ultrasonic device includes a transducer coupled to a switching device that switches the transducer between a transmit mode and a receive mode switching device, wherein the switching device includes the field effect device.

Abstract: An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

Abstract: A semiconductor device (2) has a semiconductor chip (16) the front side (1) of which has integrated circuit elements and an electrically conductive metallization structure (3) with chip contact areas (9). The metallization structure (3) has an electrically conductive patterned adhesion layer (6), which provides a low-resistance contact with silicon, and an electrically conductive patterned intermediate layer (7), which provides a connectable surface. Furthermore, a passivation layer (8) is provided, which covers the top side and the edge sides of the intermediate layer (7) whilst leaving the chip contact area (9) free. The intermediate layer (7) comprises Ni and is free of noble metals. The intermediate layer (7) is at least 10 times thicker than the adhesion layer (6).

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; an elevated source/drain region formed away from the gate electrode, a surface of the elevated source/drain region being higher than that of the semiconductor substrate; a source/drain extension region formed in the semiconductor substrate lying under a recess portion formed between the gate electrode and the elevated source/drain region; a first gate sidewall insulating film formed on a side face of the gate electrode, and on a bottom face and a side face of the recess portion; and a second gate sidewall insulating film formed on the first gate sidewall insulating film.

Abstract: In a semiconductor device including a semiconductor substrate, and an n-channel type MOS transistor produced in the semiconductor substrate, the n-channel type MOS transistor includes a gate insulating layer formed on the semiconductor substrate and having a thickness of at most 1.6 nm, and a gate electrode layer on the gate insulating layer, and the gate electrode layer is composed of polycrystalline silicon which has an average grain size falling within a range between 10 nm and 150 nm in the vicinity of the gate insulating layer.

Abstract: A nonvolatile memory includes a plurality of drain regions and a plurality of source regions, and a plurality of control gate regions. The drain regions and the source regions are formed on a semiconductor chip so as to extend parallel to each other and extend between opposite ends of the semiconductor chip, and resistances of the source regions per unit length along its longitudinal direction are higher than resistances of the drain regions per unit length along its longitudinal direction. The control gate regions are formed on the semiconductor chip to extend in a direction perpendicular to the drain regions and the source regions. With this arrangement, the cell size can be reduced without causing deterioration of the writing characteristic and increase of the off leak current.

Abstract: An SOI semiconductor component comprises a semiconductor substrate having a basic doping, a dielectric layer arranged on the semiconductor substrate, and a semiconductor layer arranged on the dielectric layer. The semiconductor layer includes a drift zone of a first conduction type, a junction between the drift zone and a further component zone which is configured in such a way that a space charge zone is formed in the drift zone when a reverse voltage is applied to the junction, and a terminal zone adjacent to the drift zone. A first terminal electrode is connected to the further component zone, and a second terminal electrode is connected to the terminal zone. In the semiconductor substrate a first semiconductor zone is doped complementarily with respect to a basic doping of the semiconductor substrate, and the first terminal electrode is connected to the first semiconductor zone. A rectifier element is connected between the first terminal electrode and the first semiconductor zone.

Abstract: A method of fabricating an MOS device is described. A substrate doped a first type dopant is provided as a drain. A first type epitaxial layer is formed on the substrate and is patterned with a trench to form several islands. A gate dielectric layer is than formed on the surface of the trench, and a gate is formed in the trench covering the gate dielectric layer. A second type dopant is doped into the islandswith the doping concentration decreasing gradually from the bottom to the top of the islands. Afterwards, a source is formed at the top of the islands. Accordingly, the doping concentration in the islands decreases gradually from the drain to the sourcewith the highest doping concentration near the drain. Therefore, the width of the depletion region can be reduced, and the length of the device channel can be reduced for lowering channel resistance and gate capacitance.

Abstract: An objective of the present invention is to provide a semiconductor device capable of suppressing generation of the hot carriers while reducing resistance in a drain region, and a method of manufacturing the same. Specifically, the present invention provides a semiconductor device including a field effect transistor comprising a source region and a drain region in the surface region of a semiconductor silicon substrate, characterized in that the drain region has a multiple impurity diffusion layer including at least a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer, and a bird's beak provided on the side of the drain region of the lower part of a gate electrode provided is larger than a bird's beak provided on the side of the source region of the lower part of the gate electrode.

Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity; and a semiconductor layer provided on the semiconductor substrate and having a super junction structure including drift layers of the first conductivity and RESURF layers of a second conductivity different from the first conductivity, the drift layers and the RESURF layers being laterally arranged in alternate relation parallel to the semiconductor substrate, the RESURF layers being each provided alongside an interior side wall of a trench penetrating through the semiconductor layer, the drift layers each having an isolation region present between the RESURF layer and the semiconductor substrate to prevent the RESURF layer from contacting the semiconductor substrate.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

Abstract: A semiconductor device includes a first insulator formed at a part under a semiconductor layer, a second insulator formed under the semiconductor layer in an arranged manner avoiding the first insulator and having a relative dielectric constant different from that of the first insulator, a backgate electrode formed under the first and second insulators, a gate electrode formed on the semiconductor layer, and a source layer and a drain layer formed in the semiconductor layer to be respectively arranged on opposite lateral sides of the gate electrode.

Abstract: An ESD protection device with a low trigger voltage includes a semiconductor layer, a lightly doped well region formed in the semiconductor layer, a highly doped anode region formed in the well region, a highly doped cathode region formed in the semiconductor layer, a highly doped bridging region bridging a junction between the semiconductor layer and the well region, and a highly doped channel stop region of formed in semiconductor layer between the cathode region and the bridging region. The trigger voltage may be adjusted over a range of voltages, and the ESD protection devices may be connected in parallel in order to be effective in very high current situations.

Abstract: A semiconductor device includes a substrate, a first oxide film lying on the substrate, a thin semiconductor film lying on the first oxide film, a first terminal formed on the semiconductor film, a second terminal formed on the semiconductor film, a semiconductor element formed on the semiconductor film and electrically connected between the first and second terminals, and a protective diode formed on the semiconductor film and electrically connected in between the second and first terminal in a forward direction.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Abstract: An IGBT is provided which comprises N+ type extended region 9 sectively formed in P+ type collector region 1 to define a built-in diode in cooperation with N+ type extended region 9, an N? type base region 2 and a P? type base region 3 in semiconducting substrate 10. N? type base region 2 comprises a recombination region 21 developed between P type base region 3 and collector electrode 8 to acquire minority carriers accumulated around recombination region 21 in first base region 2 by recombination region 21 for improvement in recovery property of the diode without increasing voltage in the forward direction since recombination region 21 does not reach between and beneath adjoining second base regions 3 in N type base region 2 for current path.

Abstract: A method is described for forming an at least partially silicided contact. In one embodiment, a hardmask is deposited over a contact. A coating of sacrificial material is then provided on top of the hardmask. The sacrificial material coating is etched back until the top of the contact is exposed. The contact is then opened, the sacrificial material is removed, and a silicidation of the contact is performed.

Abstract: A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body.

Abstract: Embodiments of the invention include sequentially forming a pad oxide film and a mask film on a semiconductor substrate, and then forming an opening for partially exposing the pad oxide film. An undercut region is formed using the mask film as an etch mask, exposing a partial surface of the substrate. A spacer is formed surrounding both sidewalls of the mask film, and a recess is formed in the substrate. A gate oxide film, a gate electrode, a gate insulation film, a gate spacer, and source and drain regions are also formed. A resultant transistor structure has a small open critical dimension that improves process margin and provides uniformity to the recess depth, and removes a requirement that a bottom critical dimension of a subsequently formed self-aligned contact should be small. Degradation of the gate oxide film and increases in leakage current may also be prevented.

Abstract: A method of fabricating a semiconductive film stack for use as a polysilicon germanium gate electrode to address problems associated with implant and diffusion of dopants. Achieving a sufficiently high active dopant concentration at a gate-dielectric interface while avoiding gate penetration of dopants such as boron is problematic. A higher gate implant dosage or annealing temperature is needed, and boron penetration through the thin gate oxide is inevitably enhanced. Both problems are exacerbated as the gate dielectric becomes thinner. In order to achieve a high level of active dopant concentration next to the gate dielectric without experiencing problems associated with gate depletion and penetration, a method and procedures of applying a diffusion-blocking layer is described with respect to an exemplary MOSFET application. However, a diffusion-blocking concept is also presented, which is readily amenable to a variety of semiconductor related technologies.

Abstract: An electro-acoustic transducer wherein a stopper of a terminal is composed of an elastic body having an impulsive-force resistance and an excellent resilience. The stopper is mounted on the yoke or lower plate of magnetic circuit, which is made of a metallic material having an impulsive-force resistance. In this way, the stopper can restrict the terminal within the reversibility limit value of the spring force of the metallic material, and hence can enhance the reliability.

Abstract: A CMOS image sensor is provided. The CMOS image sensor incorporates a semiconductor substrate having a photodiode area and a transistor area; a trench area formed in the photodiode area; a transistor and a floating diffusion area formed on the transistor area; a first conductive type diffusion area formed on the photodiode area; and a second conductive type diffusion area formed on the trench area above the first conductive diffusion area.

Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

Abstract: The CMOS image sensor includes one or more photodiodes formed on a semiconductor substrate to generate current in accordance with the amount of incident light, an interlayer insulating layer formed on the semiconductor substrate including the photodiodes, color filter layers formed on the interlayer insulating layer to transmit specific wavelengths, and micro-lenses formed on the color filter layers between the insulating layer patterns to concentrate light on the photodiodes.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.