Abstract: An accumulator package (2) for a hand-held power tool includes: a housing (4) having a plurality of accumulator cells (28) provided therein, a connection element (18) electrically connected with the accumulator cells (28) and accessible from outside, a charge state display (22) for displaying a charge state of the accumulator cells (28), a locking mechanism (14) for securing the accumulator package (2) on the power tool, and locking mechanism-operating elements (16) that simultaneously form accessible from outside outer switch elements for actuating the charge state display.

Abstract: The invention relates to a new VRLA battery float model. The model covers the steady state and transient float charge behaviour of both positive and negative electrodes. Backup analysis verifies the internal polarisation distribution for a conventional 2V-cell polarisation behaviours can be identified without the need for a physical reference electrode. The estimated individual electrode polarisation allows early detection of common failure modes like negative plate discharge as well as a reference for float voltage optimisation. Furthermore, the positive polarisation relating to minimum grid corrosion may be correlated with the occurrence of the peak of a “Tafel” like resistance used by the model. The model encourages utilisation of low signal perturbation for testing a cell's state of health and state of charge conditions while at float.

Abstract: A dual voltage supply system supplies high and low voltage electrical power to separate high and low voltage loads. The system includes an AC alternator and first and second rectifier circuits, each connected to the alternator and a corresponding high and low voltage load. The first rectifier circuit commutates the alternator voltage to the high voltage load when the alternator voltage is higher than a voltage of the high voltage load. The second rectifier circuit commutates the alternator voltage to the low voltage load when the alternator voltage is higher than a voltage of the low voltage load and less than some maximum voltage which is less than the maximum voltage that can be tolerated by the low voltage load(s). The second rectifier circuit is turned off whenever the first rectifier circuit is turned on.

Abstract: A method, circuit, and system for managing power dissipation in a linear regulator are provided. The method includes receiving an input voltage at a pass element of the linear regulator, delivering an output voltage through the pass element, determining an output current through the pass element, and measuring a voltage drop across the pass element. The circuit includes a pass element that is operable to receive an input voltage and deliver an output voltage and a first amplifier and a second amplifier that are operable to monitor power dissipation through the pass element. The system includes an integrated circuit, a power source that is operable to power the integrated circuit, and a linear regulator that is operable to regulate a power output from the power source to the integrated circuit.

Abstract: In some embodiments, a switching mode power converter has an input and an output. The switching mode power converter may be configured to transition between a continuous conduction mode at a first load level and a discontinuous conduction mode at a second load level, where the second load level is lower than the first load level. A control circuit may be connected to the switching mode power converter, wherein the control circuit is configured to adjust the switching frequency of the switching mode power converter during the transition between the continuous conduction mode and the discontinuous conduction mode in accordance with maintaining low voltage deviation with respect to a reference voltage. Other embodiments are disclosed and claimed.

Abstract: A high efficiency buck converter has power-saving means to improve the efficiency under both heavy load and light load conditions. A first circuit generates an oscillation signal and a power-saving signal in response to a feedback signal. In reference to the feedback signal and the oscillation signal, a second circuit generates switching signals to control switching devices. An off-time of the switching signal increases in response to a decrement of load. The power-saving signal turns off the switching devices and parts of control circuits of the buck converter during the off-time of the switching signal for saving power under light load conditions.

Abstract: A voltage regulator system is disclosed for providing a regulated voltage supply. The voltage regulator system includes a power supply input node for receiving a power supply input voltage, a regulated voltage output node for providing a regulated output voltage, and a feedback circuit coupled to the regulated output voltage node and to a voltage regulator input node wherein a non-zero voltage is provided by the voltage regulator input node.

Abstract: Techniques for an adaptive synchronous switch in switching regulators are described, one aspect of which is to achieve a more optimal on/off timing of a synchronous switch that is controlled by the comparator in a feedback control loop and thereby improves power conversion efficiency and system performance; One approach samples a node in the output of the switching regulator and generates a sampled error signal that is analyzed to determine if the current comparator offset is too high or too low relative to a target switching regulator output value at least in part based on the sampled error signal value, and accordingly generates a compensated feedback error signal and applied to the compensated feedback error signal to an input of the comparator to have the effect of a comparator offset adjustment signal.

Abstract: Techniques for near zero light-load supply current in switching regulators are described. In one aspect a voltage regulator operating a normal mode is generating an error signal indicating a difference between the output and the regulated voltage. A control signal, at least in part based on the error signal, actively controls the output of the regulator. The control signal is monitored over period of time. The monitoring activates a signal indicating when the control signal is inactive for the period of time indicating a light-load condition. The voltage regulator is then placed in a standby mode when the signal is active and the error signal indicates the output is substantially at the regulated voltage. Portions of the voltage regulator are then disabled permitting the voltage regulator to operate at the minimum current draw.

Abstract: An assembly group for current measurement comprises a conductor plate with three cuts and a measuring element placed on the conductor plate that has a difference sensor formed from two magnetic field sensors. By means of the three cuts a first and a second conductor section are formed in the conductor plate, wherein the current direction in the second conductor section runs opposite to the current direction in the first conductor section. The first magnetic field sensor is located above the first conductor section and the second magnetic field sensor is located above the second conductor section. The magnetic field sensors are sensitive to a magnetic field that runs parallel to the surface of the conductor plate and orthogonal to the current direction in the two conductor sections.

Abstract: The invention provides tester load board shields for attachment to tester load boards. The shields of the invention protect from physical damage and electromagnetic interference. A preferred embodiment of a tester load board shield of the invention is disclosed in which a disc and outer rim of conductive metal such as aluminum or aluminum alloy are configured to accept a tester load board. The tester load board shield has holes to align with a selected tester load board for attachment of the shield thereto. Stanchions are provided to facilitate attachment of the Loadboard with shield to automatic test equipment known in the arts while a tester load board, also familiar in the arts, is fastened to the shield. Another embodiment of a tester load board shield is disclosed in the shape of annulus configured to contain a tester load board within an outer rim planar surface and inner rim.

Abstract: An apparatus and a method for monitoring a ratio of at least two components being mixed use sensors detecting ferrous taggant particles in the component(s) and the mixture. The sensors include an annular drive coil positioned between inner and outer annular sense coils all surrounding a passage for material being sensed. The ratio is determined by comparing a signal generated by one sensor through which a taggant particle containing component is flowing with a signal generated by another sensor through which the mixture is flowing delayed by the time required for the component to flow from the one sensor to the another sensor. The signals can also be used to control the flow of the components and to check the mixture after use.

Abstract: A rotary position sensing including a first and second magnet spaced from one another. A first and second triangular magnetic flux director are arranged in a generally diamond shaped configured with an air gap between the two magnetic flux directors. A magnetic field sensor system is positioned in the air gap between the magnetic flux directors. The magnets and the magnetic flux directors, with the magnetic field sensor system in the air gap, are rotatable relative to one another about an axis generally normal to a plane including the magnets and magnetic flux directors. The magnetic field sensor system provides an output in response to a rotational position of the magnets relative to the magnetic flux directors.

Abstract: An apparatus, sensor, and a method for measuring an applied strain are provided. The apparatus includes a strain sensor comprising an electrically conductive member composed of a magnetostrictive material. The apparatus further includes a signal generator electrically coupled to the electrically conductive member. The signal generator is configured to generate an electrical current that propagates through the electrically conductive member. The apparatus further includes a measuring circuit electrically coupled to the electrically conductive member. The measuring circuit is configured to measure at least one of an amount of inductance, resistance, and impedance of the electrically conductive member. The apparatus further includes a processor electrically coupled to the measuring circuit. The processor is configured to calculate the amount of force applied to the strain sensor based on at least one of the amount of inductance, resistance, and impedance of the electrically conductive member.

Abstract: Method for nondestructive and contact-free detection of faults in a test specimen which is moved relative to a probe that detects a periodic electrical signal having a carrier oscillation whose amplitude and/or phase is/are modulated by any fault in the test specimen. The probe signal is filtered and sampled by a triggerablie A/D converter stage to obtain a demodulated digital measurement signal which is filtered using a digital frequency-selective adjustable second filter unit to obtain a useful signal which is evaluated to detect a fault in the test specimen. The A/D converter stage is triggered at a fraction of the frequency of the carrier oscillation selected as a function of the fault frequency obtained as the quotient of the relative speed between the test specimen and the probe and the effective width of the probe, and the frequency-selective second filter unit is adjusted as a function of the fault frequency.

Abstract: A sensor assembly includes a first magneto-resistive field sensor in a first surface-mountable package, which measures first and second components of a magnetic field projected onto respective different first and second axes with respect to a spatial orientation of the sensor and to produce first position signals indicative of the measured first and second components. A second magneto-resistive field sensor in a second surface-mountable package measures at least a third component of the magnetic field projected onto at least a third axis with respect to the spatial orientation of the sensor, and to produce second position signals indicative of the measured third component. A substrate assembly orients the first field sensor in a first spatial orientation and to orient the second field sensor in a second spatial orientation so that the third axis is oriented out of a plane containing the first and second axes.

Abstract: Magnetoresistive sensors which use the AMR or the GMR effect and indicate the direction of the homogeneous magnetic field of a rotatable permanent magnet in the angle measurement or the position of the sensor with respect to a scale, which is magnetized periodically in an alternating direction, for the position measurement, and in which the angle or position value is obtained from the quotient of the output signals from two bridges or half bridges with the aid of arctan interpolation, allow small measurement errors if the output signals have small harmonic components and hysteresis areas. In arrangements according to the invention, this is achieved by the resistors being composed of strips and by continuously varying the resistance-determining angle along the strip longitudinal extent for each constant magnetic field acting on the strips.

Abstract: The invention relates to a method for the hyperpolarisation of atomic nuclei by means of optical pumps in a sample cell. Polarisation of an electron spin of an optically pumpable species, which is produced by means of laser light, is transferred to the nucleus spin of an atom which is to be hyperpolarisied. According to the invention, components of the mixture and/or other inert compounds for hyperpolarisation are guided in the sample cell such that the mixture does not come into contact with the inner wall of the sample cell, or does to a small degree. A device for carrying out said method comprises at least one means which guides the components of the mixture of non-optical pumpable species and nuclei which are to be hyperpolarisied, and/or other inert compounds for hyperpolarisation, into the sample cell (5) such that the mixture does not come into contact with the inner wall of the sample cell (5), or does to small degree. As a result, the wall can be prevented from sagging.

Abstract: Systems and techniques for imagining samples including components with small values of T2. Optionally, the systems and techniques may provide (for example) suppression of unwanted signals, enhanced contrast, and artifact control in imaging samples with small values of T2.

Abstract: A method for simultaneously tracking an invasive device disposed within a patient and acquiring an imaging signal of the patient with a magnetic resonance imaging (MRI) system during a single echo acquisition time period (46) of the MRI system. The method includes applying a radio frequency excitation pulse (26) to a patient to start an echo acquisition time period of an MRI system. The method then includes acquiring a tracking signal (54) from the invasive device during the echo acquisition time period and also acquiring an imaging signal (36) of the patient proximate an end of the same echo acquisition time period.

Abstract: The invention relates to the obtainment of magnetic resonance measurement data for the reproduction of an image of an object volume, illustrating the contrast between volume elements (voxels) which differ from one another in the parameter vectors Pi of the magnetic resonance property of the respective inherent substance i. The object volume which is to be imaged is subjected within a stationary magnetic field to a sequence of repetitive blocks of effects, each containing an RF-pulse with a flip angle ?<90° and magnetic field gradients, in order to obtain in each block N?1 location-coded measurement signals and to achieve sufficient intravoxel dephasing, wherein the phase ?(k) of the RF-pulse is changed from block to block in accordance with the rule ?k??k-1=?+k*?, where k is the running index of the blocks within the sequence and 100 is a randomly selected phase angle.

Abstract: The invention relates to an apparatus and method which are designed to be used for diagnosis and therapy based on non-ionising radiations. The operation thereof is based on the principle of nuclear magnetic resonance. A quantitative diagnosis can be made using the following devices: a manually-controlled digital filter/selector (18), a monitor for frequency matrices (25), a monitor for frequency images (26), and a control panel (28). Moreover, therapy can be provided with the following devices: a radio frequency resonating antenna (4), a low radio frequency signal processor/modulator (10), a radio frequency pulse amplifier (13) and, a central pulse control unit (16). According to the invention, the emission parameters (frequency, power and polarity) can be selectively adjusted in order to provide personalised therapy. The invention substantially improves selection and/or differentiation levels throughout the entire process. The invention is scientifically, technically and commercially viable.

Abstract: The invention relates to a magnetic resonance imaging (MRI) system comprising a main magnet system for generating a main magnetic field in an examination volume, a gradient coil system (1) which is substantially arranged between the main magnet system and the examination volume and which comprises sub-gradient coils (4,5,6) embedded in a binding material (11) having a glass temperature, control means (13) for controlling a temperature of the gradient coil system, and temperature-influencing means for influencing the temperature of the gradient coil system on the basis of control signals supplied by the control means. The control means are suitable to control, during operation of the MRI system, the temperature of the binding material of the gradient coil system to a value above the glass temperature. The invention further relates to a method of using a magnetic resonance imaging (MRI) system.

Abstract: For the purpose of preventing development of motion artifacts and improving image quality, a first displacement N1 of the diaphragm before a scanning section 2 performs an imaging sequence and a second displacement N2 of the diaphragm after the scanning section 2 has performed the imaging sequence are detected by a body motion detecting section 25 as displacement caused by respiratory motion of a subject. Thereafter, based on the first displacement N1 and second displacement N2 of the diaphragm detected by the body motion detecting section 25, imaging data is selected as raw data by a raw data selecting section 26. Then, based on the imaging data selected as raw data by the raw data selecting section 26, a slice image of the subject is produced by an image producing section 31.

Abstract: In accordance with some embodiments of the present invention, a battery testing apparatus and method include a processor, a first clamp coupled to the processor, a second clamp coupled to the processor, and a third clamp coupled to the processor wherein the processor is configured to collect data on a current flow when the first and second clamps are connected with a first battery and the third clamp is connected to a conductor connecting the first battery with a second battery connected to the first battery in parallel. The processor is further configured to process the data to determine whether the first battery is stronger than, weaker than or the same capacity as the second battery.

Abstract: A method and apparatus for automatically performing a measurement of a power plant's battery backup capacity. The process comprises reducing an output voltage of a rectifier and identifying a time when said output voltage has been so reduced, measuring the voltage (e.g., at the output of the battery) to determine when the battery has been discharged and identifying a time when the battery has been determined to be discharged, calculating the period of time for the battery to discharge based on the two identified times, restoring the output voltage of the rectifier, and comparing the calculated period of time for the battery to discharge to a predetermined minimum acceptable period of time for the battery to discharge. Advantageously, this process is performed automatically at predetermined intervals or in accordance with a predetermined scheduling algorithm, and is advantageously performed during known “off-peak” time periods (e.g., during the overnight hours).

Abstract: A method for detecting charge defect spots (CDSs) on a chargeable surface is provided, including charging the chargeable surface to receive and hold a first voltage charge, spacing a surface of a scanner probe a distance from the chargeable surface, the scanner probe having a diameter, and biasing the scanner probe to a second voltage charge within a predetermined voltage threshold of the first voltage charge, wherein a parallel plate capacitor is established with the chargeable surface and a dielectric substance between the scanner probe and the chargeable surface.

Abstract: The present invention relates to a system applied for the measurement of the total ohmic internal resistance of fuel cells and stack of fuel cells. The apparatus comprises an electronic load system which comprises: an input unit generating an input pulse, a driver for the control of the input pulse, a MOSFET module comprising at least one MOSFET device for the generation of a short circuit in a fuel cell, a bank of selectable resistors and a measuring circuit which comprises: a shunt for converting the fuel cell current into a voltage signal, differential amplifiers for the current and the voltage signals and a data acquisition system which receives the voltage and the current signals obtained by the differential amplifiers.

Abstract: A test system and method for a MEMS sensor has an electrical input signal that drives a capacitor of the MEMS sensor. The capacitor has a movable plate. A mechanical actuator provides a mechanical stimulus to the MEMS sensor. A detection system detects an output signal of the capacitor. The system determines a resonant frequency, spring constant, damping ratio, frequency response and a hysteresis for the capacitor.

Abstract: For one embodiment, an integrated circuit includes a node to couple one or more components to the integrated circuit to carry current through a package for the integrated circuit. The integrated circuit also includes a monitor to measure a resistance of the package based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package. For another embodiment, current through one or more components that are to carry current through a package for an integrated circuit is controlled. A resistance of the package is measured based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package.

Abstract: A contact resistance measuring circuit is configured to determine the contact resistance of a testing device. The measuring circuit is coupled to a processing circuit and the testing device. The measuring circuit includes a pair of input/output units coupled together via a pass device. Each of the input/output units includes a pull-up device and a pull-down device to provide separate pull-up and pull-down control, respectively. The pull-up devices, the pull-down devices, and the pass device are dynamically configurable such that the measuring circuit uses either a pull-up mode or a pull-down mode to measure voltage and current characteristics of each contact point, or pin, of the testing device. The processing circuit calculates the contact resistance for each pin according to the measured voltage and current characteristics. The calculated contact resistances are used to calibrate the testing device.

Abstract: Disclosed herein are exemplary embodiments of a contact system (referred to as a “Z-block”) for interfacing a semiconductor wafer to an electrical tester, and methods for making the same. In a preferred embodiment, the Z-block comprises three stacked pieces or layers: an upper and lower piece which are similar in structure, and a unique middle piece. The pieces each contain corresponding locking holes and probe pin holes. The locking holes are strategically arranged on each of the pieces to allow the stacked piece structure to be locked together at various points during its manufacture. After alignment of the probe pin holes in the various pieces, probe pins are injected into these holes. The probe pins are then aligned and locked into place by moving the middle piece relative to the upper and lower pieces. Such locking of the probe pins is accomplished through interaction of the middle piece with the shape of the probe pins, which prevents the probe pins from slipping out of the probe pin holes.

Abstract: A test system and method which employs a filter bank to select different spectral components of a pulsed measurement signal. The filter bank utilizes filter nulls to suppress non-selected spectral components. After filtering the selected spectral components, the spectral components are combined to provide for a measurement signal which is analyzed to determine characteristics of a device being tested. The characteristics of the filters can be adjusted in response to a change in the characteristics of a pulsed signal applied to the device under test, so that the selected spectral components will correspond to desired spectral components generated by the pulsed signal applied to the device under test.

Abstract: A rotatable or translatable carousel configured to facilitate electrical or electronic testing of Devices Under Test (DUTs) in combination with an insertion handler and a test head is disclosed. The carousel is configured to be placed on a test head of a tester in a first position with a first Device under Test (DUT) (such as a system-on-a-chip (SOC) integrated circuit (IC)) loaded in a first test position of the carousel. A first electrical or electronic test is performed on the first DUT at the first position, after which the carousel is advanced to a second position and a second DUT is loaded in a second test position of the carousel. While the carousel is positioned at the second position, the first test is performed on the second DUT and a second electrical or electronic test is performed on the first DUT.

Abstract: An apparatus for measuring on-chip characteristics in a semiconductor circuit is provided. The apparatus for measuring the on-chip characteristics includes an oscillation unit, a timing test unit, and a selection unit. The oscillation unit is configured to selectively output a first oscillation signal responsive to a first control signal. The timing test unit is configured to generate a second oscillation signal using an input clock signal, generate a pulse from the second oscillation signal responsive to a second control signal, and determine whether an operating time violation has occurred based on a comparison of the second oscillation signal and the pulse. The selection unit is configured to select one of the output of the oscillation unit and the output of the timing test unit responsive to a test mode signal.

Abstract: One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.

Abstract: An inspection system, for inspecting pin grid arrays on integrated circuit devices includes a pin base mask configured to receive a device having a pin grid array. A dark-field, low-angle lighting system emits light onto the pin grid array. The pin base mask and low-angle lighting system provide for a clear and definitive image of the pin grid array. A camera captures the image of the pin grid array. A processor, coupled to the camera, analyzes the images captured by the camera. Based on the captured image, the processor determines whether any pins on the pin grid array are bent or missing, or whether there are extra pins present.

Abstract: A semiconductor chip package capable of detecting an open and a short is disclosed, comprising: a first pad group comprising a plurality of first substrate pad sub groups, formed on a substrate, each composed of first substrate pads electrically connected, and insulated from each other, and a plurality of first element pad sub groups formed on an element and composed of first element pads electrically connected such that each first substrate pad sub group is electrically connected through the first element pads corresponding to the first substrate pads; a second pad group electrically insulated from the first pad group when the element is connected to the substrate, and comprising a plurality of second substrate pad sub groups formed on the substrate, composed of second substrate pads electrically connected, and insulated from each other, and a plurality of second element pad sub groups formed on the element, and composed of second element pads electrically connected such that each second substrate pad sub gr

Abstract: According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes determining that the data set associated with the wafer is useable and generating a probe map of the wafer from the data set. The probe map identifies a physical position associated with each unprobed die supported on the surface of the wafer. The probe map and one or more probe commands are communicated to a probe module to drive the probe module in resuming the probe of the wafer.

Abstract: A logic circuit for board power-supply evaluation to be incorporated into a logic device loaded on a product board includes a circuit that simulates an operation of the logic device so that utilization rate is variable at an arbitrary frequency by use of a predetermined circuit in all available logic elements of the logic device; a circuit that judges normality/abnormality of an operation of the operation simulation circuit; a utilization control circuit that varies and controls utilization rate of the logic device by controlling execution of an operation of the operation simulation circuit based on a judgement result of the operation judgement circuit and sets a utilization rate when the operation simulation circuit is instructed to stop the operation; and a utilization output circuit that outputs the judgement result of the operation judgement circuit and the utilization rate set by the utilization control circuit to the outside.

Abstract: A system, method and device for managing power distribution on a shared bus system that interconnects multiple devices each containing a signal termination component are disclosed herein. In one embodiment, the method of the invention includes detecting and communicating thermal indicia of one or more of the devices in the shared bus system to a memory controller device. The memory controller includes an on-die termination control circuit for setting and resetting the enablement of the signal termination components of the one or more devices. In a preferred embodiment, the on-die termination control circuit sets and resets the enablement of the signal termination components in accordance with the determined thermal indicia.

Abstract: The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.

Abstract: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in the column direction, I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks and a reset sele

Abstract: An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.

Abstract: Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: An apparatus for controlling a hot plug bus slot on a bus has an input for receiving a set of float signals (i.e., the set may have one or more float signals), and a driver having an output electrically couplable with the bus. The apparatus also has float logic operatively coupled with the input. The float logic is responsive to the set of float signals to cause the output to float at a high impedance in response to receipt of the set of float signals.