Abstract: A semiconductor device is disclosed which increases the data transfer rate in transferring data output from an input/output sense amplifier via a global data bus line by reducing the swing width of the data placed on the global data bus line.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from the buffer controller and a specific signal to output a control signal, and an internal clock generator controlled by the control signal from the logic circuit for buffering the external clock signal and generating internal clock signals.

Abstract: The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to put the output node to a first logic level; a second transistor of a second conductivity type turned ON according to an input signal; a third transistor of the second conductivity type connected in series to the second transistor and turned ON according to a second clock; and a fourth transistor of the first conductivity type connected between the first power supply and the output node and turned ON according to a feedback signal. The second and third transistors are connected between the output node and a second power supply. The fourth transistor is turned from ON to OFF after both the second and third transistors are turned ON.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: A buffer is disclosed. The buffer may include a buffering circuit for buffering an input signal, a buffer control circuit for outputting a first control signal which enables the buffering circuit responsive to an enable signal, and a second control signal which is enabled after the lapse of a predetermined period from a point of enable timing of the first control signal, and a logic unit for performing a logic operation with respect to an output signal from the buffering circuit and the second control signal from the buffer control circuit.

Abstract: Provided is an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption. In the output buffer circuit with a compensation capacitive load, an input part has two input terminal receiving differential input voltage signals, and an output part increases a gain of the differential input voltages. A current source biases the output part, and a slew rate increasing part is connected to the output part and the compensation capacitive load. The slew rate increasing part includes a switching element to increase a slew rate of the output buffer circuit.

Abstract: A digital clock frequency multiplier (100) for increasing an input frequency of an input clock signal includes a generator (102) that receives the input clock signal and a high frequency digital signal. The generator (102) divides a count (Nhf) of a number of cycles of the high frequency digital signal in one period of the input clock signal by a predetermined multiplication factor (MF) for generating an output clock signal. The output clock signal has a predetermined output frequency.

Abstract: A power-up signal generator of a semiconductor device includes a voltage dividing block, a level detection block, and an output block. The voltage dividing block outputs a divided voltage corresponding to a voltage level of an external power supply voltage. The level detection block is controlled according to the divided voltage, and comprises a pull-up unit and a pull-down unit. The output block outputs a power-up signal having a logic level corresponding to a voltage level of an output node of the level detection block. The pull-up unit and the pull-down unit have different threshold voltage levels with respect to a temperature change.

Abstract: A power-on reset (“POR”) methodology and circuit for an electronic circuit using multiple supply voltage domains asserts a reset signal upon ramp up of the first supply voltage signal, maintains the reset signal until all of the supply voltage signals have ramped up, and de-asserts the reset signal after all of the supply voltage signals have ramped up. Practical embodiments of the POR circuit include a control circuit that reduces static and/or dynamic current leakage associated with the operation of the POR circuit.

Abstract: A startup circuit provides a single connection to a node of a reference or other circuit to be started. The startup circuit injects high current into devices to start a reference circuit. The startup circuit provides strong current invention during startup, and low power consumption during operation.

Abstract: A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: In accordance with the present disclosure, an electronic circuit of an integrated circuit is configured to receive an input signal that has a falling transition and a rising transition and provide a selectable delay of the input signal transitions on its output. The output of the disclosed circuit can provide a falling transition delayed in response to a falling edge control signal control, and a rising transition delayed in response to a rising edge control signal. The disclosed circuit can have a rising transition control circuit (RTCC), a falling transition control circuit (FTCC) and an output circuit.

Abstract: A duty cycle corrector includes a first controllable delay configured to delay a first signal to provide a second signal, a second controllable delay configured to delay the second signal to provide a third signal, a first fixed delay configured to delay the second signal to provide a fourth signal, a second fixed delay configured to delay the first signal to provide a fifth signal, and a circuit configured to adjust the first controllable delay and the second controllable delay to phase lock the third signal to the fifth signal.

Abstract: A duty correction device includes: a duty correction unit having a plurality of duty correction cells for selectively activating the duty correction cells according to a count signal to adjust a pulse width of an input clock and output the adjusted clock as an output clock; a phase splitter for generating a rising and a falling clocks by phase-splitting the output clock; a DCC pumping unit for generating a rising and a falling duty ratio correction signals according to a reset signal; a voltage comparing unit for generating counting increase and decrease signals according to a result of comparing the rising and the falling duty ratio correction signals in response to a comparison control signal; a comparison control unit for generating the comparison control signal and the reset signal; and a counter for increasing/decreasing a value of the count signal according to the counting increase and decrease signals.

Abstract: A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input signals have equivalent voltage levels. The radiation hardened inverter and its output signal produce a radiation hardened node that drives either one of the duplicated inverter paths back to an appropriate voltage level in the event of an SET. Because, the radiation hardened node and duplicated inverter paths are isolated, the latch may be optimized for factors such as signal speed and driving strength. These factors may be optimized without affecting radiation hardness. The radiation hardened latch may also be used to build more complex circuits such as a flip-flop.

Abstract: A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

Abstract: A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay while the selective pin is connected with a capacitor. The time delay circuit is composed of charge-discharge circuit, D flip-flop, RS latch, NOR gate, a 2 to 1 multiplexer (MUX 2:1). According to an embodiment, if the selective pin is floated, the outputs of the D flip-flop, and the RS latch will make MUX 2:1 to choose an output signal of the NOR gate having input signals of an internal delay signal and input signal. On the other hand, if the selective pin is connected with an eternal capacitor having an eternal capacitor more than 250 pF, the output signal of the D flip-flop, RS latch will make MUX 2:1 to choose an output of the charge-discharge circuit but ignores the internal delay signal.

Abstract: Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

Abstract: Analog bidirectional switches (20) comprising a first (1) and a second (2) urmsistor function badly in case of the signal voltage at an input or an output of the switch (20) exceeding the supply voltage used for operating the switch (20). By providing the switch (20) with a circuit (21), a second control signal (“f”) destined for the second transistor (2) is no longer generated by solely inverting a first control signal (“e”) destined for the first tranistor (1), but is generated in response to the first control signal (“e”) and by taking into account the in/output signal (“z”) at an in/output of the switch (20). The circuit (21) comprises a generator (22) for generating the second control signal (“f”) having either a fixed value or a value of the in/output signal (“z”), and comprises a detector (23) for supplying the in/output signal (“z”) to the generator (22). A further circuit (24) comprises a further generator for generating a backgate signal (“bg”) destined for the second transistor (2).

Abstract: A one mode of a gate driving circuit that drives a gate electrode of an electric power switching element (9), comprising drive means (6) configured to supply to the gate electrode a current in accordance with a voltage applied across the principal electrodes of the electric power switching element (9), while utilizing a voltage produced by dividing a voltage applied across the principal electrodes by use of resistors (4a, 4b). Since the drive means (6) utilizes a voltage produced by a voltage dividing resistor circuit, which divides the voltage applied across the principal electrodes of the electric power switching element (9) as a power source voltage, only an addition of the dividing resistors (4a, 4b) makes it possible to constitute the power source for the current drive means (6).

Abstract: A trimming circuit, an electronic circuit, and a trimming control system for reducing the risk of failures when perform trimming and for ensuring that a desired device is readily manufactured. A selector, a resistor, and a fuse are connected in series between a power supply and ground. A probe pad for performing probe trimming is connected immediately above the fuse. The selector includes two back-to-back connected n-type MOS transistors. Each n-type MOS transistor has a gate terminal connected to a selector control circuit. A trim sense circuit is arranged at a power supply side of the fuse. The trim sense circuit detects fuse breakage and changes the operation of an element associated with each trimming circuit TC based on the detection.

Abstract: A reference circuit provides a reference voltage and a reference current that are both temperature and a power supply voltage independent. The reference circuit includes a bandgap reference circuit, a current source, and a resistor. The bandgap reference circuit provides a feedback voltage to control the current source and thereby generate a temperature independent voltage and a PTAT (proportional to absolute temperature) current. A resistor having a positive temperature coefficient is coupled to the feedback controlled current source to provide a CTAT (complementary to absolute temperature) current. The CTAT current is summed directly into the feedback controlled current source to produce a reference current that is substantially constant over a range of temperatures.

Abstract: A reference voltage circuit includes first circuitry that generates a thermal voltage that is approximately proportional to absolute temperature, a first voltage multiplier, second circuitry that generates an inverse thermal voltage that is approximately inversely proportional to absolute temperature, a second voltage multiplier and a summer. The first voltage multiplier multiplies the thermal voltage to obtain a first multiplied voltage. The multiplied voltage is not equal to the thermal voltage. The second voltage multiplier multiplies the inverse thermal voltage to obtain a second multiplied voltage. The summer sums the first multiplied voltage with the second multiplied voltage to obtain a reference voltage.

Abstract: A system and method for providing a voltage. The system includes a first transistor including a first gate, a first terminal, and a second terminal. The first terminal is configured to receive a first predetermined voltage, and the first gate is configured to receive a first control signal. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal. The second gate is configured to receive a second control signal, the third terminal is biased to a second predetermined voltage, the second terminal and the fourth terminal are directly connected to a first node, and the first node is associated with a first voltage level. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal.

Abstract: A current bias circuit and a current bias start-up circuit thereof are disclosed. The bias start-up circuit supplies a compensation current to the bias circuit to compensate the leakage current of the current bias circuit during activation and turns off the compensation current after start-up. Accordingly, the bias start-up circuit could compensate the leakage current of the current bias circuit and the bias start-up circuit could reduce the power consumption.

Abstract: An apparatus for generating a power signal from a load current is described, has a controller with a load current input, a load current output, an intermediate signal output, and a status signal output, an influencing device with an intermediate signal input and a power signal output, and an interruption device with an interrupt input, an interrupt output, and a status signal input. The controller generates a status signal and an intermediate signal depending on the load current, and the interruption device interrupts the power signal if the status signal satisfies a predetermined first condition, and otherwise lets the power signal pass, and the influencing device generates the intermediate signal as the power signal and output the same at the power signal output if the intermediate signal does not satisfy a predetermined second condition, and otherwise generates and output a power signal with a predetermined value.

Abstract: In a first aspect, the invention provides an audio amplifier. A regulator reference signal corresponding to an input audio signal is generated by regulator reference generator. A power signal is generated corresponding to the regulator reference signal by a voltage regulator. A compensation block also uses the input signal, or a delayed version of the input signal to generate a modulation control signal. A modulator generates a modulated signal in response to the modulation control signal. An output stage combines the power signal and the modulation signal to provide an output audio signal corresponding to the input audio signal. The compensation block may be a forward compensation block configured to compensate for characteristics of the regulator reference generator or the voltage regulator or both, and possibly other components of the amplifier. In other embodiments, the compensation block may be part of a feedback compensation loop.

Abstract: A power amplifier circuit for amplifying an input RF signal with respect to a specified RF output power includes an input terminal for supplying the input RF signal to be amplified, an output terminal for the RF signal with the output power specified, an amplification path formed between the input terminal and the output terminal having a power amplification circuit for amplifying the RF signal, a bypass formed between the input terminal and the output terminal for the RF signal to bypass the amplification path, a control terminal for controlling the operation of the amplification path and the bypass, such that an RF signal is either passed through the amplification path or the bypass.

Abstract: A PAMELA-type of composite power amplifier is configured in such a way that a single power amplifier is operated at low output voltage amplitudes by prohibiting a pair of outphasing power amplifiers to produce any current. Preferably, at output voltage amplitudes above the maximum voltage of the single power amplifier is to be reached, the pair of outphasing power amplifiers is taken into operation providing currents phase shifted by substantially 180 degrees. When also the outphasing power amplifiers reach their maximum voltages, an outphasing operation is performed.

Abstract: A system and method for increasing accuracy of transmitter power detection over a larger range of output power levels wherein a diode detector is followed by a series cascade of 2 op amps. The first op amp functions as a differential/buffer amplifier, which improves temperature performance. The second op amp has two selectable gain factors. The output of the second op amp is routed to the ADC. A single control can is connected to a controllable switching device that configures the second op amp for high gain or low gain.

Abstract: Systems and methods relating to the provision of gain, phase and delay adjustments to signals to be used by a predistortion subsystem. A portion of an input signal is delayed by delay elements prior to being received by the predistortion subsystem. The delayed input signal portion is also received by a feedback signal processing subsystem that adjusts the gain and phase of the feedback signal based on the delayed input signal portion. The adjusted feedback signal is used, along with the delayed portion of the input signal, to determine an appropriate predistortion modification to be applied to the input signal.

Abstract: Described herein are representative embodiments of amplifiers having multiple amplification paths. In certain exemplary embodiments, the amplifiers are operated as linear power amplifiers, such as may be used in wireless communications systems. In one exemplary embodiment, an amplifier circuit is described comprising switchless amplification paths coupled in parallel to one another. In this exemplary embodiment, the amplification paths comprise amplifier sections that are activated substantially exclusively of one another.

Abstract: A calibration circuit for voltage-controlled oscillator (VCO) includes a calibration bias generator, a VCO, a detection unit, a micro control unit, an adjuster unit, a phase-locked loop (PLL) unit, a control voltage detection unit, and a control switch set. The calibration bias generator outputs a first control voltage. The VCO outputs an oscillation frequency according to the first control voltage. The detection unit detects the oscillation frequency and outputs the detection result signal to the micro control unit. The micro control unit outputs an adjust signal according to the detection result signal. The adjuster unit receives the adjust signal voltage and adjusts the oscillation frequency output from the VCO according to the adjust signal voltage. The PLL unit outputs a second control voltage to the VCO. The control voltage detection unit outputs voltage-detection signal to the micro control unit, which outputs the adjust signal according to the voltage-detection signal.

Abstract: A method and apparatus for a low noise low jitter signal source is provided. A Voltage Controlled Oscillator (VCO) is configured as part of a phase locked Loop (PLL) with a reference clock, a loop filter and a method of offsetting the Tune Voltage input to the Voltage Controlled Oscillator (VCO) to achieve low phase noise. A method and apparatus for precisely controlled jitter injection into a high speed data or clock signals is provided. Using IQ modulation techniques comprising an IQ modulator, by synchronously controlling the IQ modulator inputs precisely controlled phase shift for jitter injection are produced. This can also be used with the low noise low jitter signal source described herein.

Abstract: An oscillation frequency control part includes a voltage-to-current converting circuit converting an input voltage to a current having a value corresponding to the input voltage, and outputting a current in proportion to the current obtained from the voltage-to-current converting circuit. An oscillating circuit part includes a ring oscillator, wherein a current in proportion to the output current of the oscillation frequency control part flows through the ring oscillator so that the oscillation frequency in the ring oscillator is controlled by the output current of the oscillation frequency control part. The voltage-to-current converting circuit has linear voltage-to-current conversion characteristics in a predetermined range of the input voltage including a ground potential.

Abstract: In a voltage controlled oscillator, a resonant circuit generates a resonant frequency in response to a tuning voltage. A differential oscillator includes first and second transistors differentially cross-coupled to the resonant circuit. The first and second transistors supply energy to the resonant circuit to oscillate the resonant frequency from the resonant circuit, thereby generating first and second oscillation signals having a phase difference of 180 degree. Also, the first and second transistors adjust the first and second oscillation signals to a uniform level in response to a body bias voltage. In addition, an output level detector detects a level of the first and second oscillation signals from the differential oscillator and supplies the body bias voltage corresponding to the detected level to a body of each of the first and second transistors.

Abstract: A method, apparatus, and a localized in-line cable filter system are provided for implementing electromagnetic cable noise suppression. The localized in-line cable filter system includes at least one electromagnetic interference (EMI) filter element connected between a cable and a current return path. An insulation displacement terminal connects the EMI filter element to the cable. The EMI filter element and current return path provide a low impedance connection toward a source.

Abstract: A duplexer for connection with an antenna comprises an antenna port, a transmitting filter comprising bulk acoustic wave (BAW) resonators having a first antenna side impedance coupled with the antenna port, a receiving filter comprising BAW resonators having a second antenna side impedance coupled with the antenna port, and a shunt inductance coupled between the antenna port and ground. The shunt inductance and the first and second antenna side impedances of the transmitting filter and the receiving filter are selected in such a way that the shunt inductance turns the first and second input impedance in a negative direction in a Smith diagram.

Abstract: A composite filter chip includes a stacked chip made by stacking a first chip and a second chip. The first chip has a first filter circuit formed on the main surface thereof. The second chip has a second filter circuit formed on the main surface thereof.

Abstract: A piezoelectric device includes a piezoelectric substrate having a connection pad, a package having an electrode pad, and a connection member to connect the electrode pad to the connection pad, the connection member being a metal member having a plurality of spherical metal particles connected to each other by sintering.

Abstract: A film acoustically-coupled transformer (FACT) has a first and a second stacked bulk acoustic resonator (SBAR 1, SBAR 2). Each SBAR has a stacked pair of film bulk acoustic resonators (FBARs) and an acoustic decoupler between the FBARs. Each FBAR has opposed planar electrodes and a layer of piezoelectric material between the electrodes. A first electrical circuit connecting one of the FBARs of SBAR1 to one of the FBARs of SBAR 2 and a second electrical circuit connecting the other of the FBARs of SBAR 1 to the other of the FBARs of SBAR 2. The first electrical circuit connects the respective FBARs in parallel and second electrical circuit connects the respective FBARs in series. A shunt inductor is included from the reception path to ground.

Abstract: A multi-layer printed circuit board includes a first conductive layer including at least one conductor pattern and a plated through hole extending into the first conductive layer and intersecting the conductor pattern. A current diverting cutout in the conductor pattern is positioned proximate the intersection of the plated through hole and conductor pattern.

Abstract: A dielectric substrate is provided with first and second conductor openings communicating with each other via a first slit, and third and fourth conductor openings communicating with each other via a second slit, and the slits intersect each other. With this structure two resonant modes including an even mode in which magnetic field vectors are directed from the first to third conductor openings and from the fourth to second conductor openings, and an odd mode in which magnetic field vectors are directed from the third to second conductor openings and from the first to fourth conductor openings, or two resonant modes including an X mode in which magnetic field vectors are directed from the first to second conductor openings, and a Y mode in which magnetic field vectors are directed from the third to fourth conductor openings are generated.

Abstract: An inductive output tube (IOT) operates in a frequency range above 1000 MHz. An output window may be provided to separate a vacuum portion of the IOT from an atmospheric pressure portion of the IOT, the output window being surrounded by a cooling air manifold, the manifold including an air input port and a plurality of apertures permitting cooling air to move from the port, through the manifold and into the atmospheric pressure portion of the IOT. The output cavity may include a liquid coolant input port; a lower circular coolant channel coupled to receive liquid coolant from the liquid coolant input port; a vertical coolant channel coupled to receive liquid coolant from the lower circular coolant channel; an upper circular coolant channel coupled to receive liquid coolant from the vertical coolant channel; and a liquid coolant exhaust port coupled to receive liquid coolant from the upper circular coolant channel.

Abstract: In an embodiment of the invention, a package for high frequency waves mounted by a high frequency electronic circuit comprises an hermetic box-shaped high frequency package containing a high frequency electronic circuit in the inside and shielded by a conductor, an input terminal and an output terminal partly led out to the outside of the high frequency package, an input side feed-through section having one of its opposite ends connected to the input terminal and the other end connected to the high frequency electronic circuit and having a predetermined characteristic impedance; and an output side feed-through section having one of its opposite ends connected to the output terminal and the other end connected to the high frequency electronic circuit and having a characteristic impedance lower than the characteristic impedance of the input side feed-through section as viewed from the output terminal side.

Abstract: A switch includes a first member, one end of which being secured to a substrate, multiple first beam portions respectively having multiple first contact portions, one ends of the multiple beam portions being secured to the first member, multiple contact switch portions connected in parallel, the multiple first contact portions and multiple second contact portions being in a contact state or in a non-contact state in the multiple contact switch portions, and resistors arranged respectively between the multiple contact switch portions and a common connection point to which the multiple contact switch portions are coupled. When at least one of the multiple switch portions is in a contact state, one of the resistors corresponding to the at least one of the multiple switch portions in a contact state has a resistance value greater than another one of the resistors corresponding to at least one of the multiple contact switch portions that is in a non-contact state.

Abstract: Provided is a self-sustaining center-anchor microelectromechanical switch driven by an electrostatic force used for controlling a signal transmission in an electronic system, which can suppress deformation of a movement plane generated during manufacturing and operation process by inserting the self-sustaining center-anchor, and improve a ground line contact phenomenon of an upper electrode, thereby enhancing reliability and signal isolation feature while maintaining an existing insertion loss feature compared to the microelectromechanical switch of the prior art.

Abstract: A tripping device comprises a coil frame, a coil, a plunger, a spring, and an anti-shock device. The coil is fixedly coupled to the coil frame and has a cylindrical channel extending therethrough. The plunger is reciprocatingly received within the cylindrical channel and the spring is structured to bias the plunger within the cylindrical channel. The anti-shock device includes at least one of a number of anti-shock devices structured to eliminate movement of the coil relative to the coil frame and a number of anti-shock devices structured to eliminate movement of the plunger relative to the cylindrical channel. An under-voltage release mechanism comprises a mounting bracket, a tripping device, and an angled support. The mounting bracket includes a first portion and a second portion. The angled support is fixedly coupled to the mounting bracket between the first and second portions and is structured to prevent flexing of the mounting bracket.