Abstract: A circuit for parasitically powering a device comprises diodes, a capacitor, and an inductor all disposed across a signal line, the inductor disposed in series between the diodes and the capacitor. The first diode is preferably a rectification diode, the second diode is preferably a flyback diode, and a DC/DC power supply circuit is preferably disposed across the capacitor. Multiple signal lines are contemplated. The parasitic voltage circuit can include a resistor and a MOSFET in series with the first diode and the inductor, more preferably an impedance control circuit that generates a pulse width modulated signal to actuate the MOSFET, and still more preferably, the impedance control circuit can turn the MOSFET on and off at a rate and duty cycle commensurate with maintaining a relatively constant current from the signal line through rectification diode Ds.

Abstract: A current-source sine-wave voltage inverter for converting a direct current (DC) voltage to an alternating (AC) voltage includes a DC source for providing a DC voltage, a current source circuit having a primary side inductance of a transformer, a clamping circuit, an inverting circuit, and a control and driving circuit. The clamping circuit includes a first switch cascaded with a first diode, a second diode cascaded with a second switch, a first capacitor connected between an anode of the first diode and a cathode of the second diode, a secondary side inductance of the transformer cascaded with a third diode, the secondary side inductance of the transformer and the third diode connected to two ends of the DC source, and a cathode of the third diode connected to an anode of the DC source. The present invention also provides a fuel cell system.

Abstract: A PWM cycloconverter easily capable of improving an input current waveform and regenerating energy of a snubber into a power source is provided. A PWM cycloconverter includes a PWM converter connected to a DC voltage system. An output unit of the PWM converter is connected to a place before an input filter of the PWM cycloconverter to keep down resonance of the input filter.

Abstract: A high-voltage detecting circuit for saving power in a standby mode is provided. The high-voltage detecting circuit includes a high-voltage detecting module, a switch module and a control module. The high-voltage detecting module is composed of several resistors for detecting a high-voltage power supply. A control terminal of the control module is controlled by the power supply to switch off the switch module when the power supply stays at the standby mode, ensuring that the power loss of the high-voltage detecting module is eliminated.

Abstract: The subject invention reveals a method to sample the drain source voltage of a power mosfet synchronous rectifier during its on time using high speed low voltage analog comparators and operational amplifiers. The method relies on a sampling switch such as a small signal level high voltage enhancement mode mosfet that is enabled when the drain source voltage of the power mosfet is near zero volts. The sampling switch isolates and protects the high speed low voltage analog circuit from the high voltages present on the drain of the power mosfet during the off state of the power mosfet.

Abstract: Techniques for high performance inverter charger systems are described herein. In one embodiment, a power supply system includes, but is not limited to, an inverter to generate an AC (alternating current) output based on a DC (direct current) input, a current sensing circuit coupled to the inverter to sense an amount of current drawn from the inverter, and a microcontroller coupled to the inverter and the current sensing circuit to reduce the AC output of the inverter according to a predetermined algorithm stored within the microcontroller, in response to a detection that the amount of current drops below a predetermined threshold. Other methods and apparatuses are also described.

Abstract: A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where a match line is activated and a consistency cancel circuit for forcibly making the match line inactive when a word line and a write instruction signal are both activated. When a write operation and a retrieve operation are simultaneously instructed, a result of the retrieval is forcibly judged to be inconsistent at a write address, thereby it is unnecessary to prohibit the simultaneous execution of the write operation and the retrieve operation.

Abstract: A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; and two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction

Abstract: A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside of the terminal memory mats, and second bit lines are connected according to a folded bit line system to the second sense amplifiers SA2. Two memory cells provided at the points where a word line WL intersects with a pair of bit lines BL, /BL connected to the second sense amplifiers SA2 constitute a twin cell unit TWC for storing a single bit of data in complementary fashion.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: A method and circuit are described for ensuring a properly operational power-up read of fuse cells in a nonvolatile memory by selecting predefined data for loading in a portion of a fuse memory and matching the reading of the predefined data during power-up with the predefined data, thereby indicating a proper power-up read of fuse cells. The fuse memory is partitioned into a first section of fuse cells for conducting a pre-check procedure to match a first predefined data being read against the first predefined data, a second section for reading main fuse cells to match with a second predefined data being read against the second predefined data, and a third section of fuse cells for conducting a post-check procedure to match a third predefined data being read against the third predefined data.

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the-logic block can retain state information while still greatly reducing sub-threshold leakage current.

Abstract: One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a first voltage according to an amount of stored charge. A write assist system is connected between the node and a second voltage. The write assist network is configured, when the node is selected, to discharge the charge storage device and to pull the node from the first voltage to a discharge voltage that is outside a range defined by the first voltage and the second voltage to facilitate setting the latch system to another of the first state and the second state.

Abstract: An object of the present invention is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. The present invention is configured as follows. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

Abstract: A memory device has an information plane (32) for storing data bits in a magnetic state of an electro-magnetic material at an array of bit locations (31). The device further has an array of electro-magnetic sensor elements (51) that are aligned with the bit locations. The information plane (32) is programmable or programmed via a separate magnetic writing device (21). In particular a read-only sensor element (60) is described for a read-only magnetic memory.

Abstract: The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first magnetic moment vector and said second magnetic region being provided with a free second magnetic moment vector which is free to be switched between the same and opposite directions with respect to said fixed first magnetic moment vector of said first magnetic region, a second stacked structure being at least partly arranged in a lateral relationship as to said first stacked structure and comprising a third magnetic region being provided with a fixed third magnetic moment vector and said second magnetic region; wherein said first and second structures being arranged in between at least two electrodes in electrical contact therewith.

Abstract: A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.

Abstract: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.

Abstract: The present invention discloses a method for managing memory blocks in a flash memory. The method is first to calculate the total number of good blocks and total number of bad blocks in the flash memory, and then all the good blocks and the bad blocks will be evenly allocated to each segment according to the number of segments contained in the flash memory. After the allocation, the allocation information will be recorded in one good block to form a data block so that when the flash memory is executing initialization, the controller chip may find the data block, and store the data in the SRAM (static random access memory) of the flash memory. Then, according to the data stored in the SRAM, the controller chip may generate a corresponding table for the block contained in the segment according to the data stored in the SRAM. As a result, the flash memory may be used with lower capacity and may obviate the problem of being unusable when the flash memory contains the excessive amount of the bad blocks.

Abstract: A method of updating data, which is stored in each page in a non-volatile memory with a multi-plane structure, using an external buffer, is provided. In the method, source data that will not be updated in a page in each plane of the non-volatile memory is moved to the external buffer. The source data is loaded from the external buffer to an empty page in each plane and dummy programming is performed. Update data received from a host is randomly inputted to the page to which the source data has been loaded in each plane and programming is performed.

Abstract: A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the first oxide layer relative to the main surface of the semiconductor substrate and a second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.

Abstract: A method for programming a non-volatile memory device includes applying a first dummy voltage to a Multi-Level Cell (MLC). A first program voltage is applied to the MLC to program the MLC, the first program voltage being applied to the MLC after the first dummy voltage has been applied to the MLC. The MLC is verified whether or not the MLC has been programmed correctly by the first program voltage. A second dummy voltage is applied to the MLC after the first dummy voltage has been applied, the second dummy voltage being N volt higher than the first dummy voltage, wherein the second dummy voltage applied to the MLC is of sufficiently low voltage, so that the second dummy voltage does not change an initial state of the MLC. A third dummy voltage is applied to the MLC after the second dummy voltage has been applied, the third dummy voltage being N volt higher than the second dummy voltage.

Abstract: Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.

Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.

Abstract: Disclosed are various embodiments that program a memory array with different carrier movement processes. In one application, memory cells are programmed with a particular carrier movement process depending on the pattern of data usage, such as code flash and data flash. In another application, memory cells are programmed with a particular carrier movement process depending on particular threshold voltage state to be programmed, in a multi-level cell scheme.

Abstract: A method of operating a non-volatile memory comprising a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is bigger than the fourth voltage, the third voltage is bigger than the second voltage, and the second voltage is bigger than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

Abstract: The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Abstract: A system and method for a multi-use eFuse macro is presented. A device includes multiplexers and selection logic that allow eFuse latches to store auxiliary data in addition to programming electronic fuses. The multiplexers and selection logic are coupled to the inputs and outputs of the eFuse latches, and are controlled by a processing unit or an external tester. When a tester wishes to program or update an eFuse element (electronic fuses), the multiplexers and selection logic are configured for “eFuse” mode, which allows an eFuse controller to provide program data and control data to the eFuse latches which, in turn, program the eFuse element. When the device requires additional storage, the multiplexers and selection logic are configured for “auxiliary data” mode, which allows a processing unit to store and retrieve data in the eFuse latches.

Abstract: A data output multiplexer for multiplexing and transferring data of a data input/output (I/O) line includes a first latch unit coupled to the data I/O line to latch the data of the data I/O line, a transmission gate unit to transfer an output of the first latch unit in response to control signals, a second latch unit to latch an output of the transmission gate unit, and a leakage current blocking unit to block leakage current between an input node and an output node of the transmission gate unit by fixing the input node and the output node at the same logic level values during a power down mode or a self refresh mode.

Abstract: In a system of using a plurality of memories with a plurality of CPUs, a plurality of memory arrays are placed on the same memory chip with each memory array being individually provided with a data-related circuit, an address-related circuit and a control-related circuit. These memory arrays however share a data terminal, an address terminal and a control terminal for chip external connection. A data, address and control signals are distributed to the memory arrays via three MUX of signal selection circuits controlled with an array selection signal (clock). A signal is supplied to one memory array at rising timing of the clock while a signal is supplied to another memory array at falling timing of the clock. Thus, in memory integration of placing a plurality of memory arrays on one chip, independent operation for each memory array is attained, and no bus arbitration between CPUs is necessary.

Abstract: A data delivery apparatus including a storage adapted to store limited-access data which associates user data for specifying a user, with data, access to which is permitted or limited to the user; a function determination unit adapted to determine whether a destination device to which the limited-access data is to be transmitted has an access control function of permitting or limiting access to the limited-access data for each user; an authentication unit adapted to, when the limited-access data destination device is determined not to have the access control function, request input of authentication information and performing an authentication process using the input authentication information; and a transmission control unit adapted to, when the authentication process by said authentication unit is successful, transmitting the limited-access data to the destination device.

Abstract: A control selection circuit for a semiconductor device including a pulse generation circuit to delay a first pulse signal by a predetermined delay time to generate a second pulse signal, a frequency information generation circuit to generate a selection signal in response to the second pulse signal, the selection signal indicating an operating frequency of the semiconductor device, and a control circuit to select a control scheme of for the semiconductor device in response to the selection signal.

Abstract: An apparatus for controlling a flash memory and the method thereof are disclosed. The flash memory includes a plurality of blocks which are divided into a plurality of storage blocks and a plurality of spare blocks. The apparatus includes a bad block mapping table and a controller. When a data is to be accessed based on an accessed block address, the controller determines whether the block corresponding to the accessed block address is a damaged block. When the controller determines that the block corresponding to the accessed block address is a damaged block, the controller searches the bad block mapping table based on the accessed block address to find the address of the corresponding spare block for replacing the accessed block address.

Abstract: An embodiment of the present invention relates to a repair circuit of a semiconductor memory device. The repair circuit includes an address counter that sequentially generates a first column address signal and a second column address signal in response to a write enable signal or a read enable signal, a repair controller that generates a repair column address signal earlier than the second column address signal in response to the first column address signal, an address latch enable signal, a command enable signal, and a write enable signal, and a repair scramble unit that selects a repair cell in response to a repair I/O control signal and the repair column address signal. If an address on which a repair operation must be performed occurs, the repair controller directly receives the write enable signal or the read enable signal and activates the repair controller earlier than a general cell using a previous address, thereby offsetting an operating time consumed in the repair controller.

Abstract: A second roll call test mode is added in addition to a first roll call test mode for checking use/nonuse of a redundancy circuit. A semiconductor memory device is capable of confirming program states of an enable fuse and each address fuse by providing with a logic circuit which blocks program information of the enable fuse by using a second test mode signal.

Abstract: A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state.

Abstract: Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Abstract: An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to be programmed, a first programming current is applied to a first eFuse to thereby increase the resistance of the first eFuse by an incremental amount. When the pair of eFuses is to be returned to an unprogrammed state, a second programming current source is applied to a second eFuse to thereby increase a resistance of the second eFuse to be greater than the resistance of the first eFuse. When the sensing current is applied to the eFuses, a difference in the resulting voltages across the eFuses is identified and used to indicate whether the reprogrammable eFuse is in a programmed state or unprogrammed state.

Abstract: Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.

Abstract: A multi-chip semiconductor memory device may comprise of a plurality of memory chips sharing a predetermined chip enable signal. Each of the plurality of memory chips may comprise of an active internal power supply generation circuit configured to convert an external power supply voltage into an internal power supply voltage and to be disabled in response to deactivation of a predetermined drive control signal. Each of the plurality of memory chips may also comprise of a conversion control circuit for generating the drive control signal, wherein the drive control signal is deactivated in an interval in which any of the plurality of memory chips is in an active interval.

Abstract: A method for reducing power in an SRAM is achieved by applying a first voltage to all bitlines of a section of the SRAM in standby operation and applying a second voltage to all the bitlines of a section of the SRAM in normal operation. The first voltage is not greater than the second voltage.

Abstract: A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

Abstract: Provided are an apparatus and method for preventing a dual port memory full in a mobile communication terminal with multi processors. The apparatus includes an auxiliary processor having a buffer and storing data in the dual port memory, a main processor having a memory processing module and a buffer and loading the data of the dual port memory, and the dual port memory into which the data from the auxiliary processor and the main processor are loaded. When the dual port memory is used as data exchange units of the multi processors, the synchronization collapse can be prevented, thereby providing the smooth services.

Abstract: An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address, a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection, an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address, and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address.

Abstract: The system for on-circuit asynchronous communication, between synchronous subcircuits, includes a first synchronous subcircuit regulated by a first clock frequency, which sends requests to a second synchronous subcircut regulated by a second clock frequency. The first subcircuit transmits data to the second subcircuit through a first mesochronous unidirectional communication link, and the second subcircuit transmits availability tokens which report the availability of an additional elementary memory location in the queue situated at the extremity of the first mesochronous unidirectional communication link to the first subcircuit, via a second mesochronous unidirectional communication link. The first subcircuit comprises means of transmission for directly transmitting to the second subcircuit data of a size that is at most equal to the size corresponding to the elementary memory locations available in the queue.

Abstract: An electronically operated whisk mechanism. Such whisk mechanism including a wire frame mixing portion having each of a first predetermined length and a predetermined number of wires. A generally hollow handle portion has a portion of the wire frame extending into a first end thereof. The generally hollow handle portion having a second predetermined length. There is a motor disposed in the generally hollow handle portion and connected to that portion of such wire frame mixing portion which extends into such first end of such generally hollow handle portion for causing rotation of the wire frame mixing portion. A power source is electrically connected to the motor and a switch is connected between the power source and such motor for controlling power to such motor.

Abstract: An improved paint mixer of the type rotating a paint container about a tumbling axis and a perpendicular spin axis, the improvements of a clamp assembly and lock, splash guards protecting a range-of-travel of upright clamp portions, low friction guide plates, an adjustable height strike plate and roller, a rigid gear assembly, an offset in the clamp to return the paint container to an upright position after mixing, and a relief in a raised portion on a lower plate of the clamp for assisting loading and unloading of the paint container.