Patents Issued in April 19, 2007
  • Publication number: 20070085170
    Abstract: A single crystalline a-plane nitride semiconductor wafer includes one to three orientation flats in a crystalline direction, wherein a-plane ({11-20} plane) is formed as a main plane. Since plane orientation can easily be recognized, accuracy can be improved when a semiconductor device is formed on the nitride semiconductor wafer.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 19, 2007
    Inventors: Hyun Shin, Ki Lee
  • Publication number: 20070085171
    Abstract: A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Patricio Ancheta, Ramil Viluan, James Baello, Elaine Reyes
  • Publication number: 20070085172
    Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.
    Type: Application
    Filed: December 8, 2006
    Publication date: April 19, 2007
    Inventor: Yu-Hao Hsu
  • Publication number: 20070085173
    Abstract: A method and apparatus for providing double-sided cooling of leadframe-based wire-bonded electronic packages. The method includes the steps of: positioning a plurality of heatslug members (140) over a corresponding plurality of electronic packages (100?) formed on a leadframe strip (142), wherein each of the heatslug members includes a heatslug (130) and a plurality of legs (144) for supporting the heatslug over a respective one of the electronic packages; introducing a molding compound (132) between each heatslug member and its respective electronic package; curing the molding compound; and cutting the heatslug members and separating the electronic packages (100) from the leadframe strip, such that each electronic package includes a heatslug for cooling a first side of the electronic package.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 19, 2007
    Inventor: Xuejun Fan
  • Publication number: 20070085174
    Abstract: An integrated circuit packaging apparatus includes a first conductive layer disposed between an integrated circuit die and a conductive die paddle. Bond wires connect the first conductive layer to the lead frame package and to the integrated circuit die. A first dielectric layer is disposed between the first conductive layer and the conductive die paddle such that the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance. A method for providing bypass capacitance and power routing for an integrated circuit packaging apparatus includes; depositing a first dielectric layer on a conductive die paddle, depositing a first conductive layer on the first dielectric layer, and connecting the first conductive layer to the lead frame package and to the integrated circuit die. The first conductive layer, the first dielectric layer, and the conductive die paddle cooperate to provide bypass capacitance.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Thomas Omega Wheless, Randall Don Briggs
  • Publication number: 20070085175
    Abstract: A nano-sized solder suspension flows by selective wetting onto a bond pad and away from a bond-pad resist area. A microelectronic package is also disclosed that uses the nano-sized solder suspension. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes a bump that was reflowed from the nano-sized solder suspension.
    Type: Application
    Filed: November 22, 2006
    Publication date: April 19, 2007
    Inventors: Daoqiang Lu, Tian-An Chen
  • Publication number: 20070085176
    Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.
    Type: Application
    Filed: February 10, 2006
    Publication date: April 19, 2007
    Inventors: Wu-Chang Tu, Geng-Shin Shen
  • Publication number: 20070085177
    Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 19, 2007
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD
    Inventors: Kum-weng Loo, Chek-lim Kho, Jing-en Luan
  • Publication number: 20070085178
    Abstract: A conductor substrate for mounting a semiconductor element, at least a portion thereof mounting the semiconductor element being sealed with an insulating resin, wherein an uppermost surface layer of the conductor substrate comprises copper or an alloy thereof, and the conductor substrate is partly or entirely covered with a layer of copper oxide containing a hydroxide formed upon the surface treatment of the conductor substrate and a process of producing the conductor substrate as well as a process for the production of a semiconductor device using the conductor substrate.
    Type: Application
    Filed: December 4, 2006
    Publication date: April 19, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kazumitsu Seki, Yoshihito Miyahara, Muneaki Kure
  • Publication number: 20070085179
    Abstract: A plastic lead frame, electrical component system, and method using plastic-injection, plating, and known photolithography techniques are disclosed. The plastic lead frame and electrical component system operates with an integrated circuit, which functions as a sensor, such as an automotive gear tooth sensor. The plastic lead frame includes electrical contacts that serve as a linkage between the sensor and at least one electrical power source. In addition, the plastic lead frame may be constructed from granular or pelletized raw plastic or recycled components.
    Type: Application
    Filed: August 8, 2005
    Publication date: April 19, 2007
    Inventor: Stephen Shiffer
  • Publication number: 20070085180
    Abstract: A package for semiconductor image pickup device is provided. The package is fabricated by using flip chip bumping. During deposition process of forming a metallic bonding layer and a metal layer for plating, a surface of a semiconductor image pickup device is maintained at the range between room temperature and 200° C. in accordance with a first embodiment. A polymer layer for preventing stress from generating can absorb stress generated during the deposition process in accordance with a second embodiment. According to the present invention, a functional polymer layer on the surface of a semiconductor image pickup device can be prevent from being deteriorated in its properties and from transforming at its surface.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 19, 2007
    Applicant: NEPES CO., LTD.
    Inventors: Jong-Heon Kim, Chi-Jung Song
  • Publication number: 20070085181
    Abstract: A power semiconductor module having at least one fuse. The power semiconductor module comprises a housing, load terminal elements that lead outside of the housing, and a substrate disposed inside the housing with a plurality of metal connecting tracks of different polarity electrically insulated from one another. On at least one of these connecting tracks, at least one power semiconductor component is disposed and is connected correctly in terms of circuitry to first connecting elements that have a first line cross section. The fuse comprises a second connecting element that has a second line cross section, less than the first, and is disposed between two connecting tracks and/or between a connecting track and a load terminal element. The second connecting element is sheathed in one portion by an explosion protection means.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 19, 2007
    Inventors: Christian Kroneder, Uwe Scheuermann, Dejan Schreiber
  • Publication number: 20070085182
    Abstract: A semiconductor device includes a semiconductor chip having a plurality of electrode pads, and a rewiring pattern having a plurality of interconnects which are connected to the electrode pads and extend over an insulation film. The semiconductor device also includes a plurality of columnar electrodes each of which has a main body section and a protrusion section, and a sealing section which has a top face having a height the same as the top faces of the protrusion sections. The semiconductor device also includes solder balls formed on the protrusion sections. The semiconductor device also has a plurality of trenches in the sealing section. Each trench has a depth which reaches the boundary between the main body and protrusion of the electrode. The side faces of the protrusion section are exposed face defined by the trenches. Each solder ball is electrically connected to the top face and side faces of the protrusion section of each electrode.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 19, 2007
    Inventor: Tadashi Yamaguchi
  • Publication number: 20070085183
    Abstract: An integrated circuit is provided. The integrated circuit comprises a plurality of electrode pads that are exposed through openings of a surface protective layer. An NG identification marker is attached to the integrated circuit. An NG marker pad is separate from the plurality of electrode pads and exposed through an opening of the surface protective layer so as to specify a position at which the NG identification marker is placed.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 19, 2007
    Applicant: ALPS ELECTRIC CO., LTD.
    Inventors: Tsutomu Takeya, Shuichi Usami
  • Publication number: 20070085184
    Abstract: A substrate is provided. A first die is placed on the substrate. A film spacer is attached to the first die and a second die is placed on the film spacer. The substrate, the first die, the film spacer, and the second die are encapsulated in an encapsulant.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyeog Kwon, Hee Lee
  • Publication number: 20070085185
    Abstract: A stacked arrangement of integrated circuit chips are bonded to a lead frame. Two side-by-side integrated circuit chips have bottom contact pads bonded to a lead frame structure having contact terminals. The two side-by-side integrated circuits have top contact pads bonded to an overlying integrated circuit chip. A low profile integrated circuit assembly is achieved without using bond wires or preforms, and which is well adapted for SO-8 packages.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventor: Chad Vos
  • Publication number: 20070085186
    Abstract: A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected to the substrate through the bonding wires. The second chip is disposed above the first chip, and it has second bonding pads disposed on an active surface thereof. The second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventor: Geng-Shin Shen
  • Publication number: 20070085187
    Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.
    Type: Application
    Filed: December 22, 2005
    Publication date: April 19, 2007
    Inventors: Ming Sun, Yueh Ho
  • Publication number: 20070085188
    Abstract: A stack structure of a carrier board embedded with semiconductor components and a method for fabricating the same are proposed. The stack structure includes first and second carrier boards having a through hole respectively, first and second semiconductors component disposed in through holes of the first and second semiconductor components respectively, and a dielectric layer structure clamped between the first carrier board and the second carrier board and having a first dielectric layer formed on the first carrier board and an inactive surface of the first semiconductor component and filled in gaps between the first carrier board and the first semiconductor component, a second dielectric layer formed on the second carrier board and an inactive of the second semiconductor component and filled in gaps between the second carrier board and the second semiconductor component, and a bonding layer clamped between the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: August 25, 2006
    Publication date: April 19, 2007
    Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATION
    Inventors: Chia Chang, Chung Lien
  • Publication number: 20070085189
    Abstract: A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an electrode pad disposed on the first principal surface of the semiconductor substrate and electrically connected to the semiconductor device, a through via formed in a through hole penetrating through the semiconductor substrate and the electrode pad, and an Au bump deposited on the electrode pad and the through via such as to electrically connect between the electrode pad and the through via.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 19, 2007
    Inventors: Masahiro Sunohara, Mitsutoshi Higashi
  • Publication number: 20070085190
    Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.
    Type: Application
    Filed: November 8, 2006
    Publication date: April 19, 2007
    Inventors: Robert VINSON, Joseph Brief, Donald Beck, Gregory Jandzio
  • Publication number: 20070085191
    Abstract: A lead pin of a circuit includes a pin, an insulator that surrounds the pin, and a conductor that surrounds the insulator, the conductor including non-uniformity.
    Type: Application
    Filed: July 13, 2006
    Publication date: April 19, 2007
    Applicant: NEC SYSTEM TECHNOLOGIES, LTD.
    Inventors: Yasushi Nobutaka, Hiroshi Kamiya
  • Publication number: 20070085192
    Abstract: A semiconductor component includes a substrate with an active side that includes connection regions disposed thereon. A die includes an upper metallization layer disposed over an upper surface. Integrated circuitry is disposed at the upper surface of the die and a passive side of the die is disposed on the active side of the substrate. The die includes exposed metal patterns at the level of its upper surface side. The exposed metal patterns are deformed in such a way that ends of the exposed metal patterns are connected to the connection regions of the substrate.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 19, 2007
    Inventor: Peter Poechmueller
  • Publication number: 20070085193
    Abstract: Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 19, 2007
    Inventor: Kazuhiro Kashiwakura
  • Publication number: 20070085194
    Abstract: A dielectric composite material containing a toughened benzocyclobutene resin and at least about 50% by weight of an inorganic filler. Also electronic packages having at least one conductive layer and at least one layer of the dielectric composite material. The dielectric composite material can have a dielectric constant less than about 3.5, and a dielectric loss of less than about 0.004.
    Type: Application
    Filed: November 9, 2006
    Publication date: April 19, 2007
    Inventors: Guoping Mao, Shichun Qu, Fuming Li, Robert Clough, Nelson O'Bryan
  • Publication number: 20070085195
    Abstract: A wafer level packaging cap for covering a device wafer with a device thereon and a fabrication method thereof are provided. The method includes operations of forming a plurality of connection grooves on a wafer, forming a seed layer on the connection grooves, forming connection parts by filling the connection grooves with a metal material, forming cap pads on a top surface of the wafer to be electrically connected to the connection parts, bonding a supporting film with the top surface of the wafer on which the cap pads are formed, forming a cavity on a bottom surface of the wafer to expose the connection parts through the cavity, and forming metal lines on the bottom surface of the wafer to be electrically connected to the connection parts.
    Type: Application
    Filed: March 2, 2006
    Publication date: April 19, 2007
    Inventors: Moon-chul Lee, Jong-oh Kwon, Woon-bae Kim, Ji-hyuk Lim, Suk-jin Ham, Jun-sik Hwang, Chang-youl Moon
  • Publication number: 20070085196
    Abstract: A light emitting diode (LED) package is provided. The LED package comprises a first lead, a second lead, a heat dissipater, a housing, a conductor and an LED chip. The dissipater is disposed between the first lead and the second lead. The housing covers the heat dissipater and parts of the first lead and the second lead. The housing has an upper surface that exposes the heat dissipater, the first lead and the second lead. The conductor is connected between the first lead and the heat dissipater. The LED chip further has a first surface and a second surface, which are oppositely disposed, wherein the second surface is disposed on the heat dissipater. The Led chip is electrically connected to the first lead and the second lead.
    Type: Application
    Filed: August 17, 2006
    Publication date: April 19, 2007
    Applicant: CORETRONIC CORPORATION
    Inventors: Tung-An Chen, Chung-Min Chang, Chih-Cheng Huang, Liang-Chih Lee
  • Publication number: 20070085197
    Abstract: A semiconductor insulation structure is disclosed for a semiconductor module, incorporating therein a semiconductor element, with which an electrically conductive structural body is held in pressured contact via an intervening insulation member. The semiconductor insulation structure includes a deformation preventing structure to avoid the insulation member from deforming when applied with load thereto. In one aspect, the deformation preventing structure includes a deformation resistant abutment surface, formed on the semiconductor module, and a readily deforming abutment surface formed on the electrically conductive structural body. In another aspect, the deformation preventing structure includes a reinforcement formed on a cooler and held in contact with the insulation member in an area placed in opposition to an outer circumferential periphery of the semiconductor module.
    Type: Application
    Filed: October 13, 2006
    Publication date: April 19, 2007
    Applicant: DENSO CORPORATION
    Inventors: Hiroaki Arai, Takahiro Ogawa, Mitsuharu Inagaki
  • Publication number: 20070085198
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Inventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing Zhou, Jiangqi He
  • Publication number: 20070085199
    Abstract: An integrated circuit package system includes a conductive substrate. A heat sink and a plurality of leads are etched in the substrate to define a conductive film connecting the heat sink and the plurality of leads to maintain their spatial relationship. A die is attached to the heat sink and wire bonded to the plurality of leads. An encapsulant is formed over the die, the heat sink, and the plurality of leads. The conductive film is etched away to expose the encapsulant and the bottom surfaces of the heat sink and the plurality of leads. Wave soldering is used to form solder on at least the plurality of leads. Multiple heat sinks and hanging leads are provided.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: You Yang Ong, Cheong Chiang Ng, Suhairi Mohmad
  • Publication number: 20070085200
    Abstract: A substrate for power decoupling and a method of forming a substrate for power decoupling. The substrate comprises one or more decoupling capacitors; and one or more interconnections to the decoupling capacitors. At least one of the interconnections comprises a lossy material.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Inventors: Chee Lu, Boon Lok, Sunappan Vasudivan
  • Publication number: 20070085201
    Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 19, 2007
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
  • Publication number: 20070085202
    Abstract: With respect to a semiconductor device which communicates data by wireless communication, an object of the present invention is to improve sensitivity of an antenna and to protect a chip from noise without increasing the size of the device. A coiled antenna and a semiconductor integrated circuit which is electrically connected to the coiled antenna are included. The semiconductor integrated circuit is arranged so as to overlap with the coiled antenna In this manner, arrangement of the coiled antenna and the semiconductor integrated circuit in the semiconductor device is devised, so that sensitivity of the antenna can be improved and power enough to operate the semiconductor integrated circuit can be obtained without increasing the size of the device.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 19, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Publication number: 20070085203
    Abstract: A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided on the upper surface of the low-elasticity layer 40 and connected to an IC chip 70 via solder bumps 66, and conductor posts 50 that penetrate through the low-elasticity layer 40 and electrically connect the lands 52 to the conductor pattern 32. The low-elasticity layer 40 is formed of resin composition containing epoxy resin, phenol resin, cross-linked rubber particles and a hardening catalyst.
    Type: Application
    Filed: November 27, 2006
    Publication date: April 19, 2007
    Applicants: IBIDEN CO., LTD., JSR CORPORATION
    Inventors: Takashi Kariya, Toshiki Furutani, Hirofumi Goto, Shin-ichiro Iwanaga
  • Publication number: 20070085204
    Abstract: A semiconductor device includes at least one macro-cell device, the macro-cell device comprising a plurality of LDMOS devices. A first conductive layer is formed over the substrate, the first conductive layer providing source and drain contacts for the macro-cell device. A first isolation layer is formed over the first conductive layer and a second conductive layer is formed over the first isolation layer, the second conductive layer forming a drain bus and a source bus, wherein the buses are electrically coupled to the contacts through the first isolation layer. A second isolation layer is formed over the second conductive layer and insulates the source bus from the drain bus. A plurality of conductive bumps are formed over the second isolation layer, at least one of the conductive bumps directly contacting the drain bus and at least one of the conductive bumps directly contacting the source bus through the second isolation layer.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Jacek Korec, Shuming Xu, Wenhua Dai
  • Publication number: 20070085205
    Abstract: A semiconductor device with electroless plating metal connecting layer and a method for fabricating the same are proposed. A supporting board with at least one cavity is provided. At least one semiconductor chip with a plurality of copper electrode pads is received in the cavity and an insulating protecting layer is formed on the semiconductor chip. A plurality of holes is formed in the insulating protecting layer to expose the copper electrode pads. An electroless plating metal connecting layer is formed on the copper electrode pads by electroless plating. Therefore, the electrically connecting process of the semiconductor chip is simplified and easily practiced, and the fabrication cost is reduced.
    Type: Application
    Filed: August 24, 2006
    Publication date: April 19, 2007
    Inventors: Shang-Wei Chen, Zhao-Chong Zeng, Chung-Cheng Lien, Shih-Ping Hsu
  • Publication number: 20070085206
    Abstract: A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.
    Type: Application
    Filed: November 27, 2006
    Publication date: April 19, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: MIN-CHIH HSUAN, Kai-Kuang Ho, Kuo-Ming Chen, Kuang-Hui Tang
  • Publication number: 20070085207
    Abstract: A pad structure, a method of forming a pad structure, a semiconductor device having a pad structure and a method of manufacturing a semiconductor device are disclosed. The pad structure may include a first pad, a second pad, a third pad and/or a spacer. The first pad may contact a contact region on a substrate. The first pad may include doped polysilicon. The second pad may contact the first pad. The second pad may include a metal silicide or a metal silicongermanium. The third pad may contact the second pad. The third pad may include a conductive material (e.g., doped polysilicon, a metal or a metal nitride). The spacer may be formed on sidewalls of the second and the third pads.
    Type: Application
    Filed: August 2, 2006
    Publication date: April 19, 2007
    Inventors: Woo-Sung Lee, Young-Wook Park, Nam-Kyu Kim, Bong-Hyun Kim, Man-Sug Kang
  • Publication number: 20070085208
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV-absorption layer at least between the first and the second porous low-k layers.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Jim-Jey Huang, Jei-Ming Chen
  • Publication number: 20070085209
    Abstract: An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Inventors: David Lu, Horng-Huei Tseng, Syun-Ming Jang
  • Publication number: 20070085210
    Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.
    Type: Application
    Filed: January 26, 2006
    Publication date: April 19, 2007
    Inventors: Feng-Yu Hsu, Chih-Chien Liu, Chun-Chieh Huang, Jei-Ming Chen, Shu-Jen Sung
  • Publication number: 20070085211
    Abstract: A second interlayer insulating film is formed on a first interlayer insulating film and a wiring including a Cu film, and a via and a trench are formed in the second interlayer insulating film so as to expose the Cu film. After a hollow having an inner diameter larger than that of the via is formed in the Cu film, a first barrier metal film is formed. Subsequently, the first barrier metal film is re-sputtered to fill the hollow with the first barrier metal film and to extend the via so as to have a rounded lower part. Next, a second barrier metal film and a Cu film are formed sequentially in the via and the trench. Then, the Cu film, the second barrier metal film, and the first barrier metal film on the second interlayer insulating film are removed.
    Type: Application
    Filed: July 11, 2006
    Publication date: April 19, 2007
    Inventor: Masakazu Hamada
  • Publication number: 20070085212
    Abstract: A dielectric composite material containing a toughened benzocyclobutene resin and at least about 50% by weight of an inorganic filler. Also electronic packages having at least one conductive layer and at least one layer of the dielectric composite material. The dielectric composite material can have a dielectric constant less than about 3.5, and a dielectric loss of less than about 0.004.
    Type: Application
    Filed: November 9, 2006
    Publication date: April 19, 2007
    Inventors: Guoping Mao, Shichun Qu, Fuming Li, Robert Clough, Nelson O'Bryan
  • Publication number: 20070085213
    Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.
    Type: Application
    Filed: December 14, 2006
    Publication date: April 19, 2007
    Inventors: Kie Ahn, Leonard Forbes
  • Publication number: 20070085214
    Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 19, 2007
    Inventors: Satoshi Isa, Mitsuaki Katagiri, Toru Chonan, Shigeyuki Nakazawa
  • Publication number: 20070085215
    Abstract: Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 19, 2007
    Inventors: Russell Budd, Punit Chiniwalla, Chirag Patel
  • Publication number: 20070085216
    Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 19, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Michael Bauer, Edward Fuergut
  • Publication number: 20070085217
    Abstract: A mounting board on which a semiconductor chip having multiple connection bumps is to be mounted by flip-chip bonding is disclosed. The mounting board includes multiple connection pads to be electrically connected to the corresponding connection bumps, where the connection pads have respective surfaces coated with solder; and an insulating layer configured to surround the connection pads and isolate the connection pads from each other. Each of the connection pads has a first region and at least one second region to be connected to a corresponding one of the connection bumps. The first region has a surface substantially as high as a surface of the insulating layer and the second region has a surface lower than the surface of the first region.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 19, 2007
    Inventor: Haruo Sorimachi
  • Publication number: 20070085218
    Abstract: A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
    Type: Application
    Filed: November 24, 2006
    Publication date: April 19, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Wen Chen, Chih-Ming Chung, Chi-Hao Chiu
  • Publication number: 20070085219
    Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduce, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.
    Type: Application
    Filed: November 20, 2006
    Publication date: April 19, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Gu-Sung Kim