Abstract: A multimeter includes a body portion, a cover pivotally connected to the frame such that the cover is selectively moveable about a rotational axis between an open position and a closed position, and a probe assembly including a pair of measuring lines connectable to the frame. The cover includes a magnetic portion on an exterior surface thereof that is configured and positioned to magnetically mount the body portion for use in an inclined relation to a metal surface when the cover is in the open position, and to magnetically mount the body portion to a metal surface when in the closed position.

Abstract: A RF and pulse bias tee for use with a source measure unit (SMU) includes a SMU source terminal; a SMU measure terminal; an output terminal; a SMU measure terminal pulse/RF block between the SMU measure terminal and the output terminal; a SMU source terminal high frequency block having two end nodes and an intermediate node, the end nodes being connected between the SMU source terminal and the output terminal; a RF input; a pulse/DC block between the RF input and the output terminal; a pulse input; and a DC block between the pulse input and the intermediate node.

Abstract: A magneto impedance sensor element with electromagnetic coil comprised of: a terminal board on which an extended groove which extends in one direction has been formed; an electromagnetic coil, made with one part of the coil formed in a spiral shape inside the extended groove in the terminal board, and joined to each tip of that coil the other part of the coil placed across the top of the groove; insulating material placed in the extended groove on the terminal board; and a magnetic sensitive body inserted within the insulating material, to which either high frequency or pulse electic current is applied. When either high frequency or pulse electrical current is applied to the magnetic sensitive body, voltage is output from the above electromagnetic coil in response to the intensity of the external magnetic field which is generated in the electromagnetic coil.

Abstract: System and methods for estimating properties of a geologic formation are disclosed. A preferred embodiment includes a method for estimating properties of a geologic formation, comprising the steps of: measuring a property of the formation in two or more directions along a path in the formation; obtaining directional property values for at least one spatial unit along the path in the formation based on the property measurements; and providing an anisotropy estimate of the formation from the obtained directional property values.

Abstract: A first pulse sequence is executed on an imaging portion of an object to be examined using a multiple receiving coils including a plurality of receiving coils to obtain sensitivity images 701 to 703, each of n in number, which is smaller than the number of examination image. When those sensitivity images are calculated, NMR signals are measured only in a low-frequency region of a k space. Next, a second pulse sequence is executed while phase encoding steps are thinned out to acquire examination images 704 and 705, each of m in number (m>n), of the object with each receiving coil.

Abstract: The invention enables to monitor a magnetic field drift of a magnetic resonance imaging apparatus on the basis of the magnetic resonance signals, which are acquired during magnetic resonance image data acquisition, such as by single shot EPI or by a gradient echo sequence. The phases of at least two magnetic resonance signals are acquired an echo time after the corresponding RF excitations. This corresponds to the central k-space line, which has frequency encoding but no phase encoding. The difference of two consecutive phase measurements, which are acquired at a certain time interval provides the shift of the resonance frequency. This enables monitoring of the shift of the resonance frequency and compensation of the magnetic field drift.

Abstract: For generating of magnetic resonance exposures of an examination subject, a dielectric element with high dielectric constant is positioned on the examination subject to locally influence the B1 field distribution, the dielectric element being formed primarily of material whose magnetic resonance line(s) is/are shifted by at least a specific degree relative to the magnetic resonance line of water protons for a given magnetic field. In a measurement for generation of a magnetic resonance exposure a measurement sequence is used, such in the acquisition of the raw image data the dielectric material of the dielectric element supplies no signal contributions for the image generation and/or the signals caused by the dielectric material of the dielectric element can be separated from the signals caused by the examination subject.

Abstract: The invention relates to an MRI system (1) comprising an examination volume (11), a main magnet system (13) for generating a main magnetic (field (B0) in the examination volume, a gradient magnet system (19) for generating gradients of the main magnetic field, and an anti-vibration system (39) for reducing vibrations of the gradient magnet system. According to the invention the anti-vibration system comprises a gyroscope (41) which is mounted to the gradient magnet system. As a result of the gyroscopic effect of the gyroscope, the vibrations of the gradient magnet system are effectively reduced. In an open type MRI system (1) according to the invention, a separate gyroscope (41, 43) is mounted to each of the two portions (21, 23) of the gradient magnet system (19), and each gyroscope has an axis of rotation (61) parallel to the main direction (Z) of the main magnetic field (B0).

Abstract: A magnetic field generating apparatus for use in magnetic resonance imaging (MRI) is disclosed. The apparatus includes an annular magnet field generator defining a patient bore, a gradient coil disposed between the magnetic field generator and the patient bore, a first set of shim elements, and a second set of shim elements. The patient bore has an imaging volume, a z-axis, and an isocenter. The first set of shim elements are disposed at a region between the magnetic field generator and the imaging volume, and the second set of shim elements are disposed at the region at a location having equal to or greater than a specified Z/R ratio, where Z defines an axial distance from the isocenter and R defines a radial distance from the z-axis.

Abstract: In accordance with various embodiments, there is a method for determining the specific gravity of a battery. Various embodiments include the steps of applying an increasing current ramp to a battery and measuring a response voltage of the battery when the increasing current ramp is applied to the battery. When the current ramp reaches a predetermined current a decreasing current is supplied to the battery and the battery's voltage response is measured. The specific gravity of the battery can be determined based on the voltage response of the battery to the applied current ramp.

Abstract: A method and apparatus for detecting shorts between accessible and inaccessible signal nodes (e.g., integrated circuit pins) of an electrical device (e.g., an integrated circuit), using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible node under test is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to at least one of the accessible node and inaccessible node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a signal present on the at least one of the accessible node and inaccessible node of the electrical device. Based on the value of the capacitively sensed signal, a known expected “defect-free” capacitively sensed signal measurement and/or a known expected “shorted” capacitively sensed signal measurement, one can determine whether a short fault exists between the accessible node and inaccessible node of the electrical device.

Abstract: A method and system for detecting whether an antenna is property connected to a distributed antenna network. The current drawn by the antenna is measured and compared against an expected current draw or reference level. The measured level of current drawn by the antenna is indicative of whether the antenna is properly connected or is disconnected. The comparison results may be used as the basis for creating a status message, which is then communicated to a central monitoring unit for each antenna. The central monitoring unit may generate appropriate alarms in response to a status message indicating a fault condition at a particular antenna.

Abstract: An inverter output current detection device is provided which can calculate an output current of an inverter easily by using a low-performance calculating device without lowering a calculation accuracy. A current ic? equivalent to a capacitor current ic is digitally calculated according to a predetermined expression. This expression is ic?=V×?0×C×[cos Wavedata]×K, where V is an effective value or average value of an output voltage vo, C is a capacitance of a capacitor C, ?0 is an angular frequency of the output voltage, and K is a value obtained by multiplying a detection ratio for detecting the output voltage vo, a conversion ratio for converting an analog value into a digital value, and a conversion ratio for converting the effective value or average value V into a maximum value.

Abstract: A system for shielding an engine component of an equipment service vehicle including an enclosure, wherein the enclosure includes a surface having a plurality of apertures formed in the surface of the enclosure, the plurality of apertures being dimensioned to minimize electromagnetic emissions from the engine component of the equipment service vehicle.

Abstract: An apparatus and a method for electrically testing a microelectronic product employ an electrical probe tip for electrically stressing a portion of the microelectronic product other than an electrical contact portion of the microelectronic product when electrically testing the microelectronic product. The apparatus and the method provide for more accurate and efficient electrical testing of the microelectronic product.

Abstract: This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. A wafer level test system uses an optical probe to search for and align with an optical alignment loop. The test system uses a located alignment loop as a reference point to locate other devices on the wafer. The test system tests the operation of selected devices disposed on the wafer. The alignment loop is also used as a reference device for an adjacent device of unknown performance.

Abstract: A probe mark reading device for reading probe marks stormed on electrode pads of semiconductor chips contained in a semiconductor wafer (90), comprising a CCD camera (20) for taking an image of the semiconductor wafer (90) and outputting the image as an image signal Si, an optical unit (21) for optically enlarging a location to be photographed by the CCD camera (20), a light source (30) for illuminating the location to be photographed by the CCD camera (20) with a flash of light generated for a short period of time from when a flash signal Sf is provided, an X-Y stage (40) capable of changing a position to be photographed by the CCD camera (20) based on a motor control signal Sm by moving a mounted semiconductor wafer (90) in an X-direction and a Y-direction, and a computer (10) for providing control and saving the images after receiving and trimming the image signal Si. With the above configuration, it is possible to read probe marks in a short time without a user having to expend much time or effort.

Abstract: A plurality of chip regions are defined over a surface of a semiconductor substrate and separated from one another by a scribe region. A plurality of main pads are disposed in the chip regions and a test element group is disposed at the scribe region. The test element group is electrically connected to the main pads through interconnections.

Abstract: An apparatus and method for determining the presence or absence in a motor lock error in a sensorless motor. The method includes the steps of: driving the sensorless motor; determining whether or not a predetermined time elapses after the sensorless motor has been driven; measuring a current applied to the sensorless motor after the lapse of the predetermined time; calculating a difference between the measured current with a predetermined reference current; and determining the presence or absence of a motor lock error in the sensorless motor by determining whether the determined difference is equal to or higher than a predetermined reference difference, so that it quickly determines the presence or absence of a motor lock error in the sensorless motor without using a sensor and prevents an overcurrent from flowing in the sensorless motor, resulting in the prevention of a faulty operation or damage to the sensorless motor.

Abstract: By adding redundant logic gates into a circuit without changing function of the whole circuit, the present invention can tolerate certain delay variations. The present invention can be applied in the IC industries to improve the yield in semiconductor manufacturing.

Abstract: The present invention relates to an apparatus for adjusting a slew rate of a data signal outputted by a signal from an external circuit in a semiconductor memory device and a method therefor. The apparatus includes: a slew rate control signal generation block for outputting a plurality of slew rate control signals through combining control codes inputted from the external circuit in response to a command signal; and a data buffer for adjusting a slew rate of a data signal inputted by using the slew rate control signals.

Abstract: A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output.

Abstract: Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for reconfigurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency. The reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.

Abstract: A configuration for a programmable device is determined to implement an incomplete function using at least two logic cells. Function inputs are partitioned into portions associated with first and second logic cells. The partitioning is screened to determine if it is potentially acceptable by determining if a portion of the function can be implemented using a complete look-up table. If the partitioning of the function inputs is potentially acceptable, the function inputs are assigned to the input ports of the logic cells. Variables are assigned to look-up table locations and a correspondence is determined between function input and output values, the variables, and the look-up table locations. Boolean tautology rules are applied to the correspondence to simplify the variables. If the simplified variables are consistent, a configuration is output that includes assignments of function inputs to input ports and look-up table data based on the simplified variables.

Abstract: A crossbar switch (50) is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules (40), the crossbar switch (50) providing communication links between the modules (40). The modules (40) and crossbar switch (50) can be easily updated in a partial reconfiguration process changing only portions of modules (40) and the crossbar switch (50) while other portions remain active. The crossbar switch (50) uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch (50) can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.

Abstract: A system of finite state machines built with asynchronous or synchronous logic for controlling the flow of data through computational logic circuits programmed to accomplish a task specified by a user, having one finite state machine associated with each computational logic circuit, having each finite state machine accept data from either one or more predecessor finite state machines or from one or more sources outside the system and furnish data to one or more successor finite state machines or a recipient outside the system, excluding from consideration in determining a clock period for the system logic paths performing the task specified by the user, and providing a means for ensuring that each finite state machine allows sufficient time to elapse for the computational logic circuit associated with that finite state to perform its task.

Abstract: The present invention relates to a semiconductor circuit device including a logic circuit and a signal line driving circuit. The logic circuit is operated at high supply voltage and outputs a signal with a high voltage amplitude. The signal line driving circuit receives a lower supply voltage and has a low-threshold transistor. With the above configuration, a signal can be transmitted at a high speed with a low voltage amplitude and low power consumption. Thus, the semiconductor circuit device including the signal line driving circuit can reduce operating current and can be operated with a low amplitude and low standby current at a high speed.

Abstract: CMOS buffer circuits with reduced short circuit current. In the CMOS buffer circuit, an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to turn off the first output transistor according to a delay signal. A bidirectional delay unit is controlled by the input signal to turn on the second output transistor after the first output transistor be turned off. In the bidirectional delay unit, a bidirectional logic unit generates two logic signals according to an inversion signal of the input signal, first and second bidirectional buffers are coupled to the output driving unit, generating a second signal to turn on the second output transistor according to the input signal and the two logic signals.

Abstract: A bus communication system contains a pair of communication conductors and a driver. The driver contains a plurality of pairs of controlled current source circuit, each pair comprising current source circuits of a first and second, mutually opposite polarity, and a control circuit for matching currents drawn by the current sources in each pair. The current source circuit of the first polarity have outputs coupled to a first one of the communication conductors, the current source circuits of the second polarity have outputs coupled to a second one of the communication conductors. A delay line is provided, with taps coupled to control inputs of the current sources of the first and second polarity, so that the pairs are switched on successively with mutual delays between successive pairs, as determined by the delay line.

Abstract: An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator and an AC attenuator. A common-mode correction loop is coupled to the AC attenuator and the DC attenuator for rejecting common-mode noise generated by the CML driver apparatus. The common-mode correction loop can also provide a common-mode voltage suitable for facilitating high-speed operation of low-voltage devices in the internal data path of the integrated circuit. An amplifier can be provided to compensate for signal attenuation in the input network.

Abstract: The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: A voltage detection circuit, comprises a constant-current circuit, a current mirror circuit operated by the constant-current circuit, at least one diode-connected first transistor disposed between an output of the current mirror circuit and a detected voltage, and an output circuit outputting one logic voltage in response to a turn-on of the first transistor when the detected voltage is a predetermined voltage or higher, and outputting the other logic voltage in response to a turn-off of the first transistor when the detected voltage is lower than the predetermined voltage.

Abstract: A CV conversion circuit capable of measuring a plurality of capacitances with a simple circuit is provided. A time-division signal is applied to each capacitor, whereby a plurality of capacitances of the capacitors can be measured in series by a circuit with a small number of components.

Abstract: The present invention relates to an output driver circuit which exhibits a reduced variation in the slew rate of an output signal thereof, irrespective of a variation in temperature occurring during a process carried out by a semiconductor memory device, to which the output driver circuit is applied, or a variation in temperature caused by the operation characteristics of the semiconductor memory device, while exhibiting excellent operation characteristics even in a high-speed operation mode thereof.

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals. A detection signal is generated every time the master triangular wave signal reaches predetermined threshold levels. In response to the detection signal, a capacitor associated with one slave triangular signal is promptly discharged to bring the slave triangular signal to the lower limit voltage, whereby the respective slave triangular wave signals are synchronized to be offset in phase relative to the master triangular wave signal by respective predetermined phase angles.

Abstract: The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power switch for a sleep mode and inputting an external sleep control signal; the power switch is used to control a combinational circuit to enter into the active or the sleep mode, and the combinational circuit is connected to a virtual power supply; an internal clock signal is separately input to a master stage and a slave stage of the flip-flop, and whether to enter into the sleep mode or the active mode is determined by the voltage level of the internal clock signal. In the present invention, all the logic gates of the combinational circuit are formed of low-threshold CMOS's, which enables the present invention to maintain a given operation speed at a lower voltage.

Abstract: An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.

Abstract: A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Abstract: In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two. A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

Abstract: The invention relates to a level converter for converting a signal (in) comprising a first voltage level (Vint) and supplied to the level converter, to a signal (Out) including a second voltage level (Vsupply) differing from the first voltage level (Vint). The level converter includes an amplifier device. The level converter is additionally supplied with a signal obtained from the signal (in) and delayed for compensating for distortions contained in said signal (in).

Abstract: A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal.

Abstract: In an embodiment, a switched capacitor transformer transfers a differential reference voltage at its input ports to its output ports, where a capacitor is switched so that the capacitor is coupled to the input ports during a first portion of a cycle of operation and then coupled to the output ports during a second portion of the cycle of operation, where the first and second portions of the cycle of operation are non-overlapping. Other embodiments are described and claimed.

Abstract: A method and circuit for driving the gate of a MOS transistor having a negative or low threshold voltage negative, in which the driving circuit is formed on a single chip. A negative voltage is generated from a positive voltage to drive the gate of the MOS transistor negative. The MOS transistor may be a native NMOS transistor, and the negative voltage is generated for increasing source-drain impedance of the native NMOS transistor. On the other hand, the MOS transistor may be a PMOS transistor, and the negative voltage is generated for reducing source-drain impedance of the PMOS transistor. The MOS transistor can be used as an open-drain switch or a source follower.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Abstract: A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output voltage and controlling the charge pump for stabilizing the output voltage.

Abstract: A voltage regulator has a reference voltage generator that outputs a reference voltage based on first and second electrical source voltages, an output circuit which generates a predetermined direct-current voltage based on the reference voltage and generates a comparison voltage lower than the predetermined direct-current voltage, and a differential amplifier coupled between the reference voltage generator and the output circuit. The differential amplifier provides a control voltage to the output circuit responsive to a difference between the reference and comparison voltages. The voltage regulator has a voltage adjustment circuit that adjusts the reference voltage responsive to a variation in the first electrical source voltage. The differential amplifier may include a constant-current circuit and an operation current generating circuit.