Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract: A voltage-controlled amplifier for a signal processing system includes an input voltage reception end, a first voltage-to-current converter, a reference current generator, a gain adjustment circuit, a first current mirror, and an output circuit. The voltage-controlled amplifier adjusts a gain according to a variable control voltage, so as to transfer an input voltage to an output voltage according to the adjusted gain. When adjusting the gain, the present invention changes only an alternating current part of the input voltage, and can decrease noise, the production cost, and increase integration degree.

Abstract: Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this performance is achieved by forming a trench type light-transmission layer to occupy a major surface of the photo diode so as to reduce the area available for defects on the surface of the semiconductor substrate. As a result of this reduction, the depletion region formed upon the operation of the sensor may extend toward the surface of the semiconductor substrate without concern for defects. The image sensor may be manufactured without forming a blocking layer in connection with a silicide layer.

Abstract: A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.

Abstract: The invention provides for a junction diode including a heavily doped first region having a first conductivity type, a second lightly doped or intrinsic region having a second conductivity type, and a third heavily doped region having a second conductivity type. The junction diode comprises more than one semiconductor or semiconductor alloy. In preferred embodiments, the lightly doped or intrinsic region has a higher proportion of germanium than on or the other or both of the heavily doped regions. In preferred embodiments, the junction diode is vertically oriented, and the top region has a higher proportion of silicon than the other regions.

Abstract: A semiconductor device includes a first insulating film having a cavity, a second insulating film formed on the first insulating film and having an opening exposing the cavity, a lower electrode of a concave shape in cross section formed on the bottom and sides of the cavity, a capacitive insulating film formed on the lower electrode, and an upper electrode formed on the capacitive insulating film. The diameter of the cavity of the first insulating film is larger than that of the opening of the second insulating film, and the end of the second insulating film located on the sides of the opening is formed in an eaves-like part to project like eaves inwardly beyond the sides of the first insulating film.

Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Abstract: The present invention relates to a device with integrated capacitance structure has at least one first and an adjacent second rewiring plane, each of which comprises at least one first partial structure and a second partial structure, which is different from the first partial structure, the second partial structure in each case substantially surrounding the first partial structure, and the first partial structure of the first rewiring plane being electrically connected to the second partial structure of the second rewiring plane and the second partial structure of the first rewiring plane being electrically connected to the first partial structure of the second rewiring plane and forming different poles of the capacitance structure.

Abstract: A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.

Abstract: An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to form word lines that intersect the active area lines at the angled segments.

Abstract: The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

Abstract: As and B are implanted to side surfaces of trenches 3 by a rotation ion implanting method, and by using a difference between these impurities in diffusion coefficient, the structure in which an n?-type epitaxial Si layer is interposed between trenches 3 is converted into a semiconductor structure consisting of n-type pillar layer 5/p-type pillar layer 4/n-type pillar layer 5 lining up. The structure can function substantially the same role as that of a super junction structure.

Abstract: This invention is characterized in that, a gate electrode 27F formed on a P-type well 3 via a gate oxide film 9, a high-concentration N-type source layer and a high-concentration N-type drain layer 15 respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer 10 and respectively parted by a P-type body layer formed under the gate electrode 27F are provided.

Abstract: A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.

Abstract: Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to ?A) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.

Abstract: An array of small square contact holes, on the order of magnitude of the exposing light wavelength, are formed by selecting the partial coherence and numerical aperture of the exposing light source and the pitch of the array of windows on an attenuating phase shifting mask so that side lobes formed by the exposing light being diffracted as it passes through the array of window constructively interfere with one another in the vicinity of a desired contact hole on the material surface. This constructive interference of side lobe patterns, in combination with the pattern formed by the light passing undiffracted through the array of windows, forms an array of square exposed regions on the material surface. When the material is a photoresist, the exposed regions can be selectively dissolved in order to form square patterns that can be used to etch square holes in the underlying substrate or layer.

Abstract: The present invention provides a semiconductor wafer comprising an insulated board of sapphire or the like having translucency, which is provided with a positioning orientation flat at a peripheral portion thereof, and a silicon thin film formed over the entire one surface of the insulated board. In the semiconductor wafer, ions are implanted in an area containing the orientation flat at a peripheral portion of the silicon thin film to amorphize silicon. Thus, the translucency at the amorphized spot is eliminated and accurate positioning using the conventional optical sensor can be performed.

Abstract: A display device of the present invention comprises: a source line; a pixel electrode; a first TFT for switching an electrical connection between the source line and the pixel electrode; and a second TFT as a spare. The second TFT includes a semiconductor film and a gate electrode. The semiconductor film includes a source electrode and a drain electrode. The gate electrode is provided on the semiconductor film with a gate insulation film interposed therebetween. The display device includes an interlayer insulation film between the source line and the semiconductor film of the second TFT. The interlayer insulation film is thicker than the gate insulation film. When the first TFT is unusable, a contact hole is formed in the interlayer insulation film such that the source line is electrically connected to the source electrode, whereby the electrical connection between the source line and the pixel electrode is rendered switchable by the second TFT.

Abstract: A part of the gate of a FINFET is replaced with a stress material to apply stress to the channel of the FINFET to enhance electron and hole mobility and improve performance. The FINFET has a SiGe/Si stacked gate, and before silicidation the SiGe part of the gate is selectively etched to form a gate gap that makes the gate thin enough to be fully silicidated. After silicidation, the gate-gap is filled with a stress nitride film to create stress in the channel and enhance the performance of the FINFET.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity silicon. The high-resistivity substrate is then controllably doped to provide a region of high-conductivity in the main substrate. Electrical isolation is achieved in such an embodiment by patterning the high-conductivity region either by masking the main substrate during the doping or etching through the doped, high-conductivity region in order to form regions of high conductivity. Effective isolation results from confinement of electrical currents to the lowest-resistance path. An alternative embodiment employs the fabrication of pn junctions and the use of reverse biasing to enhance the electrical isolation. A further embodiment comprises a main substrate layer of low-resistivity semiconductor material with a layer of insulator deposited thereon.

Abstract: A photoelectric transducer comprises an electrode (5) on which a semiconductor layer (7) carrying a sensitizing dye is deposited. The semiconductor layer (7) contains semiconductor particles and a binder and has a porosity of 40 to 80%. A method for manufacturing a photoelectric transducer by applying a solution containing semiconductor particles and a binder to an electrode (5), drying the electrode, and pressing the electrode under a pressure of 20 to 200 Mpa so as to form a semiconductor layer (7) is also disclosed. By the method, a photoelectric transducer comprising a semiconductor layer where a conduction path of photo-excited electrons is ensured without sintering the semiconductor layer at a high temperature and which has an adhesive power adaptable to the flexibility of the base and exhibiting excellent photoelectric transducing characteristics can be provided.

Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se

Abstract: A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface and an element isolation trench formed on the main surface of the semiconductor device, while the trench width of an upper end of the element isolation trench is larger than the trench width of a bottom surface and the length of a side surface located between the upper end and an end of the bottom surface is larger than the length of a straight line connecting the upper end and the end of the bottom surface. Thus, the element isolation trench is so formed that the trench width of the upper end is larger than the trench width of the bottom surface, whereby an insulator can be readily embedded in the element isolation trench. Thus, the insulator can be prevented from defective embedding.

Abstract: In accordance with certain embodiments consistent with the present invention, diamond nanoparticles are mixed with polymers. This mixture is expected to provide improved properties in interlayer dielectrics used in integrated circuit applications. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-? family heterostructure devices.

Abstract: A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.

Abstract: The invention relates to a semiconductor element with metallic and non-metallic surfaces, with the non-metallic surfaces of the semiconductor being provided with a layer which has irregularities, so that adhesion between the non-metallic surface and the molding compound is thus increased.

Abstract: A semiconductor chip mounting substrate having a semiconductor bare chip and a substrate electrically connected to the semiconductor bare chip by wire bonding is provided. Here, a protective film is provided on the surface of the semiconductor bare chip and is disposed so as to expose all or a part of a bonding wire.

Abstract: A leadless type semiconductor package includes a plate-like mount, and at least one semiconductor chip mounted on the plate-like mount such that a bottom surface of the semiconductor chip is secured to the plate-like mount, and the semiconductor chip has at least one electrode pad formed on a top surface thereof. The package further includes at least one flat electrode electrically connected to the electrode pad, and a molded resin enveloper for completely sealing and encapsulating the semiconductor chip. The molded resin enveloper further partially seals and encapsulates the flat electrode such that a part of the flat electrode is exposed as an outer electrode pad on a top surface of the molded resin enveloper.

Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: A flip-chip ball grid array integrated circuit package with improved thermo-mechanical properties is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. A semiconductor die is flip-chip mounted to the first surface of the substrate and electrically connected to ones of the conductive traces. An intermetallic heat spreader is fixed to a back side of the semiconductor die and a plurality of contact balls are disposed on the second surface of the substrate. The contact balls are in the form of a ball grid array and ones of the contact balls of the ball grid array are electrically connected to ones of the conductive traces.

Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.

Abstract: Integrated circuit packages and their manufacture are described, wherein the packages comprise dendrimers or hyperbranched polymers. In some implementations, the dendrimers or hyperbranched polymers include repeat units having one or more ring structures and having surface groups to react with one or more components of a plastic. In some implementations, the dendrimers or hyperbranched polymers have a glass transition temperature of less than an operating temperature of the integrated circuit and form at least a partially separate phase.

Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A semiconductor device which integrates a plurality of semiconductor chips into a single package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first bonding pads outputting first signals having a first level. The second semiconductor chip includes a plurality of second bonding pads and a plurality of third bonding pads. The plurality of second bonding pads is electrically coupled to a part of the plurality of first bonding pads to receive the first signals having the first level from the first semiconductor chip through the part of the plurality of first bonding pads. The plurality of third bonding pads converts the first signals received through the plurality of second bonding pad into second signals having a second level different from the first level and outputs the second signals through the plurality of third bonding pads.

Abstract: A ball grid array packaged semiconductor device mounted on a mounting board and including pads formed within a package and are connected to signal lines of a bare chip by bonding wires. There are formed first vias extending from the respective pads to a bottom surface of a package, and second vias extending from the same respective pads to a top surface of the package to form continuous vias. This makes it possible to connect the mounting boards to the top and bottom surfaces of the package, thereby enabling reduction of the wiring density of wiring patterns on the mounting boards, and thereby facilitating routing of the wiring patterns on the mounting boards. The semiconductor device is capable of reducing wiring density of the wiring pattern on the mounting board.

Abstract: A center pad type integrated circuit chip and a method of forming the same is presented. The chip comprises an integrated circuit chip having chip pads formed on a center region thereof and a jumper. The jumper includes a buffer layer arranged adjacent to a side of the chip pads and a plurality of jump metal lines formed on the buffer layer. The jump metal lines are spaced apart from each other.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: A thermal enhance semiconductor package with a universal heat spreader mainly comprises a carrier, a semiconductor chip and a universal heat spreader. The semiconductor chip is electrically connected to the carrier in a flip-chip fashion and the universal heat spreader is mounted on the back surface of the semiconductor chip. Therein the universal heat spreader has a plurality of through holes for upgrading the efficiency of heat transmission. Moreover, a heat transmission pin is provided in one of the through holes to increase the areas for heat dissipation so as to enhance the thermal performance of the package.

Abstract: An integrated circuit package is proposed in which a laminar substrate 41 is provided with an aperture 43. A heat-spreader member 1 is mounted to cover this aperture 43, and contains a cavity 3 opening towards the aperture 43 in the substrate 41. A stack of integrated circuit circuits 11, 21, are located with one integrated circuit 21 of the stack inserted into the cavity 3, and one integrated circuit 11 of the stack electrically connected to the substrate 41.