Patents Issued in June 7, 2007
  • Publication number: 20070126443
    Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.
    Type: Application
    Filed: January 30, 2007
    Publication date: June 7, 2007
    Inventors: Gary Grube, Igor Khandros, Benjamin Eldridge, Gaetan Mathieu
  • Publication number: 20070126444
    Abstract: A probe is disclosed, comprising a beam 4B, which has a front end 4b1, an intermediate portion 4b2 and a base end 4b3, the front end being a portion for contacting a test subject through a contactor, the base end being a portion for fixing the probe; and a substantially trapezoidal contactor 4A, which is fixed to the leading end 4b1 of the beam.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 7, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hisatomi Hosaka, Kiyoshi Takekoshi
  • Publication number: 20070126445
    Abstract: Integrated circuit package testing devices having a substrate with a cavity, and a device connecting a latch to said substrate, wherein said latch provides an unobstructed path to a center of the cavity, and the method for making and using the devices.
    Type: Application
    Filed: November 30, 2005
    Publication date: June 7, 2007
    Inventors: Amos Stutzman, Daniel Cram
  • Publication number: 20070126446
    Abstract: A ground-signal-ground (GSG) test structure for production measurement of RF device performance in integrated circuits comprises one pair of signal pads (S1, S2) and two pairs of ground pads (G1a, G1b; G2a, G2b). All the six pads (G1a, G2a, S1, S2, G1b, G2b) are arranged linearly, whereby the width of the structure is small enough for the structure to be placed in a narrow saw lane of a wafer.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 7, 2007
    Inventor: David Szmyd
  • Publication number: 20070126447
    Abstract: An improved apparatus and method for testing experiment is disclosed. The apparatus includes a motherboard and a stress module. The motherboard includes a component under test. A stress module connects the component and contacts the component directly. The stress module can provide the component with various rages of temperature and voltage for test. Besides, the stress module also can provide an anti-electrostatic device to prevent electrostatic disturbance.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 7, 2007
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventor: Wen-Dong Yen
  • Publication number: 20070126448
    Abstract: A pipeline tester is disclosed that is capable of testing systems-on-a-chip (SOCs) or Devices Under Test (DUTs) in pipeline fashion. The tester provides faster, more economical testing of such SOCs and DUTs, which are loaded sequentially into the tester. A plurality of underlying test stations are disposed in the tester. Above the test stations are disposed corresponding test fixtures which are configured to receive moveable test beds therein. The test beds are mechanically and electrically connected to the underlying test stations. Loaded within each test bed is an SOC or DUT. One or more electrical or electronic tests are performed on each SOC or DUT while the SOC or DUT is loaded in a test bed positioned above a test station. Once the test has been completed, the test bed is moved to another test station, where another electrical or electronic test is performed. Electrical or electronic tests may be performed in parallel on different DUTs or SOCs loaded into different test beds.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 7, 2007
    Inventors: Ronald Hubscher, Jason Smith, Frank Hamlin
  • Publication number: 20070126449
    Abstract: A system and method for measuring performance of a voltage regulator module (VRM) (61) attached to a microprocessor (62) is disclosed. The system includes: a voltage transient tester (VTT) fixture (5) for setting different working voltage levels of the VRM; an oscillograph (2) for measuring transient voltage levels of the VRM, and generating a transient voltage waveform according to the transient voltage levels; an voltmeter (3) for measuring steady voltage levels of the VRM under thermal effects generated by the microprocessor; a direct current (DC) electronic load (4) for educing load currents from the VRM; and a measurement control module (10) installed in a computer (1) for generating load current control signals, controlling the DC electronic load to educe the load currents from the VRM according to the load current control signals, and generating a performance report of the VRM by integrating various measurement results.
    Type: Application
    Filed: June 12, 2006
    Publication date: June 7, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: MING-SHIU OU YANG, WEI-YUAN CHEN, SUNG-KUO KU, CHO-HAO WANG
  • Publication number: 20070126450
    Abstract: Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
    Type: Application
    Filed: February 1, 2007
    Publication date: June 7, 2007
    Inventors: Kevin Condon, Theodore Levin, Leah Pastel, David Vallett
  • Publication number: 20070126451
    Abstract: An exemplary method for testing the quality of light-permeable thin films includes the steps of: providing a testing pattern; obtaining an image of the testing pattern as a reference image with an image sensor through a reference light-permeable thin film; determining resolution of the reference image by a modulation transfer function; obtaining an image of the testing pattern as a testing image with the image sensor through a to-be-checked light-permeable thin film; determining resolution of the testing image by a modulation transfer function; comparing the determined resolution of the testing image with that of the reference image so as to decide whether the to-be-checked light-permeable thin film is flawed.
    Type: Application
    Filed: June 16, 2006
    Publication date: June 7, 2007
    Applicant: HON HAI Precision Industry CO., LTD
    Inventor: Wei-Chung Chang
  • Publication number: 20070126452
    Abstract: A mounting apparatus includes a base and at least one pair of shoe plates. The shoe plates are formed on a top surface of the base. Each of the shoe plates comprises a plurality of grooves respectively on top surfaces thereof for holding at least one connector. It is simple and economical to using the mounting apparatus for holding a connector during a wire wrapping process.
    Type: Application
    Filed: September 11, 2006
    Publication date: June 7, 2007
    Applicant: HON HAI Precision Industry CO., LTD.
    Inventors: Hai Li, You-Hui Zhan
  • Publication number: 20070126453
    Abstract: Disclosed herein is an apparatus for testing a semiconductor device in a cost-saving manner. The apparatus may include a first substrate having a plurality of drive circuits for supplying various test signals, and a second substrate detachably connected to the first substrate. One side of the second substrate may be electrically connected with the first substrate and the other side thereof may be electrically connected with a semiconductor device such that the respective test signals are supplied from the drive circuits to the semiconductor device.
    Type: Application
    Filed: November 13, 2006
    Publication date: June 7, 2007
    Inventor: Sung Kim
  • Publication number: 20070126454
    Abstract: An apparatus and method of detecting a functionally defective substrate includes a detection unit to detect a trend in change in a voltage of a power source when a substrate is heated by the power source given by discharging of a capacitor and a test unit to compare the detected trend to a trend of change set in advance and to output the comparison result as a determination signal which indicates whether the substrate has a defect.
    Type: Application
    Filed: October 20, 2006
    Publication date: June 7, 2007
    Applicant: Samsung Elecronics Co., Ltd.
    Inventor: Chun-ku Han
  • Publication number: 20070126455
    Abstract: The gain of a buffer provided in a performance board can be adjusted. A performance board 10 of a semiconductor test apparatus (image sensor tester) 1a comprises buffers 11-1 to 11-n for driving cables, and switches 12-1 to 12-n for switching between the input of a measurement signal output from a device under measurement and the input of a reference signal output from a reference-signal generator 40. During calibration, the switches 12-1 to 12-n are turned to terminals b to which the reference signal is input, such that the reference signal is applied to the buffers 11-1 to 11-n. Then, the gains of the buffers 11-1 to 11-n are corrected so that the output of an analog capture board 20a has a desired value.
    Type: Application
    Filed: November 14, 2006
    Publication date: June 7, 2007
    Inventor: Kenji Yoshida
  • Publication number: 20070126456
    Abstract: There is provided a test socket for an integrated circuit. The test socket comprises a first plurality of test points for making electrical contact with contacts of a laminate package and a second plurality of test points for making electrical contact with contacts of a lead frame package. The test socket is suitable for testing, at one time, a laminate package, or a lead frame package, or both a laminate package and a lead frame package.
    Type: Application
    Filed: November 17, 2006
    Publication date: June 7, 2007
    Inventors: Chye Toh, Boon Chew
  • Publication number: 20070126457
    Abstract: A wafer holder is provided with a mounting stage having a mounting surface for mounting a wafer, and a holding member for holding the mounting stage, wherein relationships are established such that K1>K2 and Y1<Y2, where K1 is the thermal conductivity of the mounting stage, Y1 is the Young's modulus of the mounting stage, K2 is the thermal conductivity of the holding member, and Y2 is the Young's modulus of the holding member. The wafer holder preferably comprises a supporting member on the lower part of the holding member, wherein a relationship is establish such that K2>K3, where K3 is the thermal conductivity of the holding member.
    Type: Application
    Filed: November 22, 2006
    Publication date: June 7, 2007
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masuhiro Natsuhara, Tomoyuki Awazu, Hirohiko Nakata, Katsuhiro Itakura
  • Publication number: 20070126458
    Abstract: Various methods and systems for determining one or more properties of a specimen are provided. One system for determining a property of a specimen is configured to illuminate a specimen with different wavelengths of light substantially simultaneously. The different wavelengths of light are modulated at substantially the same frequency. The system is also configured to perform at least two measurements on the specimen. A minority carrier diffusion length of the specimen may be determined from the measurements and absorption coefficients of the specimen at the different wavelengths. Another system for detecting defects on a specimen is configured to deposit a charge at multiple locations on an upper surface of the specimen. This system is also configured to measure a vibration of a probe at the multiple locations. Defects may be detected on the specimen using a two-dimensional map of the specimen generated from the measured surface voltages.
    Type: Application
    Filed: January 31, 2007
    Publication date: June 7, 2007
    Inventors: Jianou Shi, Jeffrey Rzepiela, Shiyou Pei, Zhiwei Xu, John Alexander
  • Publication number: 20070126459
    Abstract: A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components.
    Type: Application
    Filed: January 26, 2007
    Publication date: June 7, 2007
    Inventors: Warren Farnworth, Mark Tuttle
  • Publication number: 20070126460
    Abstract: A flat panel display, a fabricating method thereof, a fabricating apparatus thereof, a picture quality controlling method thereof and a picture quality controlling apparatus for reducing a recognizing degree of a defective pixel and electrically compensating a charging characteristics of the defective pixel are provided. In the flat panel display, a display panel has a plurality of pixels. A defective pixel is electrically connected to an adjacent normal pixel. A memory stores a location data that indicates a location of the link pixel and a compensation data that compensates for charging characteristics of the link pixel. A compensation circuit modulates a digital video data to be displayed on the link pixel on the basis of the location data and the compensation data.
    Type: Application
    Filed: June 30, 2006
    Publication date: June 7, 2007
    Inventors: In Chung, Soon Yoo, Seung Nam, Deuk Lee, Jong Hwang
  • Publication number: 20070126461
    Abstract: A data acceleration device may include a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a second node which is electrically coupled with the first node, in response to an output signal from the pull-up driver, a first pull-down circuit for pull-down driving the second node, in response to an output signal from the pull-down driver, a delay circuit for delaying a signal from the second node by a preset time to output a delayed signal, a first switch for switching an operation of the first pull-up circuit in response to an output signal from the delay circuit, and a second switch for switching an operation of the first pull-down circuit in response to the output signal from the delay circuit. Also, there is presented a data transmission apparatus including the data acceleration device.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 7, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Ki Kwean
  • Publication number: 20070126462
    Abstract: In some embodiments a memory module includes a first on-chip termination device and a second on-chip termination device coupled to the first on-chip termination device to obtain an input impedance that is frequency independent. Other embodiments are described and claimed.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 7, 2007
    Inventor: Woong Ryu
  • Publication number: 20070126463
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Christopher Cox, George Vergis, Hany Fahmy, Hideo Oie
  • Publication number: 20070126464
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: George Vergis, Christopher Cox
  • Publication number: 20070126465
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Christopher Cox, George Vergis
  • Publication number: 20070126466
    Abstract: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.
    Type: Application
    Filed: December 30, 2005
    Publication date: June 7, 2007
    Inventor: Kyung-Hoon Kim
  • Publication number: 20070126467
    Abstract: An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination terminal, an off chip driver (OCD) control signal for adjusting an impedance of an output terminal, a plurality of ODT test signals for measuring a termination resistance of the termination terminal and a plurality of ODT signals having a different resistance; and a pull-up/pull-down unit for selectively driving a plurality of pull-up drivers and a plurality of pull-down drivers according to the pull-up signals and the pull-down signals in order to output a corresponding resistance of the output terminal at a read operation mode.
    Type: Application
    Filed: December 29, 2005
    Publication date: June 7, 2007
    Inventor: Kyung-Hoon Kim
  • Publication number: 20070126468
    Abstract: An on die termination (ODT) control device includes a latency block for buffering an ODT control signal to output a latency control signal by selecting one of a plurality of intermediate control signals, which are generated by sequentially delaying the buffered ODT control signal in synchronization with an internal clock, based on first latency information; an enable signal generation block for comparing a first control signal with a second control signal in response to the latency control signal to thereby produce an ODT enable signal based on the compared result; and an ODT block for controlling a termination impedance based on the ODT enable signal.
    Type: Application
    Filed: June 30, 2006
    Publication date: June 7, 2007
    Inventor: Kyung-Hoon Kim
  • Publication number: 20070126469
    Abstract: An on die termination (ODT) control device includes a mode register set for generating a clock control signal based on mode set information; a clock control unit for receiving an internal clock signal and a delay locked loop (DLL) clock signal and outputting an intermediate internal clock signal and an intermediate DLL clock signal in response to the clock control signal; and an ODT control unit for controlling an ODT block by receiving an ODT control signal in response to the intermediate internal clock signal and the intermediate DLL clock signal.
    Type: Application
    Filed: June 30, 2006
    Publication date: June 7, 2007
    Inventors: Dong-keun Kim, Kyung-Hoon Kim
  • Publication number: 20070126470
    Abstract: An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.
    Type: Application
    Filed: September 25, 2006
    Publication date: June 7, 2007
    Inventor: Kyung-Hoon Kim
  • Publication number: 20070126471
    Abstract: An on die thermal sensor (ODTS) includes a thermal sensor for outputting a first comparing voltage by detecting a temperature of the semiconductor memory device; a comparing unit for outputting a trimming code by comparing the first comparing voltage with a second comparing voltage and increasing or decreasing a preset digital code in response to the comparing result; and a voltage level adjusting unit for adjusting a voltage level of the second comparing voltage by determining a maximum variation voltage and a minimum variation voltage based on the trimming code and a temperature control code.
    Type: Application
    Filed: September 26, 2006
    Publication date: June 7, 2007
    Inventor: Chun-Seok Jeong
  • Publication number: 20070126472
    Abstract: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 7, 2007
    Applicant: University of Southern California
    Inventors: Lars Svensson, William Athas
  • Publication number: 20070126473
    Abstract: A circuit in an integrated circuit having an input terminal to be coupled to a resistor network for selecting one of multiple digital states in the integrated circuit includes a voltage decode circuit, a control circuit and a power-up control circuit. The first input terminal receives an input voltage having a voltage value associated with the multiple digital states. The voltage decode circuit receives the input voltage and generates a voltage decode signal indicative of the voltage value of the input voltage. The control circuit receives the voltage decode signal and generates an output control signal accordingly where the output control signal selects one of the multiple digital states. The power-up control circuit provides power to the resistor network, the voltage decode circuit and the control circuit for determining the selected digital state and disconnects power to those circuits after the selected digital state is determined.
    Type: Application
    Filed: September 27, 2005
    Publication date: June 7, 2007
    Inventors: Thruston Awalt, Peter Chambers
  • Publication number: 20070126474
    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Inventors: June Young Chang, Han Jin Cho
  • Publication number: 20070126475
    Abstract: A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.
    Type: Application
    Filed: August 23, 2006
    Publication date: June 7, 2007
    Inventors: David Boerstler, Eskinder Hailu, Jieming Qi
  • Publication number: 20070126476
    Abstract: A semiconductor integrated circuit includes an external terminal input with an external power supply voltage, a plurality of field effect transistors connected between the external terminal and an internal power supply line and a control circuit input with potentials of spots where voltage drops from output points of the output transistors are substantially the same in the internal power supply line, and controlling the plurality of field effect transistors according to the potential being input.
    Type: Application
    Filed: November 13, 2006
    Publication date: June 7, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Shingo Nakashima
  • Publication number: 20070126477
    Abstract: An output driver includes a pre-pull up drive unit configured to perform a pre-pull up drive operation; a pre-pull down drive unit configured to perform a pre-pull down drive operation; a drive unit configured to perform a drive operation in response to outputs of the pre-pull up drive unit and the pre-pull down drive unit; and a compensation unit configured to sense changes of driving strengths of the pre-pull up drive unit and the pre-pull down drive unit to control the driving forces of the pre-pull up drive unit and the pre-pull down drive unit.
    Type: Application
    Filed: June 30, 2006
    Publication date: June 7, 2007
    Inventor: Kwang-Myoung Rho
  • Publication number: 20070126478
    Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 7, 2007
    Applicant: DSM Solutions Inc.
    Inventor: Ashok Kapoor
  • Publication number: 20070126479
    Abstract: A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.
    Type: Application
    Filed: June 30, 2006
    Publication date: June 7, 2007
    Inventors: Hwang Hur, Chang-Ho Do
  • Publication number: 20070126480
    Abstract: A fully differential peak detection circuit includes programmable sensitivity and an autozero function. The peak detector has a fully differential charge-coupled analog signal path. The entire analog signal path is autozeroed upon enable and/or in response to sensing a logic zero at the output, where the logic zero follows a logic one. The peak detector includes a differential gain stage for receiving an analog input signal. The differential gain stage includes offset error compensation. The offset error compensation is selected upon enable and/or in response to an output signal of the peak detection circuit and automatically zeros an offset error voltage in response to a predetermined logic state of the output signal. The output of the gain stage is provided to a comparator stage. A plurality of capacitors coupled to the comparator stage stores a predetermined voltage for setting a sensitivity of the peak detector.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Dale McQuirk, Michael Bourland
  • Publication number: 20070126481
    Abstract: A peak detector is provided. Current switches are utilized and controlled by output of a plurality of error amplifiers respectively, such that charging currents are adjusted for a charge element in response to operations of the current switches respectively. Therefore, the overshooting charge is avoided and the time for charge is optimized.
    Type: Application
    Filed: April 26, 2006
    Publication date: June 7, 2007
    Inventor: Chun-Chi Chen
  • Publication number: 20070126482
    Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 7, 2007
    Inventors: Athar Khan. P, Rajiv Pandey, Pradip Mandal
  • Publication number: 20070126483
    Abstract: A gate driver is disclosed. The gate driver includes a plurality of output circuits and a plurality of delay circuits. Each output circuit includes a start-up terminal. An output terminal of each delay circuit is coupled to an input terminal of a next delay circuit. The input terminal of the first delay circuit receives an enable signal. An output terminal of each delay circuit is coupled to a start-up terminal of one of the output circuits to activate the output circuits.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 7, 2007
    Inventor: Wei-Ming Chen
  • Publication number: 20070126484
    Abstract: A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-lockup loop fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 7, 2007
    Inventors: Chia-Liang Lin, Gerchih Chou
  • Publication number: 20070126485
    Abstract: To provide a provide a voltage-controlled oscillator capable of controlling the threshold voltage of a MOS transistor independently of a temperature compensation control signal and an external voltage frequency control signal while securing linearity and downsizing the oscillator size without reducing the variable range of frequency, the voltage-controlled oscillator includes an amplifier, a piezoelectric vibrator, and a first load capacitor and a second load capacitor arranged as the load capacitors between both terminals of the piezoelectric vibrator, wherein a capacitor provided as the first load capacitor is composed of a variable capacitor with a small change in capacitance with respect to an input voltage and a capacitor provided as the second load capacitor is composed of a variable capacitor with a large change in capacitance with respect to an input voltage.
    Type: Application
    Filed: November 13, 2006
    Publication date: June 7, 2007
    Inventors: Yuichi Tateyama, Takashi Otsuka
  • Publication number: 20070126486
    Abstract: Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Inventors: Dae Woo Lee, Yil Suk Yang, Gyu Hyun Kim, Soon Il Yeo, Jong Dae Kim
  • Publication number: 20070126487
    Abstract: A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.
    Type: Application
    Filed: September 23, 2005
    Publication date: June 7, 2007
    Inventors: Ronald Sartschev, Ernest Walker
  • Publication number: 20070126488
    Abstract: Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 7, 2007
    Inventors: Dietrich Vook, Vamsi Srikantam, Andrew Fernandez
  • Publication number: 20070126489
    Abstract: A method involving: detecting a first signal characterized by a periodically occurring first event; detecting a second signal characterized by a periodically occurring second event; and based on both the detected first and second signals, generating a third signal characterized by a periodically occurring third event, wherein generating the third signal involves automatically adjusting the phase of the third signal so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.
    Type: Application
    Filed: March 28, 2006
    Publication date: June 7, 2007
    Applicant: Applied Materials, Inc.
    Inventors: Vladimir Prodanov, Mihai Banu
  • Publication number: 20070126490
    Abstract: A method and apparatus for receiving a first signal characterized by a periodically occurring first event; receiving a second signal characterized by a periodically occurring second event; delaying the first signal by a controllable amount of delay to generate a third signal characterized by a periodically occurring third event; and based on relative timing of the first and second signals, controlling the amount of delay so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.
    Type: Application
    Filed: April 3, 2006
    Publication date: June 7, 2007
    Applicant: Applied Materials, Inc. PATENT COUNSEL, Legal Affairs Dept.
    Inventors: Vladimir Prodanov, Mihai Banu
  • Publication number: 20070126491
    Abstract: Provided is a mixer for use in a direct conversion receiver. The mixer includes Field Effect Transistors (FETs), a current source (IBias), two load resistors (RLoad), another FET, and two inductors L1 and L2. The FET M21 constitutes a current bleeding circuitry and the other components except for the two inductors L1 and L2 constitute a so-called Gilbert cell mixer.
    Type: Application
    Filed: October 24, 2006
    Publication date: June 7, 2007
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Georgia Tech Research Corporation
    Inventors: Sang-Hyun Woo, Jin-Sung Park, Chang-Ho Lee, Joy Laskar
  • Publication number: 20070126492
    Abstract: High power, high frequency switches include a transmission line having at least three portions that are serially coupled between an input port and an output port to define at least two nodes and to carry a high power, high frequency signal between the input port and the output port. First and second power transistors are provided. At least a third power transistor also is provided. The controlling electrode(s) (gate) of the first, second and/or third power transistor(s) are responsive to a switch control input. The controlled electrodes (source/drain) of a respective one of the first and second power transistors, and of a respective one of the third power transistor(s) are serially coupled between a respective one of the at least two nodes and a reference voltage. The power transistors may be silicon carbide MESFETs.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 7, 2007
    Inventor: Raymond Pengelly