Abstract: Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Abstract: A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the transistor, and the top plate of the capacitor.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minority carriers having less mobility. A fabrication process for the semiconductor memory includes a “non-retrograde” implant of impurity ions that is effective to suppress the mobility and lifetime of minority carriers in the devices, and a “retrograde” implant of impurity ions that is effective to substantially increase the doping concentration at the well bottom to slow down or eliminate additional minority carriers.

Abstract: An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road side transformer using thereof. The contact member is composed of a base member made of high conductive metal, and a contact layer made of refractory metal and high conductive metal, and the contact layer is formed of a plurality of thermal sprayed layers.

Abstract: A semiconductor memory device included in a system-on-chip (SOC) or a microcomputer chip. The semiconductor memory device may include a flash memory cell array unit and a mask read-only memory (ROM) cell array unit which are formed in a single memory block without an isolation layer for separating the two units. Transistors included in the flash memory unit and the mask ROM unit are the same type and may have two threshold voltages. The transistor in each memory cell unit may be a split gate transistor, a metal-oxide-nitride-oxide-silicon, or silicon-oxide-nitride-oxide-silicon transistor. Further, the transistor included in the mask ROM unit in the semiconductor memory device may include enhancement transistors or depletion transistors in which a dopant ion-implanted region is formed at channel portions.

Abstract: Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure becomes appropriately changed to establish the desired mechanical properties for a created device.

Abstract: A vertical offset structure and a method for fabricating the same. The vertical offset structure includes a substrate; a fixed electrode fixing portion formed on the substrate; a fixed electrode moving portion formed at a position away from an upper portion of the substrate by a predetermined distance; a spring portion for connecting the fixed electrode fixing portion and the fixed electrode moving portion to each other so that the fixed electrode moving portion moves into a direction substantially perpendicular to a plate surface of the substrate; a movable electrode located away from the upper portion of the substrate by a predetermined distance to have a predetermined interval horizontal to the fixed electrode moving portion; and a cap wafer bonded to a predetermined area of one of the fixed electrode moving portion and the movable electrode.

Abstract: A magnetic random access memory according to an example of the present invention includes a magnetoresistive element, a write line for use in generation of a magnetic field for data writing with respect to the magnetoresistive element, and a strained layer which is disposed so as to correspond to the magnetoresistive element, and which has a function of being physically deformed at the time of data writing, and of controlling a magnitude of a switching magnetic field of the magnetoresistive element.

Abstract: The invention relates to a semiconductor component and a sensor component with data transmission devices, for wireless transmission the semiconductor component having a main coupling element and the sensor component having a sensor coupling element. The invention affords the possibility of multiple sensor applications without direct electrical contact between sensor component and semiconductor component, which may have a logic chip.

Abstract: A semiconductor power device includes a device feature layer, a substrate contact layer and a voltage-sustaining layer between them. The voltage-sustaining layer includes alternating semiconductor and high permittivity dielectric regions, where each region extends from the device feature layer to the substrate contact layer. Due to the flux of charges transported dominantly through the dielectric regions, the whole voltage-sustaining layer behaves like a semiconductor having a much higher electric permittivity than that of the semiconductor itself, so that the field produced by the ionized impurities of the semiconductor regions can be much higher than that of the conventional one for sustaining the same reverse voltage, and the specific on-resistance can be lower than that of the conventional one. The use of high permittivity dielectric regions can also be applied to the charge-balance structure, i.e., to COOLMOST.

Abstract: A silicon substrate includes plural partial areas defined on the silicon substrate such that adjacent partial areas are orientated in different directions. The plural partial areas define an insulating layer that extends from a surface of the silicon subtrate into the silicon substrate. Each of the plural partial areas includes first regions that contain silicon dioxide formed by oxidation of silicon in the silicon substrate, and second regions that contain silicon dioxide deposited onto the silicon substrate. The first regions and the second regions are oriented in a substantially same direction and are arranged side-by-side and alternately such that two first regions do not border and two second regions do not border.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.

Abstract: It is an object to provide a semiconductor device integrating various elements without using a semiconductor substrate, and a method of manufacturing the same. According to the present invention, a layer to be separated including an inductor, a capacitor, a resistor element, a TFT element, an embedded wiring and the like, is formed over a substrate, separated from the substrate, and transferred onto a circuit board 100. An electrical conduction with a wiring pattern 114 provided in the circuit board 100 is made by a wire 112 or a solder 107, thereby forming a high frequency module or the like.

Abstract: A side-mounted capacitor for a semiconductor die package is described. In one embodiment, a substrate has a die side to which an IC (integrated circuit) may be attached, and an edge adjacent the die side. A bypass capacitor is attached to the package substrate edge.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A substrate for mounting a device is disclosed. The substrate includes at least one transition for providing an RF connection to a lead of the device, the lead extending from a device input to an otherwise free end. The transition comprises two spaced apart electrically coupled members, the first member occupying at least the same area on a top surface of the substrate as the device lead to which it is to connect, and the second member lying in register with the first member. The transition comprises an input, which is located at the end of the second member which is nearest the free end of the device lead and an output which is located at the opposite end of the first member and which is in register with the device input. The electrical characteristics of the transition are such that the electrical length from the input of the transition to the output of the transition is approximately equal to one half of a wavelength over a given operating frequency band of the device.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: An electrode that includes an electrically conductive, substantially planar body having a first thickness and a junction area, wherein the junction area is configured to receive a solid state power cell having a second thickness. The electrode also includes an arcuate terminal electrically coupled to the body and configured to position a wire bond terminus at a perpendicular distance from the body, the distance being not substantially less than the sum of the first and second thicknesses.

Abstract: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.

Abstract: A ground-enhanced semiconductor package and a lead frame used in the package are provided. The semiconductor package includes a lead frame having a die pad, a plurality of tie bars connected with and supporting the die pad, a plurality of leads surrounding the die pad, and a ground structure, wherein the ground structure comprises at least one of first ground portions connected to the tie bars, and/or at least one of second ground portions connected to the die pad, and wherein the first ground portions are separate from each other, and the second ground portions are separate from each other; at least one chip mounted on the die pad and electrically connected to the leads and the ground structure; and an encapsulation body for encapsulating the chip and the lead frame. The separately-arranged ground portions allow thermal stresses to be released from the ground structure without rendering deformation issues.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (124), which is glass in the case of many DMD packages, seals the device (100) in a package cavity (120).

Abstract: A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads. All elements are sealed within an insulating layer such that the external terminals are partially exposed on the surface, wherein an uppermost portion of a conductive wire is positioned above the rewiring patterns and is also positioned below the lower ends of the external terminals. This realizes short wiring distances between the pads and the external terminals; hence, it is possible to reduce the wiring resistance and wiring delay time; it is possible to increase a freedom of degree regarding wiring without causing short-circuit failure; and, it is possible to easily change the wiring in a short period of time.

Abstract: An IC card that has improved endurance and demonstrates increased resistance to cracking of the case and peeling of the substrate when a bending force acts upon the IC card. First protrusions and second protrusions are formed in a recess for fitting a LGA. The second protrusions are connected to the side wall of the recess on the card center side. Because the first protrusions maintaining a constant and correct gap between the bottom portion and LGA, that is, a constant and correct thickness of an adhesive, and the second protrusions are provided, the LGA and case can be reliably bonded together. The boundary portion with the thick portion of the recess on the card center side is a portion where stresses are easily concentrated and cracks can easily occur. However, because the second protrusions provided in the bottom portion of the recess are integrally connected to the side wall, the boundary portion is reinforced and stress concentration is relaxed.

Abstract: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.

Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.

Abstract: Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.

Abstract: A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Abstract: The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

Abstract: The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.

Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.

Abstract: A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a raised ring. The raised ring circumscribes the pad or surrounds an interior pad or land on the substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

Abstract: In accordance with certain exemplary embodiments, the present technique provides methods and apparatus for providing transient and uninterrupted power to protected loads. As one example, the present invention provides an induction device that operates as an induction motor to energize a kinetic energy storage device, such as a flywheel, during conventional operating conditions. However, in the event of a loss of primary power, the induction device, which is fed ac power at variable frequencies, begins to operate as an induction generator. For example, by varying the frequency of the input ac power such that the synchronous speed of the motor is exceeded by the rotating flywheel, the induction device acts as an induction generator and provides a transient operating power to the downstream loads until an auxiliary power source, such as a diesel generator, is brought on line.

Abstract: A method is provided for exercising an engine-driven, electrical generator. The generator has a first operation mode wherein the generator generates a predetermined output voltage at a predetermined frequency with the engine running a predetermined operating speed and a second exercise mode. The method includes the step of running the engine at a predetermined exercise speed with the generator in the exercise mode. The predetermined exercise speed is in the range of 40% to 70% of the predetermined operating speed of the engine. In addition, in the exercise mode, the generator generates an exercise voltage that is less than the predetermined output voltage.

Abstract: A sensor is placed in wireless communication with a monitoring system. Power for the sensor is generated by scavenging power from fluid flow within a pipe.

Abstract: A corrosion protected wind turbine unit includes a wind turbine unit support structure or foundation implanted in water and an impressed current anode electrochemically coupled to the wind turbine unit support structure or foundation through the water. Also included is a controlled current source configured to receive electrical current from the wind turbine unit or at least one other wind turbine unit located in proximity to the corrosion protected wind turbine unit and further configured to operate the impressed current anode.

Abstract: A wind turbine for generating electrical power having a vertical “Savonius rotor type” wind rotatable turbine with multiple fixed pitch blades and a rotatable wind inlet duct having an identical number of multiple infuser-shaped aerodynamic guides as the pitch blades and is mounted in the duct to direct equal air flow at higher speed to load each of the multiple fixed pitch blades to form an infuser system. The wind-rotatable turbine is mounted within the inlet duct and infuser system. A synchronous generator is driven by the vertical turbine and an electrically driven hold-down spring system enables the wind turbine to disconnect from the generator when the wind speed is above maximum safe operating speeds.

Abstract: A high intensity discharge (HID) assembly comprises ballast circuits which includes a micro-controller, and an HID headlamp. In order to deter theft of the HID assembly from a vehicle, the micro-controller communicates with a vehicle computer, checks the VIN of the vehicle, and if the micro-controller does not recognize the VIN, causes the HID headlamp to operate in a flickering power output mode. The ballast circuits include a power control circuit, a lamp current regulator, a 400v regulator, a current sense circuit, a turn-on synchronization circuit, a shut down circuit, and a pulse width modulator.