Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

Abstract: In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of the inputs. The pulse generator is configured to generate a pair of control signals to the passgates, and is configured to generate pulses on the pair of control signals to open the passgates. Each of the latch elements is connected to a respective input and is configured to latch the signal on the respective input when passgates are open and to retain the signal on the respective input when the passgates are closed.

Abstract: Configurable circuits with microcontrollers are described herein. The microcontrollers may perform a variety of functions including the control of configurations of the configurable circuits.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

Abstract: A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal.

Abstract: The improved PCML communications driver corrects current loss and reduced voltage swing when driving an LVDS receiver load by reducing the value of the Rt1 resistors. By changing the value of the two Rt1 resistors from Rt1 to Rt1/2 (or lower), the full bias current can be restored and voltage swing is substantially improved. By making Rt1 a programmable resistor so Rt=Rt1/2 for DC bias calculation, Q2 bias current is increased back to IB, instead of IB/2.

Abstract: An improvement reducing or eliminating noise between drivers connected in common on a single chip. A DC power source (VDD1) providing a common signal to multiple PCML drivers and inductance introduced between a common DC power source and each of the multiple PCML drivers tied in common to the DC power source. The introduced inductance between VDD1 and each of the multiple PCML drivers reduces or eliminates AC noise from flowing between drivers and allows DC signaling to pass to all drivers commonly connected to VDD1.

Abstract: The interface of a single-ended CMOS type signal to differential signal loads includes a LVDS load having a +Vin input and a ?Vin input, a CMOS circuit having an output signal line, and a resistor Rt connected to the output signal line and ground. A 2.5 volt source line is connected through a resistor R1 to the ?Vin input of the LVDS load, the output signal line is connected directly to the +Vin input of the LVDS load, and a resistor R2 and capacitor C1 re connected in parallel between R1 and the ?Vin input and ground.

Abstract: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Abstract: An input voltage sensing circuit comprising a circuit input terminal; a comparator having first and second input terminals, the first of said input terminals being coupled to a reference voltage; a switch circuit provided between the circuit input terminal and the second of the input terminals of the comparator, the switch being provided to protect the comparator from voltages exceeding a predetermined voltage at which the switch turns off; and an electrostatic discharge circuit coupled to the circuit input terminal for discharging electrostatic induced voltages exceeding a predetermined value.

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third

Abstract: Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.

Abstract: Transmitter and transmission circuit. For realizing a differential transmitter, a switch circuit is connected between two load transistors of two complementary MOS pairs. The switch circuit can have two inductors. When the two complementary MOS pairs are conducting current to drive signal transition at output nodes, the inductors open to make the load transistors stop draining current. Also, the switch circuit can have switch transistor controlled by an edge detector for detecting raising and falling edges of the input signals, such that the switch circuit can make the load transistors stop draining current accordingly. In this way, raising and falling edges of the output signals are emphasized to improve signal propagation.

Abstract: The present invention improves a frequency divider circuit so that the frequency divider further obtains a capability of operating an injection-locking frequency division without changing or adding any component; and, the frequency divider operates under low voltage and low power consumption yet in high frequency, where the present invention can be use in related fields of radio frequency and optoelectronic communication.

Abstract: In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

Abstract: The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.

Abstract: Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also include a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled. Isolation diodes ensure that a discharge current can bypass inoperable voltage cells.

Abstract: A method and apparatus for pre-clocking have been disclosed.

Abstract: A low to high voltage level converter includes first and second n-channel transistors arranged to force to the ground voltage a first connection node and a second connection node, respectively. A boosting circuit operates to boost an input voltage of at least one of a first and second control nodes for the first and second n-channel transistors above a low voltage level. The converter further includes first and second cross-coupled p-channel transistors arranged to force to the high voltage level the first connection node and the second connection node, respectively. A digital output signal is taken from one of the first and second connection nodes.

Abstract: Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: A system and method for driving a bipolar junction transistor is provided. The system includes a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive a first control signal. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal. The second gate is configured to receive a second control signal. Moreover, the system includes a first resistor including a fifth terminal and a sixth terminal. The fifth terminal is connected to the first terminal, and the sixth terminal is biased to a first predetermined voltage. The fourth terminal is biased to a second predetermined voltage. The second terminal and the third terminal are connected at a node, and the node is connected to a base for a bipolar junction transistor.

Abstract: A fuse circuit may include a fuse cut detection unit to output state information indicating whether or not a fuse is cut during a fuse cut detection time period, a maintenance and output unit to maintain the state information and output a fuse state information signal, and a connection/disconnection unit to connect the fuse cut detection unit to the maintenance and output unit during the fuse cut detection time period and disconnect the fuse cut detection unit from the maintenance and output unit after the fuse cut detection time period. A fuse circuit may recognize an indefinite voltage at a detection node caused by a leakage path through a fuse as a predetermined fuse state.

Abstract: An apparatus and method for controlling a supply voltage using hierarchical performance monitors includes a signal generator generating an operating frequency and a target operating frequency, a supply voltage generator generating the supply voltage, a plurality of local performance monitors, and a global performance monitor. Each of the plurality of local performance monitors implemented in each different domain is modelled on a relationship between a level of the supplied voltage supplied to each different domain of a predetermined system and an operating speed or the operating frequency of a predetermined circuit implemented in the interior of the domain. The plurality of local performance monitors, respectively, monitors continuously whether the level of the supply voltage supplied to the domain is suitable for the target operating frequency, and outputs a local feedback signal.

Abstract: In one embodiment, an integrated circuit comprises a first circuit and a control unit coupled to the first circuit. The first circuit comprises at least one transistor and implements one or more operations for which the integrated circuit is designed. The control unit is configured to generate at least one substrate bias voltage for the first circuit.

Abstract: Techniques for efficiently generating an output voltage for use within an electronic device, such as a memory system, are disclosed. A voltage generation circuit generates the output voltage. The voltage generation circuit includes regulation circuitry that controls regulation of the output voltage to maintain the output voltage at a substantially constant level. According to one aspect, regulation is enabled when needed but disabled when regulation is not necessary, thereby reducing power consumption by the regulation circuitry. The voltage generation circuit is therefore able to operate with improved power efficiency.

Abstract: Techniques for efficiently stabilizing an output voltage produced by a voltage regulation circuit are disclosed. One embodiment pertains to a voltage regulation circuit that includes a supplemental current source that can be controllably activated to provide a supplemental current to an output terminal of the voltage regulation circuit. This supplemental current can then assist in stabilizing the output voltage level at the output terminal of the voltage regulation circuit even in the presence of high current surges by a load (i.e., electronic circuitry). Advantageously, given the availability of the supplemental current, the required amount of capacitance for a decoupling capacitor (also coupled to the output terminal of the voltage regulation circuit) can be significantly reduced. In the case of semiconductor electronic devices, the reduction in the needed capacitance yields substantial die area savings with respect to decoupling capacitors.

Abstract: An exemplary power supply circuit includes a comparator and two MOSFET transistors connected in parallel. The comparator has a non-inverting terminal connected to a reference voltage. Both gates of the MOSFET transistors are connected to an output terminal of the comparator, both drains of the MOSFET transistors are connected to a power supply, both sources of the two MOSFET transistors are connected to an inverting terminal of the comparator and act as an output of the power supply circuit.

Abstract: A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

Abstract: A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down,. essentially the reverse sequence is provided.

Abstract: A power amplifier system including: M main power amplifiers and one standby power amplifier, where M is a positive integer; an input switching module, connected to the inputs of the M main power amplifiers and the standby power amplifier; an output switching module, connected to the outputs of the M main power amplifiers and the standby power amplifier. In the system, M groups of signals are inputted to the input switching module, processed by the power amplifiers, and then outputted from the output switching module. The standby power amplifier is independent and is capable of taking place of the faulted main power amplifier immediately without a shut down. In the system there is no correlation between the isolation of various signals and the consistency of the power amplifies, which leads to a substantial decrease of the requirement on consistency of the power amplifiers.

Abstract: An efficient power amplifier circuitry for a mobile terminal or similar wireless communication device is provided. The power amplifier circuitry includes an output stage configured as a collector controlled Doherty amplifier, wherein the collector controlled Doherty amplifier increases the efficiency of the power amplifier at backoff power levels. The output stage includes main and peaking amplifiers connected in parallel and operating 90 degrees out-of-phase. The main amplifier is controlled using a first variable supply voltage, and the peaking amplifier is controlled using a second variable supply voltage. The first and second variable supply voltages are provided such that the main amplifier is active and the peaking amplifier is inactive for output power levels less than a predetermined backoff from a maximum output power level, and both the main amplifier and peaking amplifiers are active and operating in concert for output power levels greater than the predetermined backoff.

Abstract: Systems and methods are provided for efficient amplification of a signal utilizing a modified Doherty amplifier system. A modified Doherty amplifier system includes a nonlinear main amplifier and a nonlinear auxiliary amplifier. An impedance-inverting network separates the main amplifier from an associated load. A second quarter wave transmission line separates the auxiliary amplifier from an associated signal source. The signal source has an associated minimum signal power, such that the signal power never drops below a predetermined percentage of a peak signal power.

Abstract: Systems and methods are provided for amplifying a composite input signal, comprising a drive signal and an envelope signal, at a power amplifier. A secondary modulation, representing a portion of the composite input signal falling outside of a frequency band associated with the envelope signal, is produced for the drive signal. The secondary modulation is applied to the drive signal. The drive signal is amplified at the power amplifier to produce an amplified signal. At least a portion of the envelope signal is employed to drive a supply terminal of the power amplifier.

Abstract: A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.

Abstract: A circuit for minimizing audible click noise upon the startup of a Class D audio power amplifier. The amplifier including a power switching output stage and a driver for driving the output stage receiving a driving signal and a shutdown signal, the shutdown signal preventing switching of the output stage. The circuit including a comparator connected to the driver for generating the driving signal; an error amplifier receiving an audio input signal; a first feedback loop for connecting the output stage as input to an input of the error amplifier, an output of the error amplifier being connected to an output of the comparator; and a circuit coupled to the error amplifier preventing a capacitor connected to the error amplifier from excessively charging, thereby preventing noise in the output stage when the shutdown signal is removed.

Abstract: The present invention relates to a transconductance circuit intended to convert a differential input voltage, supplied as two signals to two inputs, IN+ and IN? respectively, into a differential output current. According to the invention, each of the two signals of said differential input voltage is supplied to each input, IN+ and IN? respectively, through a follower transistor, TF+ and TF? respectively, connected to said input, IN+ and IN? respectively, by its emitter and receiving said signal on a control electrode.

Abstract: A buffer amplifier for source driver is disclosed. The buffer amplifier has an N-channel differential amplifier and a P-channel differential amplifier as its input stages so as to achieve rail-to-rail input, and a class AB amplifier to push-pull the output stage so as to achieve rail-to-rail output. The output stage of the buffer amplifier is capable of larger charge/discharge, is faster, and has equal charge/discharge time. More importantly, the buffer amplifier has advantages such as lower power consumption, higher slew rate, and a more stable output.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. Differential RF power amplifiers are also provided with inductive networks coupled at various nodes of the power amplifiers. In some examples, techniques are used to stabilize differential power amplifiers by stabilizing common-mode feedback loops.

Abstract: Provided is an automatic gain control (AGC) apparatus of a cable modem. The apparatus includes: a gain controller for measuring a power level of digital input signals transmitted from outside, accumulating the measured values of the digital input signals for a predetermined period, acquiring an average size of the signals, and calculating an error value between the average signal size and a predetermined signal size; an amplitude control unit for receiving error values adjusted by the gain controller and controlling an amplitude of the signal; a low pass filter for receiving the signal outputted from the amplitude control unit and performing low pass filtering on the signal; and a signal size control unit for receiving the signal obtained from filtering of the low pass filter and controlling the signal size.

Abstract: There is provided a gain variable circuit including: a first load connected between a first supply voltage node and a first output terminal that outputs a first output signal; a second load connected between the first supply voltage node and a second output terminal that outputs a second output signal whose phase is reversed from that of the first output signal; a first differential circuit that is connected between the first and second output terminals and a first node and which changes the gains of the first and second output signals in accordance with a difference between first and second complementary gain variable signals; a second differential circuit that is connected between the first and second output terminals and a second node and which changes the gains of the first and second output signals in accordance with a difference between the first and second gain variable signals; and an amplification circuit that is connected between the first and second nodes and a second supply voltage node and which

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: Fully differential amplifier circuits are described herein that set the common mode voltage as well as reduce the output offset voltage (offset cancellation). A circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals, a first negative feedback loop coupled to the first section, and a second negative feedback loop coupled to the first section. A second section controls the first negative feedback loop for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal in different loop bandwidths. A third section controls the second negative feedback loop for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal in different loop bandwidths.

Abstract: A wide-band amplifier having a flat amplification characteristic over a wide frequency bandwidth, being prevented from degrading due to parasitic capacitance, and being short in group delay time. The wide-band amplifier includes a band-pass filter made of an LC parallel resonant circuit and an LCR series resonant circuit and provided in parallel as a load for a current output amplifier device. The band-pass filter has a plurality of poles as well as zeros provided therebetween in the s-plane, thereby improving a characteristic flatness in a passband. The output terminal of the amplifier device serves as an output terminal for the amplifier, so that the problem of group delay does not occur. A capacitance element between the output terminal of the amplifier and GND absorbs parasitic capacitance as part of constants, thereby preventing degradation of the frequency characteristic.

Abstract: A fast-settling digital automatic gain control circuit comprises first and second gain-controllable amplifiers in series. Each amplifier can be digitally switched between minimum and maximum gains by control logic that receives inputs from a multi-level voltage comparator. A peak detector connected to the output of the first gain-controlled amplifier is used to set the overall operating ranges for several threshold detectors. Four reference voltages are generated from the peak detector. The highest reference voltage is used to clock and reset the gain control logic with a hysteresis comparator to the instantaneous input signal from the first gain-controlled amplifier. The three other lower reference voltages are used to provide three-bits of digital input data to the gain control logic. Two digital controls are output, a min/max gain bit for the first gain-controlled amplifier, and a similar min/max gain bit for the second gain-controlled amplifier.

Abstract: A variable attenuator which can sequentially control attenuation effectively and has a small variation in manufacturing, is provided. The variable attenuator has a first signal input terminal; a first signal output terminal; a first control terminal receiving a control voltage; an analog/digital converter converting the control voltage to M (M is a positive integer of 2 or more) control signals; and N (N is a positive integer satisfying N?M) variable impedance elements which are connected in parallel and/or in series between the first signal input terminal and the first signal output terminal, and each impedance of which is varied by either one of the control signals.

Abstract: The present invention provides methods and apparatuses for an amplifier circuit for amplifying an input signal. An amplifier circuit for amplifying an input signal comprises an amplifying transistor circuit having a power transistor and a dc bias circuit having a plurality of current mirror circuits and a discharge transistor wherein the discharge transistor and the power transistor form a combined current mirror circuit to control quiescent current in the power transistor.