Abstract: A fan-shaped dissipating device, which is assembled on a chip of an erect PCB, has a conductive board, and a plurality of fins. The fins are respectively connected on an outside surface of the conductive board. Each of the fins has a top end and a bottom end. An interval between each two adjacent top ends of the fins is larger that between each two adjacent bottom ends of the fins. The fins are arranged in a radiating manner toward two sides from the bottom ends to the upper ends, therefore reducing the density of the accumulated air between the top ends of the fins because of rising hot air, and providing a better dissipating effect.

Abstract: A semiconductor device includes a cooling unit in which coolant flows, a semiconductor chip having two main surfaces press-pinched by the cooling unit, and an electronic member different from the semiconductor chip. The electronic member is located to contact the cooling unit.

Abstract: A method according to one embodiment may include providing a heat generating component disposed on a first side of a first circuit board, and transferring heat from the heat generating component through the first circuit board to a second side of the first circuit board. The method according to this embodiment may further include slidingly thermally coupling the second side of the first circuit board to a thermal solution disposed on a second circuit board. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A semiconductor element comprises a capacitance variable section and an inductor section. In the capacitance variable section, a variable capacitance diode equipped with first and second control electrodes is provided on an insulative substrate. The inductor section is formed on the capacitance variable section formed with the variable capacitance diode. The inductor section is formed in an insulating layer provided on the variable capacitance diode. A first input/output electrode, a second input/output electrode, and first and second control input/output electrodes are provided in exposed form on the upper side of the insulating layer provided on the capacitance variable section.

Abstract: Circuit board and system with multi-portion sockets, and signal methods practiced thereon are described herein.

Abstract: A module with a built-in circuit component of the present invention includes an electric insulating layer, a pair of wiring layers provided on both principal planes of the electric insulating layer, a plurality of via conductors electrically connecting the pair of wiring layers and passing through the electric insulating layer in a thickness direction thereof, and a circuit component buried in the electric insulating layer, wherein the plurality of via conductors are disposed in a circumferential portion of the electric insulating layer in accordance with a predetermined rule. The plurality of via conductors are placed at an interval, for example, so as to form at least one straight line, in a cut surface of the electric insulating layer in a direction parallel to a principal plane thereof.

Abstract: An electrical power circuit assembly including an insulated metal substrate (IMS) printed circuit board (PCB), a filter (PCB), and one or more bus bars disposed between the IMS PCB and the filter (PCB), the bus bar geometry configured to reduce the inductance between semiconductor power devices on the IMS PCB and capacitors on the filter PCB. For one embodiment, low profile bus bars are used between the IMS PCB and a fiberglass PCB. The fiberglass PCB has a plurality of filter capacitors electrically connected across the bus structure. The geometry and layout of the bus bars provides a connection from the IMS PCB to the fiberglass PCB with very low parasitic inductance between surface mounted semiconductor power devices on the IMS PCB and filter capacitors on the fiberglass PCB.

Abstract: Embodiments of the present invention provide an electro-magnetic suppressive structure. The electro-magnetic suppressive structure comprises a cover portion and an integrally formed conductive portion.

Abstract: The circuit arrangement has a mains connection, a mains switch and a switched-mode power supply which contains a power factor coil for power factor correction. In this case, the mains switch has two switching contacts, one of which is arranged in a supply line between the mains connection and the switched-mode power supply, and in this way switches the phase or neutral conductor of the 50 Hz line network off and on. The connections of the second switching contact are located in a voltage supply for the driver circuit of the switched-mode power supply, and the second switching contact switches the switching transistor in the switched-mode power supply off when the circuit arrangement is switched off, by its control voltage being switched off directly or indirectly. The switching contact of a relay is arranged in parallel with the first switching contact of the mains switch, and the control coil of this relay is connected to an output voltage of the switched-mode power supply.

Abstract: A switching converter in which an input voltage can be switched by means of at least one controlled switch to at least one primary winding of a transformer, with a control circuit for controlling the switch, to which control circuit a regulating signal in the sense of regulating at least one output voltage is sent, wherein the power supply of the control circuit takes place via the forward voltage of an auxiliary winding of the transformer, a rectifier, a capacitor and a series regulator, on the one hand, and, on the other hand, starting from the input voltage, via a current path and a storage capacitor, and the off-state voltage of an auxiliary winding, which is rectified by means of a rectifier, is additionally sent to the control circuit for power supply, wherein the rectified off-state voltage is used during the operation for supplying the control circuit as long as it has a sufficient voltage level.

Abstract: This invention generally relates to discontinuous conduction mode switch mode power supply (SMPS) controllers employing primary side sensing. We describe an SMPS controller which integrates a feedback signal from a point determined by a target operating voltage to a peak or trough of an oscillatory or resonant portion of the feedback signal when substantially no energy is being transferred to the SMPS output. When regulation is achieved this value should be zero; the difference from zero can be used to regulate the output voltage of the SMPS.

Abstract: First and second semiconductor switches which are activated alternately are provided between ends of a primary winding and a common potential point, wherein a DC power supply voltage is supplied to a center tap. An electric current flowing into a load is fed back to thereby subject the semiconductor switches to PWM control. Series circuits consisting of capacitors and semiconductor switches are connected between the center tap of the primary winding and the ends of the same. The semiconductor switches are activated in synchronism with the first and second semiconductor switches, thereby preventing occurrence of an anomalous high voltage, which would otherwise be caused at the time of switching operation.

Abstract: A method and a system for controlling the mains bridge of a four-quadrant PWM frequency converter provided with a direct-voltage intermediate circuit when power is flowing into the supply network. The mains bridge includes a controlled mains bridge (INU) for rectification of the mains voltage to produce a DC intermediate-circuit direct voltage (UDC) consisting of arms conducting during the positive and negative half cycles of the phase voltage of each phase of the supply network, each arm having a switch unit formed by a diode (D1–D6) and a power semiconductor switch (V1–V6), e.g. an IGBT, connected in inverse-parallel with it.

Abstract: In the current invention, in order to increase efficiency of battery powered AC electricity supply, multiple inverter/battery modules are used in parallel but can be individually shut down. The number of inverters activated depends on the power usage. When only a little power is needed only one or a few inverters are activated. When more power is needed the battery inefficiency increases and more inverters will be activated.

Abstract: According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.

Abstract: A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.

Abstract: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

Abstract: A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer.

Abstract: An spin-injection FET includes a first ferromagnetic body whose magnetization direction is fixed, a second ferromagnetic body whose magnetization direction is changed by spin-injection current, a gate electrode which is formed on a channel between the first and second ferromagnetic bodies, a first driver/sinker which controls a direction of the spin-injection current to determine the magnetization direction of the second ferromagnetic body, the spin-injection current being passed through the channel, a wiring through which assist current is passed, the assist current generating a magnetic field in a magnetization easy axis direction of the second ferromagnetic body, and a second driver/sinker which controls the direction of the assist current passed through the conductive line.

Abstract: A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.

Abstract: A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plurality of word lines. A driver region separates the first and second regions and includes word line driver circuits coupled to the word lines of the first and second memory sub-arrays. A row decoder region adjacent the first region and separate from the driver region includes at least some sub-circuits of row decoder circuits located therein. The row decoder circuits are coupled to the word line driver circuits located in the driver region and are configured to activate driver circuits to drive word lines of the first and second memory sub-arrays in response to decoding address signals selecting the particular row decoder circuit.

Abstract: A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.

Abstract: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.

Abstract: A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

Abstract: A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an insulation circuit for electrically insulating the sense amplifier circuit from the data line during an operation period of the write driver.

Abstract: Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance, a control unit is provided for generating a first control signal for the connection switch, and the circuit arrangement is designed to be operated in two operating modes, in which case in a power saving mode, the connection switch is switched by the control unit to have a high resistance, and in a security node, the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.

Abstract: A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain coupled to the first bit line via a first node, and a first source coupled to a predetermined potential, a second MIS transistor having a second gate coupled to the selection line, a second drain coupled to the second bit line via a second node, and a second source coupled to the predetermined potential, and a latch circuit coupled to the first node and the second node to store data responsive to a signal difference between the first node and the second node, wherein the selection line is operative to supply a write potential that creates a lingering change in a threshold voltage of one of the first MIS transistor and the second MIS transistor.

Abstract: The application discloses a semiconductor memory storage device comprising: a data retention portion comprising latches; a peripheral portion comprising read and write logic; and a power switching device wherein said peripheral portion is operable to be powered by a periphery voltage difference; said data retention portion is operable to be powered by a data retention voltage difference said data retention voltage difference being different to said periphery voltage difference; and in response to a write request signal to write to at least one of said latches output from said peripheral portion to said data retention portion by said write logic, said power switching device is operable to reduce a voltage difference across said at least one of said latches such that a data signal output from said peripheral portion and having a voltage level determined by said periphery voltage difference is able to write to said at least one of said latches.

Abstract: An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and an internal sensing unit. The internal driving unit is configured to generate a driving current and a preliminary voltage responsive to an external supply voltage that is supplied from external to the semiconductor memory device, and it varies a magnitude of the driving current responsive to a driving control signal. The internal transmission unit is configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage. The boosted voltage is greater than the external supply voltage.

Abstract: A random access memory that includes an array of memory cells, a first circuit configured to receive an address to address memory cells in the array of memory cells, and a second circuit. The second circuit is configured to obtain control signals including an address strobe signal and gate the address strobe signal using other control signals to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal.

Abstract: A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. Accordingly, unnecessary current consumed in the read operation can be reduced.

Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

Abstract: A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

Abstract: A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

Abstract: Disclosed herein is a semiconductor memory device having a pair of local data lines with a delayed precharge voltage application point. The semiconductor memory device of the present invention includes a delay block for delaying the activation time of a block write control signal, thus lengthening the interval starting from the time when data on a pair of bit lines are amplified to the time when a supply voltage is applied to a pair of local data lines. Therefore, according to the semiconductor memory device of the present invention, the time when the supply voltage is applied to the pair of local data lines is the time after data have sufficiently stabilized on the pair of bit lines. Therefore, the semiconductor memory device of the present invention prevents the stabilization speed of the pair of bit lines and the pair of local data lines from decreasing, thus consequently improving the operating speed of the semiconductor memory device.

Abstract: The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

Abstract: A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value during an initial value setting operation; a first power supply circuit, which supplies power to bitlines in response to the first control signal; a second power supply circuit, which supplies power to complementary bitlines in response to the second control signal; a plurality of wordlines connected to respective memory cells; and a row decoder, which selects a group of wordlines from among the plurality of wordlines based on the setting signal and a selection address and simultaneously activates the selected group of wordlines.

Abstract: A semiconductor memory having memory cells each storing first data and second data in a memory cell array arranged in a column direction; a plurality of word lines connected to the memory cells in a row direction; and first and second bit lines, to which the first and second data are respectively read out, in the column direction. When one of the first and second bit lines changes from a first potential to a second potential lower than the first potential after data read out, the potential of the other bit line is changed from the second to the first potential, and if the electric potential of the selected bit line changes from the first to the second potential when data is read out, the other bit line is selected when the data is next read out, and, if the electric potential of the selected bit line maintains the first potential, the selected bit line is maintained selected even when the data is to be read out next.

Abstract: Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.

Abstract: A sense amplifier power-gating circuit and method is disclosed which is of particular utility with respect to DRAM devices, or those incorporating embedded DRAM, and having a power-down (or Sleep) mode of operation. In accordance with a particular technique of the present invention, the local sense amplifier driver transistors serve a dual purpose as both driver and power gate transistors thereby obviating the need for large, distinct power-gating devices. This serves to minimize on-chip area requirements while not degrading sensing speed as in conventional approaches.

Abstract: A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

Abstract: A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

Abstract: In a self refresh period control circuit for controlling a refresh period of a semiconductor memory device in response to operating temperature of the device, a temperature sensor part generates a first period control signal in response to a self refresh start signal or self refresh completion signal, senses operating temperature of the semiconductor memory device in response to a clock signal generated by the self refresh start signal, and generates a corresponding second period control signal. A period magnification control part controls a self refresh period in response to the first and second period control signals. Accordingly, a refresh period characteristic change based on operating temperature, which is causable by an initial self refresh, is implemented.

Abstract: A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, comprising: a step for dividing the memory array into a holding area used as a copy source which includes memory cells on a predetermined number of word lines, and a copy area used as a copy destination which includes memory cells on word lines to which entire data of the holding area is to be copied, a step for executing copy operation in which data of each memory cell of the holding area is copied to one or more memory cells in the copy area on the same bit line or the same pair of bit lines before executing the self-refresh operation, and a step for executing the self-refresh operation in which a row address of the holding area is designated and a corresponding word line is selected and driven, and at the same time, one or more