Abstract: The present invention is a monolithic, multi-colored LED chip and a method for making the same. The LED chip is comprised of a substrate and a plurality of light emitting structures, each light emitting structure capable of emitting a wavelength of light unique compared to others and each structure layered on top of another structure and separated by a dielectric layer. The light emitting structures are then capable of independent or tandem activation, yielding the original colors of each section, blends of colors, and white light. The method starts with the base for such a chip and etches layers of the chip away, leaving exposed sections, to reach electrical contact layers for each light emitting structure. Electrically conductive material is then used to fill the exposed sections and is, in turn, etched away to leave contacts. An insulating material is then used to fill in the resultant areas.

Abstract: A semiconductor light-emitting device including a light-emitting layer forming portion, a semiconductor substrate of a first conductivity type, a first electrode which is disposed on a surface of the semiconductor substrate of the first conductivity type, a semiconductor substrate of a second conductivity type, and a second electrode which is disposed a surface of the semiconductor substrate of the second conductivity type, at least one of the semiconductor substrate of the first conductivity type and the semiconductor substrate of the second conductivity type having an interstice located near an outer side surface on a side close to the light-emitting layer forming portion and around a joined surface on a principal surface of the light-emitting layer forming portion.

Abstract: Disclosed are an inorganic electroluminescent diode and a method of fabricating the same. Specifically, this invention provides an inorganic electroluminescent diode, which includes a semiconductor nanocrystal layer formed of inorganic material, an electron transport layer or a hole transport layer formed on the semiconductor nanocrystal layer using amorphous inorganic material, and a hole transport layer or an electron transport layer formed beneath the semiconductor nanocrystal layer using inorganic material, and also provides a method of fabricating such an inorganic electroluminescent diode. According to the method of fabricating the inorganic electroluminescent diode of this invention, an inorganic electroluminescent diode can be fabricated while maintaining the properties of luminescent semiconductor material of the semiconductor crystal layer, and also an inorganic electroluminescent diode which is stably operated and has high luminescent efficiency can be provided.

Abstract: A lighting device, comprising at least one solid state light emitter, at least one first lumiphor and at least one second lumiphor which is spaced from the first lumiphor. The solid state light emitter can be a light emitting diode. A method of making a lighting device, comprising positioning at least one second lumiphor spaced from and outside of at least one first lumiphor relative to at least one solid state light emitter. A method of lighting, comprising providing electricity to at least one solid state light emitter in such a lighting device.

Abstract: A semiconductor light emitting device capable of improving the light extraction efficiency while preventing deterioration of the light emission characteristic with time and a semiconductor light emitting device assembly including the semiconductor light emitting device are provided. The semiconductor light emitting device includes a semiconductor light emitting element containing a metal element, a cap portion formed from a material which contains a sulfur or halogen element and which is capable of transmitting the light from the semiconductor light emitting element, and a shielding film which is disposed between the semiconductor light emitting element and the cap portion, which transmits the light from the semiconductor light emitting element to the cap portion, and which separates the semiconductor light emitting element side and the cap portion side.

Abstract: A color sensor integrated light emitting diode (LED) is packaged with LED and color sensor mounted side by side inside LED package comprising a heat sink for mounting LED and the color sensor, both the color sensor and LED being buried by a high refractive index polymer followed by a diffuser layer and light extraction layer, all of which are transparent. Posts electrically linked to LED and color sensor inside the package are provided for external connection to LED and color sensor. Plurality of color sensors and LEDs can be packaged inside a single package with proper orientation of desired color LEDs to receive desired color by color sensors. Color change at the very source of light emission can be controlled with color sensor integrated LED package more effectively than conventional methods. Plurality of these packages can be employed for LED backlight for LCD, consumer lighting, decorative lighting and signage displays.

Abstract: A package includes a substrate with a recess in which a light emitting element is mounted. A surface of the substrate forms an exterior surface of the package. A lid may be attached to the substrate to define a sealed region in which the light emitting element is mounted. The lid is transparent to a wavelength of light emitted by the light emitting element. Electrostatic discharge protection circuitry in the substrate is electrically coupled to the light emitting element.

Abstract: A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator is in operation providing 1.2V supply to the core. If 1.2V is available on board, all 1.2V pads are bonded to the package pins and VDDCO pad is left unbonded. A weak pulldown ensures that the regulator is inoperational and the gate voltage of ballast transistor is pulled up. Now 1.2V pads directly get supply from the board through package pins and is provided to the core without suffering IR drop.

Abstract: A light emitting module of a lighting device has a casing, a heat radiating member and terminals. The terminals extend from the casing and connects to a circuit board disposed along a light diffusing member. The heat radiating member extends in a direction perpendicular to the terminals. Alternatively, the terminals are connected to heat radiating lands formed on a second circuit board that is provided separately from a first circuit board and the heat radiating member is connected to a heat radiating land formed on the second circuit board. Further, the heat radiating member can be connected to a heat radiating plate overlapping with the second circuit board, in place of the heat radiating land.

Abstract: The optical mounting package of the present invention is featured by mounting a silicon frame on an insulating substrate for mounting the optical element. The package of the present invention is also featured by that the frame mounted on the insulating substrate for mounting the optical element is made of silicon. A method of manufacturing the package of the present invention is featured by mounting the silicon wafer on the insulating substrate.

Abstract: A packaged LED includes a substrate, an LED chip on the upper surface of the substrate, a first encapsulant material, including a reflective material, on the substrate and spaced apart from the LED chip, and a second encapsulant material on the LED chip. A method of forming a packaged LED includes forming a first meniscus control feature on a substrate and defining a first region of the substrate, forming a second meniscus control feature surrounding the first region and defining a second region of the substrate between the first meniscus control feature and the second meniscus control feature, mounting an LED chip within the first region, dispensing a first encapsulant material including a reflective material within the second region, curing the first encapsulant material, dispensing a second encapsulant material on the substrate within the first region, and curing the second encapsulant material.

Abstract: An organic light emitting device according to one embodiment of the present invention comprises a first substrate defining a pixel region and a non-pixel region; an array of organic light emitting pixels formed in the pixel region of the first substrate; a second substrate placed over the first substrate, the array being interposed between the first and second substrates; a frit seal interposed between and interconnecting the first and second substrates, wherein the frit seal comprises a plurality of elongated segments, which in combination surrounds the array; and at least one conductive line formed in the non-pixel region and elongated substantially parallel to one of the plurality of elongated segments of the frit seal, wherein no conductive line in the non-pixel region is elongated substantially parallel to one of the elongated segments and overlaps the elongated segment substantially parallel thereto when viewed from the first or second substrate.

Abstract: The leads of a light emitting diode are made coaxial. The inner lead protrudes lower than the outer lead. The package is inserted into a spongy display panel for power supply. The display panel has three layers: a lower conducting layer for contacting said inner lead and a top conducting layer for contacting said outer layer, and an insulating layer between the top and the bottom layer. For LED with a bottom electrode and a top electrode, the LED can be mounted on the planar tops of the inner lead and the top electrode wire bonded to the outer lead, or the LED can be mounted on the side surface of the inner lead and the top electrode wire bonded to the outer lead. For LED with two bottom electrode, the LED electrodes can straddle over the planar tops of the inner lead and the outer lead, or the LED electrodes can straddle over the telescopic side surfaces of the two leads.

Abstract: An object of the present invention is to provide a gallium nitride compound semiconductor multilayer structure useful for producing a gallium nitride compound semiconductor light-emitting device which operates at low voltage while maintaining satisfactory light emission output. The inventive gallium nitride compound semiconductor multilayer structure comprises a substrate, and an n-type layer, a light-emitting layer, and a p-type layer formed on the substrate, the light-emitting layer having a multiple quantum well structure in which a well layer and a barrier layer are alternately stacked repeatedly, said light-emitting layer being sandwiched by the n-type layer and the p-type layer, wherein the well layer comprises a thick portion and a thin portion, and the barrier layer contains a dopant.

Abstract: A Group III nitride semiconductor light-emitting device having a stacked structure includes a transparent crystal substrate having a front surface and a back surface, a first Group III nitride semiconductor layer of first conductive type formed on the front surface of the transparent crystal substrate, a second Group III nitride semiconductor layer of second conductive type which is opposite from the first conductive type, a light-emitting layer made of a Group III nitride semiconductor between the first and second Group III nitride semiconductor layers, and a plate body including fluorescent material, attached onto the back surface of the transparent crystal substrate.

Abstract: A nitride semiconductor light generating device comprises an n-type gallium nitride based semiconductor layer, a quantum well active layer including an InX1AlY1Ga1-X1-Y1N (1>X1>0, 1>Y1>0) well layer and an InX2AlY2Ga1-X2-Y2N (1>X2>0, 1>Y2>0) barrier layer, an InX3AlY3Ga1-X3-Y3N (1>X3>0, 1>Y3>0) layer provided between the quantum well active layer and the n-type gallium nitride based semiconductor layer, and a p-type AlGaN layer having a bandgap energy greater than that of the InX2AlY2Ga1-X2-Y2N barrier layer. The indium composition X3 is greater than an indium composition X1. The indium composition X3 is greater than an indium composition X2. The aluminum composition Y2 is smaller than an aluminum composition Y3. The aluminum composition Y1 is smaller than an aluminum composition Y3. The oxygen concentration of the quantum well active layer is lower than that of the InX3AlY3Ga1-X3-Y3N layer.

Abstract: A MEMS switch and a method of manufacturing the same are disclosed. The MEMS switch includes: a substrate including a trench, a ground line and a signal line having an opened portion; a moving plate separated from the substrate at a predetermined space and including a contact member for connecting an electrode plate and the opened portion and having a deep corrugate to insert the trench; and a supporting member for supporting the moving plate. Such a MEMS switch prevents the thermal expansion and the stiction problem.

Abstract: An object of the present invention is to provide a gallium nitride compound semiconductor light-emitting device having a positive electrode that exhibits low contact resistance with a p-type gallium nitride compound semiconductor layer and that can be fabricated with high productivity.

Abstract: A novel structure of photo sensor is disclosed. The equivalent circuit of the invented photo sensor comprises a photo transistor integrated with a surface photo sensor. The structure of the surface photo sensor is substantially identical to the base-emitter junction of the photo transistor and may be prepared in the same process. The junction depletion region of the surface photo sensor locates adjacent to the light incident surface, whereby decay of incident light is minimal and more electron-hole pairs are generated. The present invention also discloses semiconductor material containing the invented photo sensor assembly of the invented photo sensor and method for preparation of the photo sensor, the semiconductor material and their assemblies.

Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: A level shifter for a flat panel display device is provided. A first transistor has a first transistor source, a first transistor gate, and a first transistor drain. The first transistor source is connected to a first power supply and the first transistor gate and the first transistor drain are connected together. A capacitor is connected between an input voltage terminal and a first node with the first node connected to the first transistor gate and the first transistor drain. A second transistor is connected with the first node to reset the capacitor. A third transistor has a third transistor gate, a third transistor source, and a third transistor drain. The third transistor gate is connected to the first node, and the third transistor source and the third transistor drain are connected between a second power supply and an output voltage terminal. A fourth transistor has a fourth transistor gate, a fourth transistor source, and a fourth transistor drain.

Abstract: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type compound semiconductor thin film layer containing at least one of Ga, Al and In as a Group III element and As as a Group V element under such growth conditions that the growth rate gives a growth determined by a Group V gas flow rate-feed.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. The one of the capacitor and the variable capacitance diode includes a first electrode formed in a first area and a second area, a second electrode formed in the first area with the first gate oxide layer inbetween, and a third electrode formed in the second area with the second gate oxide layer inbetween.

Abstract: A method for manufacturing a semiconductor substrate includes: forming an element isolation layer on a semiconductor base material for separating an element region from the other regions; forming a first semiconductor layer on the semiconductor base material; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etching selection ratio smaller than that of the first semiconductor layer; forming support holes by removing portions of the first semiconductor layer and the second semiconductor layer, the portions corresponding to regions for the support holes; forming a support forming layer on the semiconductor base material such that the support holes and the second semiconductor layer are covered by the support forming layer; forming exposed surfaces such that portions of the support forming layer other than a region including the support holes and the element region are etched to expose a support and portions of end portions of the first semiconductor

Abstract: A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

Abstract: The solid-state imaging device of the present invention includes: a floating diffusion capacity unit which is formed on a semiconductor substrate, and is operable to hold signal charges derived from incident light; an amplifier which is operable to convert the signal charges held in the floating diffusion capacity unit into a voltage; the first wire which connects the floating diffusion capacity unit to an input of the amplifier; and a second wire which is made of the same material as the first wire, formed in the same layer as the first wire, arranged around the first wire at least along long sides of the first wire, and electrically insulated from the first wire.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits comprise a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line comprises a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further comprise gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan current flow. A system is also described, including the previously described device and a second transistor. The pathway for the flow of the majority of the current carriers in the device defines a first direction. The second transistor also has at least two terminals, and a pathway for a majority of current carriers between the two terminals defines a second direction. The angle between the first direction and the second direction is nonzero and acute.

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a non-planar type transistor region having at least one of a fin type transistor region including a fin type transistor in which a current is induced to flow through side faces of a fin formed approximately vertically to a surface of the semiconductor substrate in a direction approximately parallel to the surface of the semiconductor substrate, and a tri-gate type transistor region including a tri-gate type transistor in which a channel is formed in three surfaces having side faces and an upper surface of a fin formed approximately vertically to the surface of the semiconductor substrate, and thus a current is induced to flow through the three surfaces in a direction approximately parallel to the surface of the semiconductor substrate; and a filling material for isolation in the non-planar type transistor region within the semiconductor substrate and which has a plurality of regions having differen

Abstract: In a mounting structure of an image pickup device, an optical member allowing light to pass through is bonded to one side of an electric substrate with an adhesive with the image pickup device bonded to the other side of the electric substrate. In this structure, the hardness of an adhesive for bonding the image pickup device differs from the hardness of the adhesive for the optical member. The difference in hardness between the adhesives can reduce the influence of a difference in expansion coefficient between the image pickup device and the optical member. For example, the hardness of the adhesive for bonding the optical member can be set lower than that of the adhesive for bonding the image pickup device.

Abstract: A photodetector includes a substrate and a layer of Ge formed on the substrate. A plurality of n-type doped regions and a plurality of p-type doped regions are formed in Ge region. These doped regions formed an alternating pattern. Electrodes are formed on n-type doped regions and on the p-type doped regions. The utilization of transparent electrodes increases the sensitivity of the photodetector without impacting speed.

Abstract: A plurality of light receiving elements are arranged in a matrix with uniform space therebetween in a light receiving region defined on a semiconductor substrate. A plurality of read-out electrodes are formed on the semiconductor substrate in an arrangement corresponding to the light receiving elements to read charges generated by the light receiving elements, a light shield film having openings positioned above the light receiving elements is formed to cover the read-out electrodes, first optical waveguides are formed in the openings above the light receiving elements and second optical waveguides are formed on the light shield film. The second optical waveguides are in the form of dots, stripes or a grid when viewed in plan.

Abstract: A solid-state imaging device comprising a plurality of pixels arrayed on a plane, wherein each of the pixels includes a semiconductor substrate and a plurality of photoelectric conversion devices, the plurality of photoelectric conversion devices include at least one on-substrate photoelectric conversion device stacked in an upper portion of the semiconductor substrate and at least one in-substrate photoelectric conversion device provided within the semiconductor substrate in a lower portion of the on-substrate photoelectric conversion device, and the plurality of photoelectric conversion devices have a different photoelectric conversion sensitivity from each other.

Abstract: A polarization transfer device includes a ferroelectric thin film formed continuously as one piece; a plurality of polarization switches formed by placing the ferroelectric thin film between a first gate electrode and a second gate electrode; and a plurality of polarization accumulators formed by placing the ferroelectric thin film between a first electrode plate and a second electrode plate, wherein the plurality of polarization switches and the plurality of polarization accumulators are arranged alternately.

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract: A semiconductor storage device including a capacitor whose stored signal quantity is large with respect to its area share ratio, and a manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a transistor formed on a semiconductor substrate, a capacitor which is formed above the transistor and includes a lower electrode, a dielectric film and an upper electrode, a semi-insulating layer formed in a side edge of the upper electrode and formed by locally transforming the upper electrode, an insulator formed to cover the capacitor, and a wiring line connected with the upper electrode.

Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

Abstract: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.

Abstract: A semiconductor memory device includes a plurality of memory cells. Each memory cell includes a capacitor which is composed of a first electrode, at least one particle made of ferroelectric or high dielectric constant material and selectively arranged on the first electrode, and a second electrode formed on the particle.

Abstract: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: A capacitor of a semiconductor device and a method for fabricating the same may be provided. The method may include forming an interlayer insulation layer, an etch stop layer, and/or a sacrificial insulation layer on a semiconductor substrate, patterning the interlayer insulation layer, the etch stop layer, and/or the sacrificial insulation layer to form a contact hole exposing a desired or predetermined region of the semiconductor substrate, filling the contact hole to form a contact plug, removing the sacrificial insulation layer to expose an upper portion of the contact plug, and/or forming a dielectric layer and/or a top electrode on the exposed upper portion of the contact plug.

Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract: The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.

Abstract: A non-volatile memory is described, including a substrate, a floating gate, a control gate, a source region, and a drain region. A trench is disposed in the substrate, and a step-like recess is located in the substrate beside the trench. The floating gate is disposed on the sidewall of the trench. The control gate is disposed on the substrate between the trench and the step-like recess which extends in the step-like recess. The source region is disposed in the substrate at the bottom of the trench. The drain region is disposed in the substrate at the bottom of the step-like recess.