Abstract: A trench dummy element isolating region is formed in the fuse region of a semiconductor substrate. In the semiconductor substrate, a plurality of dummy element regions is formed so as to be enclosed by the trench dummy element isolating region. The occupancy rate of the plurality of dummy element regions in the fuse region is equal to or larger than a specific value. On the semiconductor substrate including the dummy element isolating region and dummy element regions, a plurality of metal fuses composed of multilayer metal wiring lines are formed via an interlayer insulating film. The plurality of dummy element regions are formed only below at least a part of the plurality of metal fuses.

Abstract: In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the fuse barrier pattern.

Abstract: An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

Abstract: The semiconductor device includes a semiconductor substrate, a plate electrode, and a metal layer. The semiconductor substrate includes a capacitor region and a dummy region. The plate electrode is formed over the semiconductor substrate, wherein a dummy plug of the plate electrode is formed in the dummy region. The metal layer is formed over the plate electrode, the metal layer being in contact with the dummy plug.

Abstract: After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is exposed in a depressed portion surrounded by the sidewall insulating film. Subsequently, a first metal film is deposited and then a thermal process is performed to change the silicon film into a first metal film. Thereafter, an insulating film and a second metal film are buried in the depressed portion. The insulating film composes the capacitor insulating film of a capacitor element. The first metal silicide film and the second metal film compose the lower and upper electrodes of the capacitor element, respectively.

Abstract: A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.

Abstract: A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a second indentation region provided between the first indentation region and the flat region, formed with second recesses, and having a lower probability of occurrence of growth nuclei than the first indentation region and a higher probability than the flat region in the case where a crystal of a semiconductor is grown on the main surface.

Abstract: A semiconductor device structure includes a passivation layer through which only non-semiconductor material-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed semiconductor material-comprising surface by exposing surfaces of the semiconductor device to a liquid phase solution supersaturated in an oxide of the semiconductor material. Such a solution may include a hexafluoro acid of the semiconductor material. The oxide and acid may be present in amounts that facilitate deposition of the oxide onto exposed semiconductor material-comprising structures. The exposure may be conducted at substantially atmospheric temperature and pressure and may form a passivation layer in an abbreviated time, and without subsequent heat treatment.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: Methods and apparatuses for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise a method of placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Abstract: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.

Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.

Abstract: A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.

Abstract: A method of forming a mold, concludes: winding a tape around peripheral surfaces of a first molding die and a second molding die to assemble a mold; forming on the tape an injection port for injecting a resin material for forming a plastic lens into the mold; and forming a tab by cutting out a part of the tape non-circularly.

Abstract: A stacked integrated circuit package system is provided providing a lead frame having a die paddle, attaching a first integrated circuit on the die paddle of the lead frame, connecting first electrical interconnects between the first integrated circuit and the lead frame, encapsulating the first integrated circuit and the first electrical interconnects, attaching a second integrated circuit on the die paddle of the first integrated circuit, connecting second electrical interconnects between the second integrated circuit and the lead frame, and encapsulating the second integrated circuit and the second electrical interconnects.

Abstract: An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the lead finger.

Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices.

Abstract: A semiconductor photodetector which can obtain spectral sensitivity characteristics close to relative luminous characteristics compared to a conventional semiconductor photodetector is obtained at low cost. The semiconductor photodetector includes a semiconductor light receiving element having high spectral sensitivity in wavelengths in a range from approximately 400 nm to 1,100 nm and an optical transmitting resin where micro particles is dispersed in a transparent resin with an amount which can be obtain photocurrent from the semiconductor light receiving element by transmitting light in wavelengths in the visible light region while blocking light in wavelengths in the infrared region. The semiconductor photodetector further includes a converging structure on a light receiving surface of the semiconductor photodetector.

Abstract: A light emitting module includes a metal substrate, a bearing base, at least one LED, a printed circuit board, and at least one conductive wire. A first perforation is formed on the metal substrate and the bearing base is embedded into the first perforation of the metal substrate. According to an eutectic soldering method, the LED(s) is/are adhered on the bearing base by a compound metal. A second perforation is formed on the printed circuit board to expose the LED(s) which is/are adhered on the bearing base and further allows the printed circuit board to stick on the metal substrate. The conductive wires are used to connect electrically the LED(s) with the printed circuit board.

Abstract: A smart card module including a substrate having an upper face and a lower face, contact arrays arranged on the substrate lower face, conductor structures, which have vias arranged in cutouts in the substrate, arranged on the substrate upper face and connected to the contact arrays, a chip having connecting contacts which are electrically conductively connected to the conductor structures, wherein the chip is mounted by a mount on the substrate upper face or on the conductor structures, and an encapsulation, which covers the chip and at least a part of the conductor structures and of the substrate upper face.

Abstract: A radio frequency (RF) module and a multi RF module including the same include a base substrate, a first element capable of processing RF signals formed on the base substrate, a second element capable of processing RF signals separated from and disposed over the first element, a cap substrate coupled with the base substrate to encapsulate the first and second elements including a plurality of through electrodes that electrically connect the first and second elements to the outside, and a bonding pad that encapsulates and joins the base substrate and the cap substrate and electrically connects the first and second elements to the through electrodes.

Abstract: A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, and the land section includes a first section which is in contact with the underlayer, and a second section which is not in contact with the underlayer.

Abstract: A semiconductor memory card which inputs/outputs signals by connecting to an external device, has a circuit board on an upper surface of which board terminals connected to board wiring are formed, and on a lower surface of which input/output card terminals for inputting/outputting signals to/from the external device, a power supply card terminal for supplying electric power, and a ground card terminal connected to ground potential by connecting to the external device are provided; a nonvolatile memory chip which is mounted on the upper surface of the circuit board, and has a plurality of first bonding pads formed close to a first side of the nonvolatile memory chip in a manner that the plurality of first bonding pads are wire-bonded to a plurality of first board terminals formed on the circuit board along the first side; and a controller chip which is mounted on the nonvolatile memory chip, and has a plurality of second bonding pads formed in a manner that the plurality of second bonding pads are wire-bonded

Abstract: A package is made of a transparent substrate having an interferometric modulator and a back plate. A non-hermetic seal joins the back plate to the substrate to form a package, and a desiccant resides inside the package. A method of packaging an interferometric modulator includes providing a transparent substrate and manufacturing an interferometric modulator array on a backside of the substrate. A back plate is provided and a desiccant is applied to the back plate. The back plate is sealed to the backside of the substrate with a back seal in ambient conditions, thereby forming a package.

Abstract: Provided are in-line semiconductor chip packaging apparatuses that include a buffer assembly in which a reversing unit rotates a lead frame 180° between die attaching and/or wire bonding operations and methods of manufacturing an integrated circuit chip package using such an in-line integrated circuit chip packaging apparatus. Between packaging process operations, the lead frame, which includes first and second surfaces may be rotated, thereby reversing the orientation of the first and second surfaces. The apparatuses will include one or more processing units for attaching semiconductor chips to the leadframe, or a previously mounted semiconductor chip, or for forming wire bonds between the attached semiconductor chip(s) and the corresponding lead fingers of the lead frame, attached to and/or separated by an in-line buffer assembly that includes a reversing unit.

Abstract: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die module is a substrate for the second die. The second die is electrically attached to the known good die module. At least the second die is additionally encapsulated.

Abstract: A system (100), which has an electrically insulating substrate (101) with a thickness, a first and a second surface. Electrically conductive paths (110) extend through the insulating body from the first to the second surface and have exit ports (120) at the end of the conductive paths on the first and the second surface. A cavity (130) extends downwardly from the first surface to a depth less than the thickness; the bottom of the cavity and the first substrate surface have contact pads (141). The substrate further has electrically conductive lines (150) between the first and the second surface and under the cavity, contacting the paths. The system includes a stack of semiconductor chips (160,170) with bond pads; one chip is attached to the bottom of the cavity and one chip is electrically connected to substrate contact pads.

Abstract: A multi-chip stack structure includes a chip carrier, a plurality of chips stacked stepwise on the chip carrier, and a passive component disposed on the chip carrier. The passive component is located under the stepwise chips that are cantilevered over it. Therefore, the passive component serves as a block element or a filling element in the molding process, and problems such as chip peeling void are prevented. Meanwhile, the electrical properties of the package are improved.

Abstract: The semiconductor device with which bonding wires cannot contact easily is offered. In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.

Abstract: A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A semiconductor device includes surface-mountable external contacts on an underside of the semiconductor device, wherein the external contacts are arranged on external contact pads and surrounded by a solder-resist layer. The external contacts of the outer edge regions include external contact pads that merge into inspection tags, wherein the inspection tags can be wetted by solder and are not covered by the solder-resist layer.

Abstract: A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern except for the portions of the first insulating film corresponding to the upper electrodes, a second insulating film covering at least another metal pattern except for the portions of the second insulating film corresponding to the external terminals, and a semiconductor element connected to the upper electrodes and placed on the substrate for semiconductor device. The solder-connected surface of the external terminal is positioned to have a height larger than that of a surface of the second insulating film. The semiconductor element is placed on the first insulating film and covered, together with the upper electrodes, with a mold resin.

Abstract: A method of manufacturing a semiconductor substrate includes: forming on a semiconductor base a first isolation layer for isolating an element region from another region; forming a first semiconductor layer on the semiconductor base; forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an etch selectivity less than that of the first semiconductor layer; forming a support hole by removing a portion of the second semiconductor layer and a portion of the first semiconductor layer each corresponding to the support hole; forming a support formation layer above the semiconductor base so as to cover the support hole and the second semiconductor layer; forming a support and an exposed surface for exposing part of an end of each of the first semiconductor layer and the second semiconductor layer by etching an area other than that including the support hole and the element region therein, the first semiconductor layer and the second semiconductor layer being locat

Abstract: A cooling apparatus for a circuit module having a substrate extending axially with an IC chip of a first type and IC chips of a second type mounted thereon, comprising: a first heat spreading element disposed to form a heat conduction path with the IC chip of the first type; and a second heat spreading element disposed to form a heat conduction path with the IC chips of the second type, wherein there is at least one IC chip of the second type mounted axially away from opposite sides of the IC chip of the first type, wherein the first type of IC chip is capable of generating a larger amount of heat than the second type of IC chips, and the first heat spreading element has a higher thermal conductivity than the second heat spreading element.

Abstract: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles can optionally be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material which includes silicon can be used to bond the diamond particles together either through filling voids between diamond particles or by acting as a sintering aid. The final heat spreader exhibits superior heat transfer properties advantageous in removing heat from various sources such as electronic devices and minimized difference in thermal expansion from the heat source.

Abstract: A component-containing module includes a module substrate having first wiring lines provided on the top surface of the module substrate, a first circuit component mounted on the first wiring lines of the module substrate, a submodule substrate having an area smaller than the area of the module substrate and mounted on the first wiring lines of the module substrate at a position at which the first circuit component is not mounted, a second circuit component mounted on second wiring lines provided on the top surface of the submodule substrate, and an insulating resin layer provided on the entire top surface of the module substrate so as to encompass the first circuit component, the second circuit component, and the submodule substrate.

Abstract: A low profile radio frequency (RF) module and package with efficient heat dissipation characteristics, and a method of assembly thereof, are provided. In some embodiments, the RF module package comprises a radio frequency integrated circuit (RFIC) attached to a recessed area of a lead frame. The RFIC has an active integrated circuit pattern and a plurality of conductors formed on input/output pads of the active integrated circuit pattern. An integrated passive device (IPD) is attached to the RFIC via the plurality of conductors. The IPD has a passive integrated circuit pattern, a plurality of electrode pads connected to nodes of the passive integrated circuit pattern, and metal-filled vias for electrically connecting the electrode pads to the plurality of conductors. The RFIC includes a plurality of heat conducting vias for conducting heat to the lead frame.

Abstract: A semiconductor device and method has interconnects with adjoining reservoir openings. A dielectric layer is formed as part of an uppermost of the one or more interconnect layers. Openings formed in the dielectric layer result in modified portions of the dielectric layer along portions of sidewalls of the openings. The openings are filled with a conductive material, such as metal. An exposed portion of the dielectric layer is removed to form protruding pads of the conductive material extending above the dielectric layer. Reservoir openings are formed adjacent the protruding pads by removing the modified portions of the dielectric layer. When the semiconductor device is bonded with another device, either a wafer or a die, laterally flowing metal collects in the reservoir openings and ensures that a reliable electrical connection is made between the semiconductor device and the other device.

Abstract: A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer along a sidewall of a first opening in a first dielectric layer, located over the surface of the integrated device, and providing a deformable metal feature adjacent to the sidewall spacer and in the first opening. The method further includes providing a second integrated device having a substrate, an overlying interconnect region, a contact, and a second dielectric layer surrounding the contact of the second integrated device. The method further includes contacting the contact of the second integrated device with the deformable metal feature and pressing the first dielectric layer against the second dielectric layer.

Abstract: Disclosed are a printed circuit board for a semiconductor package and a method of manufacturing the same. Specifically, a printed circuit board for a semiconductor package includes predetermined circuit patterns, having a wire bonding portion and a bump portion for mounting a semiconductor and a soldering portion for connection to external parts, in which the bump portion has a pre-solder formed using a tin or tin alloy electroplating process. According to this invention, the pre-solder, which is formed by reflow using an electroplating process, permits easy increase of the height thereof to thus enhance bondability and underfilling capability, may be formed to a desired thickness by controlling a plating thickness, and furthermore, may be applied to a fine pitch through a masking process.

Abstract: A ball grid array includes: a semiconductor chip having multiple pads; and an interposer for mounting the semiconductor chip on a first surface. The interposer includes multiple wirings on the first surface and multiple ball terminals on a second surface opposite to the first surface. Each wiring is connected to a corresponding pad of the semiconductor chip, and is electrically connected to a corresponding ball terminal. At least one of ball terminals providing a power supply terminal or a ground terminal provides a common ball terminal for connecting to at least two of the pads of the semiconductor chip through two wirings.

Abstract: A conductive layer is formed in or on a substrate. A first metal film is then formed on the substrate including the conductive layer. The substrate is then subjected to heat treatment to allow the first metal film to react with the conductive layer to thereby form a silicide film selectively on the conductive layer. A second metal film is then formed only on the silicide film by selective CVD. An insulating film is then formed over the substrate including the second metal film. A predetermined region of the insulating film is removed to form a contact hole reaching the second metal film. The inside of the contact hole is cleaned to remove a degenerated layer formed on the surface of the second metal film existing on the bottom of the contact hole.

Abstract: A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.

Abstract: The semiconductor device comprises on a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.

Abstract: An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exterior to the second solder composition, the first solder composition, and the first component.

Abstract: A hole is defined in a body of a product. A conductor made of zinc or a Zn—Al alloy fills the hole. Zinc or the Zn—Al alloy melts at a temperature equal to or higher than 375 degrees Celsius. Molten Zinc or Zn—Al alloy reliably fills the hole. Zinc and Zn—Al alloy have an electric conductivity. The hole can reliably be filled up with a conductor. The product reliably remains solid even when the product is secondarily exposed to a heat causing a solder alloy to melt. If Zn—Al alloy is utilized in the product, the Zn—Al alloy preferably contains aluminum at a content equal to or smaller than 1.0 weight %. The melting point of such a Zn—Al alloy can be kept equal to or higher than 400 degrees Celsius. The Zn—Al alloy can thus remain solid during a high temperature treatment such as anodic bonding.