Patents Issued in August 7, 2007
  • Patent number: 7253010
    Abstract: A crystallization method is provided which improves a crystallization process by deciding a best-fit focal plane for a laser beam using a test mask and then applying the decided best-fit focal plane to the crystallization process. The crystallization method includes loading a test mask on a mask stage; deciding a best-fit focal plane by performing a crystallization test using the test mask, checking the test result and deciding conditions of a best-fit focal plane from the test result; moving the mask stage to a position corresponding to the best-fit focal plane; loading a mask for crystallization process onto the moved mask stage; and performing the crystallization process using the mask for crystallization process.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 7, 2007
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Hyun Sik Seo, Yun Ho Jung, Young Joo Kim, JaeSung You
  • Patent number: 7253011
    Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, the present invention makes it possible to prevent run-off of ionized amine into the ultrapure water.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: August 7, 2007
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Osamu Takahashi, Kunio Ogasawara
  • Patent number: 7253012
    Abstract: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. A plurality of guard rings may be used that enclose respective arrays of matched devices arranged over the surface of a semiconductor wafer. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, local and global matching are achieved.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: August 7, 2007
    Assignee: Agere Systems, Inc.
    Inventors: Daniel Charles Kerr, Roscoe T. Luce, Michele Marie Jamison, Alan Sangone Chen, William A. Russell
  • Patent number: 7253013
    Abstract: A method for manufacturing a light-emitting diode (LED) is described. The method comprises: providing a temporary substrate; forming an illuminant epitaxial structure on the temporary substrate; forming a first transparent conductive layer on the illuminant epitaxial structure; forming a metal substrate on the first transparent conductive layer; forming an adhesion layer on the metal substrate; providing a supporting substrate, wherein the supporting substrate is connected to the metal substrate by the adhesion layer; removing the temporary substrate, so as to expose a surface of the illuminant epitaxial structure; forming a second transparent conductive layer on the exposed surface of the illuminant epitaxial structure; and forming an electrode on a portion of the second transparent conductive layer.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: August 7, 2007
    Assignee: South Epitaxy Corporation
    Inventors: Shih-Chang Shei, Yen-Wei Chen, Wei-Shou Chen, Chia-Sheng Chang, Hsin-Ming Lo, Chien-Fu Shen
  • Patent number: 7253014
    Abstract: A nanoparticle coated with a semiconducting material and a method for making the same. In one embodiment, the method comprises making a semiconductor coated nanoparticle comprising a layer of at least one semiconducting material covering at least a portion of at least one surface of a nanoparticle, comprising: (A) dispersing the nanoparticle under suitable conditions to provide a dispersed nanoparticle; and (B) depositing at least one semiconducting material under suitable conditions onto at least one surface of the dispersed nanoparticle to produce the semiconductor coated nanoparticle. In other embodiments, the nanoparticle comprises a fullerene. Further embodiments include the semiconducting material comprising CdS or CdSe.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: August 7, 2007
    Assignees: William Marsh Rice University, Newcyte, Inc.
    Inventors: Andrew R. Barron, Dennis J. Flood, John Ryan Loscutova
  • Patent number: 7253015
    Abstract: A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Velox Semiconductor Corporation
    Inventors: Milan Pophristic, Michael Murphy, Richard A. Stall, Bryan S. Shelton, Linlin Liu, Alex D. Ceruzzi
  • Patent number: 7253016
    Abstract: A micromechanical capacitive converter and a method for manufacturing a micromechanical converter comprise a movable membrane and an electrically conductive face element in a carrier layer. The electrically conductive face element is arranged opposite the membrane above a cavity. The electrically conductive face element and the carrier layer are perforated by perforation openings. The opening width of the perforation openings corresponds approximately to the thickness of the carrier layer.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies AG
    Inventors: Stefan Barzen, Alfons Dehe, Marc Füldner
  • Patent number: 7253017
    Abstract: Charge splitting networks for optoelectronic devices may be fabricated using a nanostructured porous film, e.g., of SiO2, as a template. The porous film may be fabricated using surfactant temptation techniques. Any of a variety of semiconducting materials including semiconducting metals and metal oxides (such as TiO2, CdSe, CdS, CdTe, or CuO) may be deposited into the pores of the porous template film. After deposition, the template film may be removed by controlled exposure to acid or base without disrupting the semiconducting material leaving behind a nanoscale network grid. Spaces in the network grid can then be filled with complementary semiconducting material, e.g., a semiconducting polymer or dye to create a exciton-splitting and charge transporting network with superior optoelectronic properties for an optoelectronic devices, particularly photovoltaic devices.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: August 7, 2007
    Assignee: Nanosolar, Inc.
    Inventors: Martin R. Roscheisen, Brian M. Sager, Jacqueline Fidanza, Klaus Petritsch, Gregory A. Miller, Dong Yu
  • Patent number: 7253018
    Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 7, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Su Kim
  • Patent number: 7253019
    Abstract: A semiconductor detector of electromagnetic radiation which utilizes a dual-purpose electrode which extends significantly beyond the edge of a photodiode. This configuration reduces the sensitivity of device performance on small misalignments between manufacturing steps while reducing dark currents, kTC noise, and “ghost” images. The collection-mode potential of the dual-purpose electrode can be adjusted to achieve charge confinement and enhanced collection efficiency, reducing or eliminating the need for an additional pinning layer. Finally, the present invention enhances the fill factor of the photodiode by shielding the photon-created charge carriers formed in the substrate from the potential wells of the surrounding circuitry.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: August 7, 2007
    Assignee: Cypress Semiconductor Corporation (Belgium) BVBA
    Inventor: Bart Dierickx
  • Patent number: 7253020
    Abstract: A method of alloying an image sensor is disclosed. The method comprises forming various semiconductor devices in a semiconductor substrate. Then, an insulator layer is formed over the semiconductor devices. Finally, deuterium gas is used to alloy said image sensor after the insulator oxide layer has been formed and prior to formation of contact holes in the insulator oxide layer.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: August 7, 2007
    Assignee: Omnivision Technologies, Inc
    Inventor: Howard E. Rhodes
  • Patent number: 7253021
    Abstract: A method of transfer molding, wherein a top-half mold and a bottom-half mold of an apparatus form a plurality of cavities interconnected, and wherein a pressure adjuster reduces the pressure of the cavities every time a specified amount of resin is supplied into any one of a plurality of cavities.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: August 7, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroyuki Nishi, Akira Sugai
  • Patent number: 7253022
    Abstract: A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package also includes an array of external contacts formed as multi layered metal bumps that include a base layer, a bump layer, and a non-oxidizing outer layer. The external contacts are smaller and more uniform than conventional solder balls, and can be fabricated using low temperature deposition processes, such that package warpage is decreased. Further, the external contacts can be shaped by etching to have generally planar tip portions that facilitate bonding to electrodes of a supporting substrate. Die contacts on the substrate can also be formed as multi layered metal bumps having generally planar tip portions, such that the die can be flip chip mounted to the substrate.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Victor Tan Cher 'Khng, Lee Kian Chai
  • Patent number: 7253023
    Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 7, 2007
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Kusagaya, Yasuhiro Yoneda, Daisuke Mizutani, Kazuhiko Iijima, Yuji Suwa
  • Patent number: 7253024
    Abstract: The present invention provides a method for manufacturing IC card by laminating a plurality of foils. The method of the present invention includes steps of putting a COB, a contact electrode of the COB facing downward; laying at least 2 foils having a hole, wherein said COB is inserted in said respective holes of the foils; laying a foil not having a hole on the foils having a hole; and compressing all of the foils.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: August 7, 2007
    Assignee: JT Corp.
    Inventors: Hong Jun Yu, Jung Ho Kim
  • Patent number: 7253025
    Abstract: A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate adhesive material. For example, each microelectronic substrate can include a first surface, a second surface opposite the first surface, and a functional microelectronic feature coupled to a connection terminal of the microelectronic substrate. The connection terminals can be coupled to a support member, such as a leadframe or a printed circuit board, with the bond plane between the microelectronic substrates either aligned with or transverse to the support member. The microelectronic substrates can be enclosed in a protective packaging material that can include a transparent window to allow selected radiation to strike one or the other of the microelectronic substrates.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, J. Michael Brooks
  • Patent number: 7253026
    Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Ho Ahn, Se-Yong Oh
  • Patent number: 7253027
    Abstract: A method of manufacturing a hybrid integrated circuit device includes the steps of forming a plurality of units each including a conductive pattern on a surface of a board made of metal, forming grooves along boundaries of the respective units of the board, electrically connecting circuit elements to the conductive patterns in the respective units, separating the respective circuit boards by dividing the board along the grooves, and flattening side surfaces of the circuit boards by pressing the side surfaces.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 7, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masaru Kanakubo
  • Patent number: 7253028
    Abstract: A method for packaging an image sensor includes the steps of providing a substrate, forming a first adhesive on one surface of the substrate, attaching a transparent material on the first adhesive, cutting or carving the surface of the transparent material to a depth penetrating the transparent material while not penetrating the first adhesive, cleaning the cut or carved surface of the transparent material, depositing a frame glue on the transparent material, and combining the transparent material with a microchip that includes a plurality of micro-lenses. The micro-lens is packaged within the transparent material. The microchip is then ground to perform a lithography process. Next, the substrate and part of the first adhesive are detached after the lithography process. After performing a cutting or carving procedure, the packaging process of the image sensors is completed.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 7, 2007
    Assignee: Youngtek Electronics Corp.
    Inventor: Hua-Hsiang Liu
  • Patent number: 7253029
    Abstract: A process for preparing an electronic package comprising: (a) providing a ceramic housing defining an internal cavity for receiving a micro device and having one or more interface portions; (b) treating the housing to form a tungsten layer on the interface portions; and (c) overlaying a palladium layer on the tungsten layer.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: August 7, 2007
    Assignee: M/A-Com, Inc.
    Inventors: Carl Geisler, Dennis O'Keefe
  • Patent number: 7253030
    Abstract: The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 7, 2007
    Assignee: Dongbu Electronics Co., Ltd
    Inventor: Kwang Young Ko
  • Patent number: 7253031
    Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: August 7, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
  • Patent number: 7253032
    Abstract: First laser light is irradiated (energy density of 400 to 500 mj/cm2) to a semiconductor film 102 in an atmosphere containing oxygen in order to obtain a semiconductor film 102b having large depressions and projections on the surface. Then, an oxidized film 105a formed by the irradiation of the first laser light is removed. After that, an inert gas with an oxygen density of 10 ppm or below is blown thereto, and, at the same time, second laser light is irradiated thereto (the energy density is higher than that of the irradiation of the first laser light). Thus, the surface of the semiconductor film 102b is flattened, and a semiconductor film 102c having fewer depressions and projections on the surface can be obtained.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: August 7, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Patent number: 7253033
    Abstract: In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10) is implanted not uniformly along the length direction of a gate (2) in the complete depletion type silicon on insulation (SOI) transistor. In other words, high concentration regions (11) where impurity concentrations are higher than that at a central portion in the end parts of the channel formation portion (10) on the side of a source (4) and a drain (5).
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: August 7, 2007
    Assignee: Sony Corporation
    Inventor: Hiroshi Komatsu
  • Patent number: 7253034
    Abstract: This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Joel P. de Souza, Alexander Reznicek, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 7253035
    Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer; forming a semiconductor layer; forming a lower data line; forming an upper data line including a source electrode and a drain electrode, the upper data line including a portion disposed on the semiconductor layer without interposing the lower data line; forming a passivation layer having a first contact hole exposing the drain electrode at least in part; and forming a pixel electrode on the first contact hole to contact the drain electrode.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Ki Kwak
  • Patent number: 7253036
    Abstract: A method of forming a gate insulation film of a crystallized thin film transistor, is provided, which can enhance an interfacial feature which exists between a gate oxide film and a silicon thin film substrate and which is fatal to performance of the thin film transistor, in the case that crystallization of amorphous silicon is performed by metal induced lateral crystallization (MILC). The gate insulation film formation method includes the steps of: forming an amorphous silicon film on an insulation substrate, and then patterning the amorphous silicon film, to thereby form a semiconductor layer; processing the semiconductor layer made of the amorphous silicon film by an oxygen plasma method, and oxidizing the silicon surface, to thereby form a first silicon oxide film; and mixing gas with silicon and depositing a second silicon oxide film on the first silicon oxide film by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 7, 2007
    Inventor: Woon Suh Paik
  • Patent number: 7253037
    Abstract: A method of fabricating a thin film transistor is provided. The method comprises first preparing a substrate and forming an amorphous silicon layer on the substrate. A catalyst construction is then positioned on the amorphous silicon layer and an anode and a cathode are then connected to the catalyst construction. A predetermined amount of electric power is then delivered to the anode and the cathode, generating joule heat which then crystallizes the portion of the amorphous silicon layer on which the catalyst construction is positioned, thereby forming a polysilicon layer. The remaining portion of the amorphous silicon layer is then crystallized to a polysilicon layer by propagating the crystallization of the portions of the polysilicon layer on which the catalyst construction is positioned.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: August 7, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventor: In-Young Jung
  • Patent number: 7253038
    Abstract: It is a problem to realize, by a reduced number of processes than that of the conventional, a reliable active-matrix liquid crystal display device having a high opening ratio for high-definition display. The present invention is characterized by: forming a gate electrode and source and drain interconnections in the same process, forming a first insulating film covering the interconnections, forming an upper light-shielding film on the first insulating film, forming a second insulating film on the upper light-shielding film, partially etching the first and second insulating films to form a contact hole reaching the drain interconnection, and forming a pixel electrode on the second insulating film to connect to the drain interconnection. Meanwhile, a holding capacitance is formed by the upper light-shielding film, the second insulating film and the pixel electrode.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: August 7, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Yoshifumi Tanada, Hiroshi Shibata
  • Patent number: 7253039
    Abstract: In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: August 7, 2007
    Assignee: Dongbu Elecotronics Co., Ltd.
    Inventor: Hak-Dong Kim
  • Patent number: 7253040
    Abstract: An insulating substrate is bonded to a monocrystalline Si substrate that includes a monocrystalline Si thin film transistor and a hydrogen ion implanted portion. After depositing an amorphous Si thin film, the amorphous Si thin film is modified into a polycrystalline Si thin film by irradiation of the excimer laser. In laser irradiation, the irradiation of the laser beam on the monocrystalline Si thin film transistor is blocked either by inserting a mask in part of the optical path of the laser beam, or by irradiating the laser beam before unnecessary portions of the monocrystalline Si substrate is detached. In this way, the irradiation of the laser beam for forming the polycrystalline Si thin film will not damage the monocrystalline Si thin film transistor in a semiconductor device in which the monocrystalline Si thin film transistor, which has been transferred, and the polycrystalline Si thin film transistor, which has been formed on the insulating substrate, are formed on the insulating substrate.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: August 7, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Itoga, Yutaka Takafuji, Yoshihiro Yamamoto
  • Patent number: 7253041
    Abstract: A method of forming a thin film transistor comprising a deposition procedure of a microcrystal material layer and performing a plasma treatment procedure. The deposition procedure and the plasma treatment procedure are repeated. A buffer layer is thus formed on the gate electrode.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: August 7, 2007
    Assignee: AU Optronics Corp.
    Inventors: Feng-Yuan Gan, Han-Tu Lin
  • Patent number: 7253042
    Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: August 7, 2007
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 7253043
    Abstract: The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In particular, one more types of dopant materials are implanted in a channel region, an extension region and/or source/drain regions to mitigate the establishment of a conduction path and the accumulation of electrons in the channel region that can result in an unwanted leakage current.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jean-Pierre Colinge, Weize Xiong
  • Patent number: 7253044
    Abstract: With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: August 7, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shigeharu Monoe, Takashi Yokoshima, Shinya Sasagawa
  • Patent number: 7253045
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semiconductor device is also disclosed.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Derick J. Wristers, David Wu, Hormuzdiar E. Nariman
  • Patent number: 7253046
    Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 7, 2007
    Assignee: Spansion LLC.
    Inventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
  • Patent number: 7253047
    Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 7253048
    Abstract: A semiconductor integrated circuit has a CMOS transistor formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Thermal oxidation is conducted to form a LOCOS for element separation between transistors in the semiconductor film. A gate oxide film of a second conductivity type transistor is formed over the insulating film. A first conductivity type impurity region is formed between the gate oxide film and the embedded insulating film in a region where the second conductivity type transistor is to be formed. A first conductivity type impurity region having a higher density than that of the first conductivity type impurity region is formed in a middle depth portion of the semiconductor film serving as the proximal region to a drain in the first conductivity type impurity region.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 7, 2007
    Assignee: Seiko Instruments Inc.
    Inventors: Miwa Wake, Yoshifumi Yoshida
  • Patent number: 7253049
    Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Shaofeng Yu, Haowen Bu, Lindsey H. Hall, Mark R. Visokay
  • Patent number: 7253050
    Abstract: Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first gate material comprising a first metal is formed over the high k gate dielectric material. The first gate material in the second region is implanted with a material different than the first metal to form a second gate material comprising a second metal. The work function of the CMOS device is set by the material selection of the gate materials.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 7, 2007
    Assignee: Infineon Technologies AG
    Inventors: Hongfa Luan, Hong-Jyh Li
  • Patent number: 7253051
    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
  • Patent number: 7253052
    Abstract: Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Pierre C. Fazan, Viju K. Mathews
  • Patent number: 7253053
    Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 ? (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Denise M. Eppich, Ronald A. Weimer
  • Patent number: 7253054
    Abstract: A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdown during a programming operation by maintaining a breakdown voltage above a programming voltage. The breakdown voltage is, at least partially, increased by forming a p-doped region (140) within a semiconductor substrate (102), and forming a drain region (166) of the OTP EPROM (100) within the p-doped region (140).
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jozef Czeslaw Mitros, David Tatman
  • Patent number: 7253055
    Abstract: An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: August 7, 2007
    Assignee: SanDisk Corporation
    Inventors: Nima Mokhlesi, Jeffrey W. Lutze
  • Patent number: 7253056
    Abstract: An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: August 7, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Jum Soo Kim, Ji Hyung Yune
  • Patent number: 7253057
    Abstract: A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an associated select gate and with a reduced gate width compared to typical devices. The tunnel window is recessed within an upper surface of a substrate. The tunnel window recess is made possible by selective etching of the substrate and oxides covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: August 7, 2007
    Assignee: Atmel Corporation
    Inventor: Bohumil Lojek
  • Patent number: 7253058
    Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Khe Yoo, Weon-ho Park, Byoung-ho Kim
  • Patent number: 7253059
    Abstract: A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At least one of the first and second output HVFETs is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 7, 2007
    Assignee: Power Integrations, Inc.
    Inventor: Balu Balakrishnan