Abstract: An automatic homing apparatus of a rotatable module applied to a foldable device. The foldable device includes a first casing and a second casing. The automatic homing apparatus includes a fastener, a pivot, and a transmission mechanism. The fastener is for fastening the first casing and the second casing. The pivot is for pivotally connecting the rotatable module to the first casing. The transmission mechanism is disposed at one end of the pivot. When the first casing is fastened to the second casing, the transmission mechanism is actuated by the fastener so that the pivot drives the rotatable module to turn for homing.

Abstract: An information processing apparatus includes a housing with a top surface and a rear surface, a CPU (central processing unit) provided in the housing, a keyboard placed on the top surface of the housing and including a plurality of keys which input key data to the CPU, a display unit attached to the housing rotatably between a closed position in which the display unit covers the keyboard and an open position in which the keyboard is exposed, and at least one switch provided on the rear surface of the housing and configured to input key data to the CPU.

Abstract: The removable hard disk housing assembly includes a housing substrate, a hard disk supporting frame, a rotatable handle, a supporting piece, two plates-liked elements and two springs. The hard disk supporting frame is connected with the housing substrate to support a hard disk. The rotatable handle is positioned at the front side of the housing substrate. The supporting piece is rotatably positioned at the housing substrate. The plates-liked elements are movably positioned within the housing substrate and are pulled by supporting piece and protrude and retract in respond to movement of the supporting piece. Two springs are positioned between the plate-liked elements and the housing substrate and are used to bias the plate-liked elements. It prevents the hard disk from falling off when the assembly is subjected to external forces. The assembly is fixed by two extension portions so that force used to fix the assembly is well distributed.

Abstract: In a method and system for detachably docking a portable device to a docking device, the docking device is placed on a stable surface. The docking device includes a pair of moveable rear latches and moveable front latches, which are operable to latch on to corresponding matching slots of the portable device when docked. The portable device is aligned vertically on top of the docking device. A vertical force is applied on the portable device. When properly aligned a pair of alignment pins included in the docking device mate with corresponding notches on the portable device when the two devices are docked. A release latch on the docking device is operable to undock the two devices.

Abstract: The present invention features a non-peripherals-based processing control unit having an encasement module that is very small and durable compared to conventional computer encasement structures. The process control unit is capable of being incorporated into various devices and/or environments, of accepting applied and impact loads, of functioning as a load bearing structure, as well as being able to be processed coupled together with one or more processing control units to provide scaled processing power. The processing control unit of the present invention further features a unique method of cooling using natural convection, as well as utilizing known cooling means, such as liquid or thermoelectric cooling.

Abstract: A computer system may include one or more modules coupled to a backplane in a housing. A module support structure may allow cooling air to flow upwardly across the modules. In one embodiment, a power section of the module may be located downstream of a data section of the module. In another embodiment, offset brackets may hold a circuit board of a module at an offset relative to a pair of guides in a module support structure. In another embodiment, a heat sink may be coupled between heat producing components on a pair of adjacent modules. In another embodiment, a converter apparatus may support a plurality of modules in a different number of slots in a system. In another embodiment, a heat sink on a module may include a pair of heat pipes arranged such that the heat pipes diverge from one another toward the condenser ends of the heat pipes.

Abstract: An adjustable heat sink shroud includes an insert that may be included within the interior of the heat sink shroud depending on the size of the heat sink enclosed within the shroud. The presence of the insert directs the flow of air through the heat sink.

Abstract: An opening is formed in a case. Air is caused to flow through the interior of the case. A panel closes the opening. A printed circuit board is disposed behind the panel within the case. A plurality of components, including a control device which can be operated on the front surface of the panel and a display device providing a display viewable on the front surface of the panel, are mounted on the printed circuit board. The printed circuit board is enclosed in a closed receptacle disposed within the case.

Abstract: An electronics module comprises a housing; and a plurality of electronic and electrical components for example fans. The module includes electromagnetic shielding for example perforated panels side walls etc. that is associated with the housing and/or the electronic components, and which provides a Faraday cage for the electronic components. The shielding is constructed so that one or more of the components can be removed from the module while the module is in operation substantially without affecting the integrity of the Faraday cage. The module enables certain components thereof to be replaced without adding to the downtime of the system or increasing electromagnetic interference.

Abstract: A wireless router dissipates heat through use of a unique heat sink having tines to increase the heat sink surface area. A housing includes lower vents and an upper vents to enable passage of an airflow. The airflow may be generated by one or more fans disposed within the housing interior. The heat sink is disposed in proximity to the upper vents and above a transceiver and an amplifier to thereby receive and dissipate heat. The wireless router is able to effectively dissipate heat generated by the transceiver and amplifier which allows for increased power output.

Abstract: A heat dissipating device (8) for cooling a number of electronic devices. The heat dissipating device includes a heat sink (7), a fan (6) mounted to a side of the heat sink and a fan duct (5). The heat sink includes a heat spreader (70), a cover (74) and fins (72) disposed between the heat spreader and the cover. The fan duct includes a mounting plate (50), a faceplate (52) extending downwardly from and perpendicular to the mounting plate, and baffle walls (506, 508) extending downwardly from the mounting plate. The mounting plate defines locating holes (540) for permitting screws (82) to pass through the locating holes and to engage with threaded holes (740) defined in the cover. An airflow generated by the fan flows through the fins and an outlet (524) defined between the baffle walls and the heat sink.

Abstract: A heat-dissipating structure is assembled on a Central Processing Unit, and has a water-cooling device, a fan and a support device. The support device is assembled between the water-cooling device and the fan to form an accommodating space. Hence, the heat-dissipating device can efficiently dissipate the heat from the Central Processing Unit and another electronic element that is disposed in the vicinity of the Central Processing Unit. Furthermore, the air-guiding device can guide the air from the fan to the correct place for cooling the Central Processing Unit or another electronic element.

Abstract: A heat collector includes a heat sink. A recess in the heat sink either forms or receives internal gas and liquid phase lines. A manifold may be integrally formed in the heat sink or may be added on. The manifold combines separate input and output connections into a composite input and output connection. An internal composite line may include the internal gas and liquid phase lines and may be connected to the composite connection of the manifold. The internal liquid phase line is fluidly connected to the internal gas phase line in a transition region of the composite line. Advantageously, the internal liquid phase line may be disposed inside the internal gas phase line for protection and positive heat transfer effects. A cover may hold the composite line in the recess and provide good thermal contact between the lines and the heat sink.

Abstract: A two-phase cooling system operated at atmospheric pressure. A reservoir containing cooling fluid has a stack that is vented to the atmosphere. The stack is shaped to allow condensation of substantially all of the cooling fluid in vapor form entering the stack. Condensation may be enhanced by cooling the stack, such as with flowing air along the outer walls of the stack or placing a thermoelectric device in contact with the stack. The system provides high thermal capacity but is easy to use and service.

Abstract: A method and an assembly of the invention are intended for connecting two parts via a spacer made from a heat-shrinkable material shrinkable only in one direction. The spacer is sandwiched between the parts and attached to both parts with such orientation that direction of the shrinkage of the spacer coincides with the direction of movement of both parts towards each other. After the parts and the spacer are interconnected, the spacer is heated for causing said parts to move closer to each other. The space between the parts can be filled with an adhesive material so that the parts will be held together without the use of clamps or binding bands while the adhesive is cured. Another application is to attach a heatsink to an electronic device supported by a PC board. Shrinkage of the spacer under effect of heating brings the electronic device into a tight heat-transferring contact with the heatsink and maintains this contact irreversibly.

Abstract: There is disclosed a heat radiation device for memory modules intended for radiating heat that is generated from a memory module group wherein a plurality of memory modules equipped with memory elements on both the front and rear face sides of a substrate are placed in parallel. The device comprises heat radiation plates in pairs composed of front face side heat radiation plates in contact with memory elements that are installed on the front face side of the substrate for each of the memory modules, and of rear face side heat radiation plates in contact with memory elements that are installed on the rear face side of the substrate; and connecting members for heat radiation plates in pairs which connect the heat radiation plates in pairs so that heat is conducted among a plurality of the heat radiation plates in pairs.

Abstract: An elastic seal member is formed at the surface of a metal plate included in a gasket, which faces toward a lid, and another elastic seal member is formed at the surface of the metal plate facing toward a side wall. At the metal plate, the seal member is disposed further inward relative to the other seal member fitted in a seal groove. As bolts are tightened, the seal members become compressed and deformed, causing the seal member to press the metal plate against an exposed portion of an inner wall portion and the other seal member to press the metal plate against the lid.

Abstract: A system for delivering power to an integrated circuit (IC) component mounted on a circuit board includes a circuit board having a first side and an opposite second side. An IC component is mounted on the first side of the circuit board, and the IC component has a plurality of power contacts. A voltage regulator module (VRM) is coupled to the second side of the circuit board. The VRM reduces a voltage supplied to the IC component from a first voltage to a second voltage. An interface connector is mounted on the VRM. The interface connector is in mating engagement with the IC component, thereby delivering power at the second voltage directly to the IC component.

Abstract: A portable device includes a first casing which houses a circuit board having a first conductive layer, a second casing which houses a circuit board having a second conductive layer, and a coupling part which openably and closably couples the first casing and the second casing. The coupling part is made of a metal material, and the first conductive layer is electrically connected to the second conductive layer via the coupling part.

Abstract: An assembling electronic device includes a plurality of functional modules, a characterized casing having a plurality of receiving cavities, and a terminal circuit. Each of said functional modules is shaped and sized to detachably receive in the respective receiving cavity so as to securely retain the functional module in the characterized casing in position. The terminal circuit is provided at the characterized casing to electrically connect with the terminals of the functional modules when the functional modules are detachably received in the receiving cavities respectively so as to form a complete circuit for the functional modules, such that each of the functional modules is replaceably mounted in the characterized casing for enhancing a user-personalizability.

Abstract: In an active semiconductor backplane for a liquid crystal spatial light modulator, spacers (25) which are distributed over the backplane extend above an array of electrical and/or electronic elements and comprise at least two layers essentially of the same material and occuring in the same order as is found in at least one of the electrical or electronic elements, such as an NMOS transistor (52). The latter is formed from a stack of layers on a silicon substrate (51) comprising polysilicon (56), continuous silicon oxide (57) modified to include gate oxide GOX (55), metallic gate electrode (59), continuous silicon oxide (58) and a metallic drain electrode (60) which is coupled to a spaced mirror electrode over the layer (58). Likewise, spacer (25) comprises the layers (57 and 58) with metallic (67, 68) deposited simultaneously with electrodes (59, 60). The foot of layer (57) is differently modified to include field oxide layer (69) and polysilicon layers thin oxide (71).

Abstract: A start-up apparatus for a power supply is presented. A charging path from an input voltage to a holding capacitor is cut off after the power converter starts up. The start-up apparatus includes a transistor having a drain supplied with the input voltage, and a source connected to the holding capacitor and an input of a start-up control unit. An output of the start-up control unit controls a switch and the transistor. The holding capacitor starts to be charged as the transistor is turned on. Once a voltage across the holding capacitor exceeds a start-up voltage, an internal control circuit is powered via the switch. Meanwhile, the transistor is turned off and the charging path is cut off. Furthermore, the start-up apparatus provides a hysteresis threshold voltage range for controlling the power converter.

Abstract: The invention regards an improved voltage converter with increased current capability. The voltage converter architecture may be configured by software. In the prior art programmable charge pumps have been configured in such a way, that the unused stages were simply short circuited by a decoding logic. According to the invention these stages are used to increase the current capability of the first pumping stage. In particular the result is an increase in current capability of a proposed charge pump device by 10% to 15% without the need of additional parts and within the same area.

Abstract: A power supply circuit comprises a bridge circuit that has four rectifier elements connected and produces a rectified voltage between a positive side output terminal and a negative side output terminal of the power supply circuit, two of the four rectifier elements being connected to the negative side output terminal, a current detection element with which to detect a current, a first switching element that is connected in series to the current detection element and together with the current detection element is connected in parallel with one of the two rectifier elements, and a second switching element that is connected in series to the current detection element and together with the current detection element is connected in parallel with the other of the two rectifier elements. Based on a result of detecting with the current detection element, switching timings of the first and second switching elements are controlled.

Abstract: A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.

Abstract: A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties when the storage element is unprogrammed, a first activation circuit which activates the selection switch, a second activation circuit which activates the protection element in complement with the first activation circuit in normal mode, and a test circuit which conducts a test on the storage element while the second activation circuit is activating the protection element together with the first activation circuit in test mode.

Abstract: The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit. The embodiments of the prevent invention provide a method and a memory circuit for holding adjacently arranged bit lines at writing voltages during a writing operation of a selected memory cell to reduce voltage crosstalk.

Abstract: The invention relates to a PMC memory circuit comprising a PMC memory cell having a PMC component, the PMC component having a solid electrolyte with permanently introduced defects, so that the PMC component has a hysteresis with regard to its I-V characteristic curve with an upper and a lower current value branch, and a data retention unit, which, for storing a state to be stored, applies to the PMC component a center voltage or storage voltage at which the PMC component is operated, either in the upper current value branch of the hysteresis for the purpose of storing a first state or in the lower current value branch of said hysteresis for the purpose of storing a second state.

Abstract: The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a plurality of bit lines connected to drain diffusion regions of the transistors, one of the bit lines being connected to the sense amplifier. The first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion region to extract the excessive majority carriers from within the semiconductor layer to the drain diffusion region.

Abstract: Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and intersect with a number of signal wires. Signals are stored in the nanowire-crossbar latch array, and output from the nanowire-crossbar latch array, by applying an input signal to each signal wire and applying selected voltages and voltage pulses to the control lines. In alternate embodiments, a second enable line that crosses and interconnects with each signal wire is added to the nanowire-crossbar latch array.

Abstract: An SRAM device includes a memory cell. The memory cell includes a first cross-coupled inverter and a second cross-coupled inverter, which is electrically connected to the first cross-coupled inverter. Each inverter includes a pull down device and a pull up device. The pull up device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pull down device is preferably within a range of about 1.5 to about 0.8. A channel area ratio of the pull up device to the pull down device is preferably within a range of about 3 to about 1. A pass gate device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pass gate device is preferably within a range of about 3.0 to about 1.2.

Abstract: An invention is provided for a low write current MRAM. Each MRAM cell includes a word line and a bit line. A magnetic device is disposed at the intersection of the word line and the bit line. Disposed at either end of the magnetic device is a writing magnet. The pair of writing magnets switches a magnetic alignment of the magnetic device during a write operation. In aspect, the pair of writing magnets and the magnetic device can be aligned along a long axis of the memory cell, which generally is not aligned with either the word line or the bit line.

Abstract: An MRAM cell comprises a magnetic metal layer and a magnetic sensing device in close proximity to the magnetic metal layer. One end of the magnetic metal layer is coupled with a word line transistor and a diode is included and configured to couple the magnetic sensing device to a bit line. The magnetic metal layer can be used to both program and read the cell, eliminating the need for a second current line in the cell.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory celf columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: A ferromagnetic memory cell is disclosed having a base (21), oriented in a horizontal plane, a bit (19), made of a ferromagnetic material, and a sense/write line (20), positioned proximate the bit (19) sufficient to detect the directed polarity of the bit when a first current is applied thereto, and to direct the polarity of the bit when a second larger current is applied thereto in a given direction. The bit (19) has a height that is oriented perpendicular to the horizontal plane of the base, and a polarity that can be directed along the height.

Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.

Abstract: The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.

Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Abstract: A NAND-type flash memory device has a multi-plane structure. Page buffers are divided into even page buffers and odd page buffers and are driven at the same time. Cells connected to even bit lines within one page and cell connected to odd bit lines within one page are programmed, read and copyback programmed at the same time.

Abstract: A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.

Abstract: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use fo a higher word line voltage, but help prevent an over soft programming effect.

Abstract: The invention relates to a method of operating a storage component 10, 30, 40. In order to enable a verification of the integrity of the data in the storage component, it is proposed that first a write operation for storing data in a data storage area 11, 31, 41 of the storage component 10, 30, 40 is performed. Then, a completion status field 15, 35, 45 in the storage component 10, 30, 40 is updated, in case the write operation has been completed successfully. The updated completion status field 15, 35, 45 indicates that the write operation has been completed successfully. The invention relates equally to a corresponding storage component and to a corresponding system.

Abstract: The invention relates to a circuit arrangement for switching high-voltage signals with low-voltage signals, particularly for driving a semiconductor memory arrangement, comprising a low-voltage logic device for generating a low-voltage signal with a first predetermined logic level and with a second predetermined logic level, comprising a latch for receiving and latching the low-voltage signal and for outputting an output signal with a voltage dependent on the logic level of the received low-voltage signal, comprising a level shifter for increasing the value of the voltage of the latched low-voltage signal to a voltage of a high-voltage signal, as a result of which the voltage of the output signal output essentially rises to the voltage of the high-voltage signal, the latch exhibiting one or more high-voltage transistors.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract: There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Abstract: The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern into the storage device, reading the data according to a read phase of a plurality of read phases, comparing the predetermined pattern with the data, and selecting a read phase from the plurality of read phases according to the comparing result.