Abstract: The invention provides a method of diagnosing a lubricated portion which can precisely measure a metal concentration in a lubricating oil and can diagnose accurately a state of the lubricated portion on the basis of a value of measurement. In accordance with the present diagnosing method, a lubricating oil picked up from the lubricated portion is diluted by an organic solvent so as to prepare a sample oil, the sample oil is filtrated by a filter so as to separate a large-diameter metal particle having a particle diameter larger than 0.5 ?m, a metal concentration of a solution formed by dissolving the large-diameter metal particle by an acid and a metal concentration of a filtrate including a small-diameter metal particle having a particle diameter equal to or smaller than 0.

Abstract: A medical diagnostic method and instrumentation system for analyzing noncovalently bonded agglomerated biological particles is described. The method and system comprises: a method of preparation for the biological particles; an electrospray generator; an alpha particle radiation source; a differential mobility analyzer; a particle counter; and data acquisition and analysis means. The medical device is useful for the assessment of human diseases, such as cardiac disease risk and hyperlipidemia, by rapid quantitative analysis of lipoprotein fraction densities. Initially, purification procedures are described to reduce an initial blood sample to an analytical input to the instrument. The measured sizes from the analytical sample are correlated with densities, resulting in a spectrum of lipoprotein densities. The lipoprotein density distribution can then be used to characterize cardiac and other lipid-related health risks.

Abstract: Multiwell plate applications are describe for use with a plurality of fibres having an extraction phase coated thereon in combination with a positioning device. The device and method described are able to perform adsorption of components of interest from a biological system in high volume.

Abstract: Fluid introduction is facilitated through the use of a port which extends entirely through a microfluidic substrate. Capillary forces can be used to retain the fluid within the port, and a series of samples or other fluids may be introduced through a single port by sequentially blowing the fluid out through the substrate and replacing the removed fluid with an alternate fluid, or by displacing the fluid in part with additional fluid. In another aspect, microfluidic substrates have channels which varying in cross-sectional dimension so that capillary action spreads a fluid only within a limited portion of the channel network. In yet another aspect, the introduction ports may include a multiplicity of very small channels leading from the port to a fluid channel, so as to filter out particles or other contaminants which might otherwise block the channel at the junction between the channel and the introduction port.

Abstract: The present invention relates to a method for using a test card (1) comprising at least one fluid circuit, constituting a network of channels (3) and/or of compartments (17), for transferring at least one biological liquid from at least one inlet (2) to at least one outlet (6, 17), and a hydrophobic fluid is injected into the test card, into all or part of the network of said card, prior to the transfer of the biological liquid(s), said hydrophobic fluid filling the capillary spaces formed by the angles of the network of channels and/or of compartments of the card and avoiding the formation of bubbles and/or of dead volumes during the transfer of the biological liquid. The invention is of preferential use in the field of microfluidics applied to biology.

Abstract: A method is provided for producing motif-specific, context-independent antibodies which recognize a plurality of peptides or proteins within a genome that contain the same motif. The method includes the step of immunizing a host with a degenerate peptide library antigen featuring (i) a fixed target motif containing one or more invariant amino acids including at least one modified amino acid, and (ii) a plurality of degenerate amino adds flanking the motif. Motif-specific, context-independent antibodies produced by the disclosed method are also provided. The method encompasses motifs consisting of a single modified amino acid, as well as short motifs comprising multiple invariant amino acids including one or more modified amino acids, such as all or part of kinase consensus substrate motifs, protein-protein binding motifs, or other cell signaling motifs. Methods of using the antibodies, e.g. for genome-wide profiling, are also provided.

Abstract: A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the mask and the surface feature may then be removed and the remaining portions of the mask may be used to define a dimension of said phase change material. Another dimension of the phase change material may be defined using an upper electrode extending over said phase change material as a mask to etch the phase change material.

Abstract: A method of treating a substrate in manufacturing a magnetoresistive memory cell includes performing a cleaning operation on the substrate using a mask layer as a protection layer for etching of a peripheral via. Further, an etch stop layer can used as a protection layer in a cleaning operation on the substrate.

Abstract: A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in a plate-up method, and the ferromagnetic liner is selectively formed on the plated conductive lines. The ferromagnetic liner may also be formed over conductive lines and a top portion of vias in a peripheral region of the workpiece.

Abstract: There is provided a method and apparatus for processing an organosiloxane film, which allow an inter-level insulating film with a low dielectric constant to be formed at a low heat process temperature. A semiconductor (10) with a coating film formed thereon is loaded into a reaction tube (2) of a heat-processing apparatus (1). Then, the interior of the reaction tube (2) is stabilized at a predetermined pressure, and hydrogen is supplied into an inner tube (3) through an acidic gas feed line (13), to heat the coating film under an acidic atmosphere. Then, the interior of the reaction tube (2) is heated up to a predetermined temperature, while heating the coating film under an acidic atmosphere. Then, gas inside the reaction tube (2) is exhausted, and ammonia is supplied into the inner tube (3) through an alkaline gas feed line (14), to heat the coating film under an alkaline atmosphere.

Abstract: A method for processing semiconductor wafers, e.g., silicon. The method includes providing a monitor wafer, which is made of a crystalline material. The method includes introducing a plurality of particles within a depth of the material, whereupon the plurality of particles cause the crystalline material to be in an amorphous state. The method also includes introducing a plurality of dopant particles into a selected depth of the crystalline material in the amorphous state using an implantation tool. The amorphous state traps the dopant particles. The method includes subjecting the monitor wafer including the plurality of particles and dopant particles into thermal anneal process to activate the dopant. The sheet resistivity is measured. The method operates the implantation tool using one or more production wafers if the dose of the dopant particles in the monitor water is within a tolerance of a specification limit.

Abstract: A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and exposed on a surface of the semiconductor package. These exposed portions of the solder bumps form the test pads by which the finished package may be tested.

Abstract: A method for forming a protective structure of active matrix triode field emission device is provided. The method comprises the steps of forming a silicon active region; depositing a gate oxide layer over the silicon active region; depositing and patterning a first metal layer over the gate oxide layer; doping impurities into portions of the said silicon active region to form a source/drain in a first conductive type and simultaneously to form a diode having a terminal in the first conductive type; forming ILD layer over the first metal layer and forming a plurality of contact holes thereon; depositing and patterning a second metal layer; forming a passivation layer over the second metal layer and forming a plurality of via holes thereon, depositing and patterning a third metal layer to form a gate and a tip structure.

Abstract: A method of making a light active sheet. A bottom substrate having an electrically conductive surface is provided. A hotmelt adhesive sheet is provided. Light active semiconductor elements, such as LED die, are embedded in the hotmelt adhesive sheet. The LED die each have a top electrode and a bottom electrode. A top transparent substrate is provided having a transparent conductive layer. The hotmelt adhesive sheet with the embedded LED die is inserted between the electrically conductive surface and the transparent conductive layer to form a lamination. The lamination is run through a heated pressure roller system to melt the hotmelt adhesive sheet and electrically insulate and bind the top substrate to the bottom substrate.

Abstract: Photonic interconnect reconfigurably couples integrated circuits such as microprocessor, memory or other logic components. Detector, modulator, broad-band coupler and waveguide elements provide transmit and receive capability on CMOS substrate. Computer-implemented design software and reusable component library automate photonic and circuit design and simulation for manufacturability.

Abstract: A method for manufacturing an electronic device includes the steps of forming a first resist pattern on a primary surface of a SAW element, the first resist pattern having openings at positions corresponding to those at which bumps and a sealing frame are to be formed, sequentially forming metals over the first resist pattern, the metals being formed into adhesion layers, barrier metal layers, and solder layers, removing the first resist pattern on the SAW element such that the bumps and the sealing frame are simultaneously formed. When the bumps and the sealing frame of the SAW element are bonded to bond electrodes of the bond substrate, the solder layers are melted and alloyed by heating.

Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.

Abstract: The present invention discloses a self-alignment manufacturing method of a microlens and an aperture using in an optical device. The method manufactures the aperture and the circular opening in the opaque film on a transparent substrate, and utilizes the self-alignment backside exposure technology to precisely integrate the aperture and the microlens made by macromolecule material without any combination step. The claimed method is simpler than conventional technology and can precisely align and integrate the microlens and the aperture with a continuous batch manufacture. Since the aperture and the circular opening are concentric circles and formed in same step, the microlens and the aperture can be precisely aligned with the backside exposure. The claimed invention can effectively improve the optical resolution and efficiency of the optical access and measurement devices.

Abstract: Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line and the source/drain electrode are formed as composites of at least two different metal conductive layers. A transparent pixel electrode is formed that is electrically coupled to the drain electrode.

Abstract: Methods and apparatus are described for irradiating one or more substrate surfaces with accelerated gas clusters including strain-inducing atoms for blanket and/or localized introduction of such atoms into semiconductor substrates, with additional, optional introduction of dopant atoms and/or C. Processes for forming semiconductor films infused into and/or deposited onto the surfaces of semiconductor and/or dielectric substrates are also described. Such films may be doped and/or strained as well.

Abstract: A method of fabricating an X-ray detector array element. A gate and a gate insulation layer are formed on a substrate. A silicon island is formed on the insulation layer in a transistor area. A common line is formed on the insulation layer, simultaneously; source and drain are formed on the island to form a TFT. A bottom electrode is formed on the insulation layer in a capacitor area and covers the common line. A passivation layer is formed on the insulation layer, the bottom electrode and the TFT. A first via hole penetrates the passivation layer to expose the source. A planarization layer is formed on the passivation layer and fills the first via hole. Second and third via holes penetrate the planarization layer. The second via hole exposes the source. The third via hole exposes part of the passivation layer. A top electrode is formed on the planarization layer and connects the source.

Abstract: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Abstract: A memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active low conductive layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: For hermetic encapsulation of a component, which includes a chip with component structures applied on a substrate in a flip-chip construction, a material is applied onto the lower edge of the chip and regions of the substrate abutting the chip, and then a first continuous metal layer is applied on the back side of the chip and on the material, as well as on edge regions of the substrate abutting the material. For hermetic encapsulation, a second sealing metal layer is subsequently applied by a solvent-free process at least on those regions of the first metal layer that cover the material.

Abstract: A stacked image sensor package contains an image sensor chip and a peripheral chip. A support pad for the peripheral chip adheres to a top surface of the peripheral chip, eliminating the need for a support member that otherwise would contribute to the thickness of the package. Thermal dissipation is enhanced by exposing surfaces including a back surface of the peripheral chip.

Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.

Abstract: In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the die-pad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.

Abstract: A stagger type TFT substrate and a fabrication method therefor in which the number of exposure processes is reduced. A resist pattern is formed in an area on the TFT substrate where a drain bus-line (DB) is to be formed and an area on the TFT substrate where a TFT is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the DB and a channel area for the TFT. In addition, a resist pattern is formed in an area where a gate bus-line (GB) is to be formed and an area where a pixel electrode is to be formed by the use of a half tone mask. Etching is performed with this resist pattern as a mask to form the GB and the pixel electrode. The DB and the channel are formed by one half tone mask and the GB and the pixel electrode are formed by another half tone mask. As a result, the number of exposure processes necessary for fabricating a stagger type TFT substrate can be reduced.

Abstract: According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.

Abstract: A method for manufacturing an organic thin-film transistor with a plastic substrate, comprising steps of: providing a mold and a plastic substrate, said mold being provided with a relief printing structure; imprinting said plastic substrate by said mold so as to define source/drain electrode regions on said plastic substrate; forming a first electrode layer so as to form source/drain electrodes on said source/drain electrode regions on said plastic substrate; forming a plurality of semiconductor mesas, each of said semiconductor mesas covering a pair of said source/drain electrodes; forming an insulating layer; forming a second electrode layer, being separated from and on said semiconductor mesas by said insulating layer; and forming a passivation layer.

Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.

Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

Abstract: A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 ? per minute using the same etchant.

Abstract: The invention provides a method of forming a silicon tip by a single etching process, as well as a method of forming a tip floating gate to increase erase speed. Etching gases comprising (1) chlorine and/or (2) oxygen/helium are performed to form a silicon tip without bottom dimple. The invention may further control the tip angle by adjusting the etching parameters of gas compositions and ratios, chamber pressures, and radio frequency powers.

Abstract: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.

Abstract: Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.

Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, a second heat treatment is performed for releasing stress generated in the substrate in the first heat-treatment. Thereafter, an impurity is implanted into an area to become an implanted region of the substrate, using the gate electrodes as masks, and a third heat treatment is performed for activating the impurity implanted.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device capable of improving the film quality of a dielectric film. The method includes the steps of providing a semiconductor substrate having a storage node contact; forming a metal storage electrode on the substrate; forming a dielectric film using any one chosen from a group including a single film made of HfO2, a single film made of Al2O3, and a lamination film made of HfO2 and Al2O3 on the metal storage electrode; performing CF4 plasma treatment on the dielectric film; and forming a metal plate electrode on the dielectric film.

Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device, which can improve a leakage current characteristic in applying HfxAlyOz as a dielectric film. In such a method, HfxAlyOz thin films are deposited on a storage electrode to form an HfxAlyOz dielectric film and a plate electrode is formed on the dielectric film. The HfxAlyOz dielectric film consists of laminated HfxAlyOz thin films which are different in compositions of Hf and Al such that the lower HfxAlyOz thin film adjoining the storage electrode has a larger composition ratio of Al than that of Hf and the upper HfxAlyOz thin film has a larger composition ratio of Hf than that of Al, and the upper HfxAlyOz thin film is subjected to heat treatment under an oxygen atmosphere after its deposition.

Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Abstract: Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal alloy layer thereby increasing the surface roughness of the second surface of the metal alloy layer, forming a capacitor dielectric on the first electrode and forming a second electrode on the capacitor dielectric. By providing a metal alloy layer and etching the second surface of the metal alloy layer, an increased capacitance of the integrated capacitor is achieved.

Abstract: A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.

Abstract: Disclosed herein is a method for forming a gate electrode of a non-volatile memory device. In an etch process of a gate electrode for defining the gate electrode, the etch process is performed by selectively adding an addition gas containing carbon. This prevents undercuts from being formed on a sidewall of a control gate when a floating gate is etched. It is thus possible to form the gate electrode having a vertical profile.

Abstract: Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the semiconductor substrate is patterned to define areas for removal of one or more layers of material interposed between the semiconductor substrate and the first mask layer. Portions of the one or more layers of material exposed by the patterned first mask layer are removed to define elements of the integrated circuit device overlying the first portion of the semiconductor substrate.

Abstract: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

Abstract: One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.