Abstract: The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a control gate and a floating gate. In a gate formation process in which a thickness of a floating gate is over 1500 ?, problems in short process time and short mass production margin in an existing process can be solved while completely stripping a dielectric layer fence.

Abstract: Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device comprises a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval; a memory cell which is formed on the surface of the substrate to connect the source region and the drain region, and has a plurality of nano-sized quantum dots filled with material for storing electrons; and a control gate which is formed on the memory cell and controls the number of electrons stored in the memory cell. It is possible to embody a highly efficient and highly integrated memory device by providing a memory device having nano-sized quantum dots and a method for manufacturing the same.

Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

Abstract: Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in the semiconductor substrate. Thus, the gate insulation layer is formed before forming the buried impurity region, thereby substantially reducing impurity diffusion that can be caused by a thermal process for forming the gate insulation layer. In addition, the gate insulation layer is not exposed, thus protecting the gate insulation layer from being recessed.

Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.

Abstract: A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.

Abstract: A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor substrate; forming a dielectric layer on the surface of the semiconductor substrate including the isolation trench; filling the isolation trench with a CVD layer; removing the dielectric layer except a portion in the isolation trench by an etching; sequentially forming an insulating layer and a conductive layer; forming a resist defining a pattern which covers via the conductive layer a portion of the insulating layer in contact with the dielectric layer; and performing an anisotropic etching on the resist to thereby remove a portion of the conductive layer exposing a surface thereof.

Abstract: The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer.

Abstract: The manufacturing stability can be improved while effectively inhibiting the short-channel effect in the transistor according to the present invention. A halo impurity having a conductivity type opposite to a first conductivity type of a first impurity is ion-implanted into the silicon substrate 101, and thereafter the first impurity having the first conductivity type, is ion-implanted and then a flash lamp annealing is conducted to form a p-type halo region 113 and a n-type extension region 111. Then, the second impurity having the first conductivity type is ion-implanted into the silicon substrate 101, and then a flash lamp annealing is conducted to form a n-type source/drain region 109. Then, the impurity contained in the silicon substrate 101 is activated via spike RTA.

Abstract: A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas, and top electrode areas; etching to remove the exposed silicon (Si) surfaces; selectively forming metal sidewalls adjacent the hard mask; filling the memory areas with memory resistor material; removing the hard mask, exposing the underlying Si active device areas; forming an overlying layer of oxide; etching the oxide to form contact holes to the active device areas; forming diodes in the contact holes; and, forming bottom electrode lines overlying the diodes.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Abstract: Disclosed herein is a method for forming an isolation film of a semiconductor memory device. According to the disclosure, in a pre-treatment cleaning process performed before a tunnel oxide film is formed, a SC-1 cleaning process is performed at a temperature ranging from 60° C. to 70° C. Therefore, oxide films in a cell region and a peripheral region are recessed even in the SC-1 cleaning process as well as a DHF cleaning process. A DHF cleaning time can be thus reduced. Accordingly, the method can minimize loss of a silicon substrate by DHF and can thus control the depth of a moat.

Abstract: Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The invented method is distinguished by a combination of the following method steps: provision of a semiconductor planar substrate composed of a semiconductor material, reduction of the thickness of the semiconductor planar substrate inside at least one surface region of the semiconductor planar substrate in order to form a raised surface region in relation to the surface planar region of reduced thickness, structuring the raised surface region of the semiconductor planar substrate by means of local mechanical removal of material in order to place impressions inside the raised surface regions, joining the structured surface of the semiconductor planar substrate with the glasslike planar substrate in such a manner that the glasslike planar substrate at least partially covers the surface planar region of reduced thickness, tempering the joined planar substrates in such a manner that in a first tempering phase, which is conducted under vacuum conditions, the glasslike planar substrate covering the surface reg

Abstract: A process and system for processing a thin film sample (e.g., a semiconductor thin film), as well as the thin film structure are provided. In particular, a beam generator can be controlled to emit at least one beam pulse. With this beam pulse, at least one portion of the film sample is irradiated with sufficient intensity to fully melt such section of the sample throughout its thickness, and the beam pulse having a predetermined shape. This portion of the film sample is allowed to resolidify, and the re-solidified at least one portion is composed of a first area and a second area. Upon the re-solidification thereof, the first area includes large grains, and the second area has a region formed through nucleation. The first area surrounds the second area and has a grain structure which is different from a grain structure of the second area. The second area is configured to facilitate thereon an active region of an electronic device.

Abstract: The present invention is related to a method of manufacturing a semiconductor device. In particular, the method of the present invention is related to uniformly irradiating a semiconductor film with laser light. In order to achieve the present invention, a scanning speed of the laser light is changed depending on a position to be irradiated. Particularly, the scanning speed becomes higher as the position gets closer to a center of the substrate.

Abstract: The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

Abstract: This invention provides a process for growing Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaxial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaxial layer, such as Si0.1Ge0.9 in a thickness of 0.8 ?m on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si01.Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 ?m Si0.05Ge0.95 layer, and/or optionally a further 0.8 ?m Si0.02Ge0.98 layer, are grown.

Abstract: The present invention provides a method of forming a thin film containing a metal oxide as the main component, the film thickness of which is relatively uniform, at a high film deposition rate over a wide area and over a long time. The present invention is a method for forming a thin film containing a metal oxide as the main component on a substrate using a mixed gas stream containing a metal chloride, an oxidizing material, and hydrogen chloride, by a thermal decomposition method at a film deposition rate of 4500 nm/min. or greater, performing at least one selected from: 1) prior to mixing the metal chloride and the oxidizing material in the mixed gas stream, contacting hydrogen chloride with at least one selected from the metal chloride and the oxidizing material, and 2) forming a buffer layer in advance on a surface of the substrate on which the thin film containing a metal oxide as the main component is to be formed.

Abstract: Semiconductor devices having a via hole and methods for forming a via hole in a semiconductor device are disclosed. A disclosed method comprises performing a first etching process on an insulating layer to form a via hole, and performing a second etching process to enlarge a bottom of the via hole.

Abstract: An apparatus for singulating and bonding semiconductor chips includes a singulating station and a mounting station. In the singulating station, a semiconductor chip is provided with a bonding wire by a bonding tool and lifted off a carrier film. Then, in the mounting station, the semiconductor chip is placed on a chip mounting surface and fixed in place. The bonding wire is guided to a contact-connection surface of the circuit carrier and bonded to this surface.

Abstract: A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask layer, formed to project into the inside of the wiring groove pattern, into a tapered shape; forming a contact hole pattern in the second and first mask layer, and removing the tapered shape portions of the third mask layer; and forming wiring grooves in the second insulation film by etching using the third mask layer, and forming contact holes in the insulation film by etching using the second and first mask layers.

Abstract: A metal filled dual damascene structure with a reduced capacitance contribution and method for forming the same, the method including forming a first metal filled damascene lined with a first metal barrier layer thickness in a first dielectric insulating layer; and, forming a second metal filled damascene lined with a second metal barrier layer thickness overlying the first metal filled damascene in a second dielectric insulating layer.

Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, to prevent a defective contact of a line in a method of completely filling a minute contact hole having a high aspect ratio with a refractory metal layer, which includes the steps of forming a contact hole in an insulating interlayer of a semiconductor substrate; depositing a barrier metal layer on an inner surface of the contact hole and an upper surface of the insulating interlayer, wherein the process of depositing the barrier metal is performed by sequentially progressing one cycle of: injecting a reaction gas of SiH4 to the chamber, injecting a first purging gas to the chamber, injecting a reaction gas of WF6 to the chamber; injecting a second purging gas to the chamber, injecting a reaction gas of NH3 to the chamber, and injecting a third purging gas to the chamber; depositing a first metal layer for nucleation on the barrier metal layer by the atomic layer deposition process; and depositing a second metal layer on the first meta

Abstract: A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative polish stop layer over the insulative material, and an insulator layer over the insulative polish stop layer. A contact opening is formed into the insulator layer, the insulative polish stop layer and the insulative material to proximate the node location. A conductive material is deposited over the insulator layer and to within the contact opening. The conductive material and the insulator layer are polished to at least a portion of the insulative polish stop layer. In one implementation and prior to depositing the conductive material, at least a portion of the contact opening is widened with an etching chemistry that is selective to widen it within the insulative material to a degree greater than any widening of the contact opening within the insulative polish stop layer.

Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.

Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

Abstract: A method for forming an Al interconnect is disclosed. A disclosed method comprises: depositing a Ti layer on a substrate having predetermined devices; depositing a TiN layer on the entire surface of the Ti layer by performing a CVD process; performing a plasma treatment for the TiN layer; depositing an Al layer on the TiN layer; and forming an ARC on the entire surface of the Al layer.

Abstract: A method for controlling an apparatus to perform a multi-layer chemical mechanical polishing (CMP) process with a polishing rate for a plurality of process runs. For each process run, a multilayered structure with a first thickness formed on a wafer is polished and a second thickness of the multilayered structure is predetermined to be polished away. The method comprises steps of receiving a post-CMP thickness information of the multilayered structure of a first process run, wherein for the first process run, the CMP process is performed for a first CMP process time. Then, a second CMP process time is determined according to the first CMP process time, the first thickness and the post-CMP thickness. Further, the second CMP process time is provided to the apparatus for processing a second process run posterior to the first process run.

Abstract: Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes creating a first set of process conditions to etch the first material, generating a second set of process conditions to etch the second material; and establishing an additional set of process conditions to concurrently etch the first and second materials at substantially the same etch rate.

Abstract: A method of fabricating polycrystalline silicon thin film transistor according to the present invention includes: depositing a buffer layer on a substrate; depositing an amorphous silicon layer on the buffer layer with a predetermined thickness; crystallizing the deposited amorphous silicon layer by using a laser to form a polycrystalline silicon layer; etching the crystallized polycrystalline silicon layer to a predetermined thickness; curing the etched polycrystalline silicon layer; and patterning the cured polycrystalline silicon layer to form a semiconductor layer.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: A method of fabricating the gate spacers of semiconductor devices is disclosed. An example method forms a gate on a semiconductor substrate, deposits a buffer oxide layer and a nitride layer sequentially on the whole semiconductor substrate including the gate, and forms spacers by etching the nitride layer.

Abstract: A circuitry sheet (322) comprising an electronic device layer stack (304) containing electronic devices, e.g., thin-film transistors, or portions thereof, formed by removing material from both sides of the device layer stack. The circuitry sheet may be made by an electronic/optoelectronic device manufacturing method (200) that includes the steps of forming the device layer stack on a temporary substrate (300), removing material from both sides of the device layer stack, and then attaching a permanent substrate (348) to the device layer stack. The method uses one or more resist layers (600) that may be activated simultaneously and independently to impart distinct circuit pattern images (603, 608, 612) into each of a plurality of image levels (612, 616, 620) within each resist layer, thereby obviating repetitive sequential exposure, registration and alignment steps.

Abstract: A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features using an off-axis lithography method. A portion of the pattern for the array of features is transferred to the first hard mask. The first hard mask is then used as a mask to pattern the material layer.

Abstract: Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A method of forming a thin film on a substrate to fabricate a microelectronic device, a microelectronic device comprising a thin film deposited according to the method, and a system comprising the microelectronic device. The thin film may include on of a low k thin film, a thin film comprising photoresist, and a sacrificial polymer. The method comprises dispersing a precursor preparation into a spray of charged droplets through subjecting the liquid precursor preparation to electrostatic forces; directing the charged droplets to move toward the substrate; and allowing the charged droplets to generate a beam of gas-phase ions as the charged droplets move toward the substrate. The method further includes directing the gas-phase ions to impinge upon the substrate to deposit the thin film thereon to yield a deposited thin film on the substrate.

Abstract: It is an object of the present invention to improve the surface planarity of a film by uniforming the thickness of an insulating layer. Further, it is another object of the invention to provide a technology for manufacturing an electronic device typified by a high-definition and high-quality display device with high yield at low cost with the use of the insulating layer. In a method for manufacturing a semiconductor device according to the invention, a semiconductor layer is formed; an insulating layer is formed over the semiconductor layer; a wiring layer connected to the semiconductor layer is formed in an opening provided in the insulating layer; and an electrode layer connected to the wiring layer is formed. The insulating layer is formed by spin coating with a composition containing an insulating material, which has a viscosity of from 10 mPa·s to 50 mPa·s.

Abstract: A method of depositing a organosilicate dielectric layer exhibiting high adhesion strength to an underlying substrate disposed within a single processing chamber without plasma arcing. The method includes positioning a substrate within a processing chamber having a powered electrode, flowing an interface gas mixture into the processing chamber, the interface gas mixture comprising one or more organosilicon compounds and one or more oxidizing gases, depositing a silicon oxide layer on the substrate by varying process conditions, wherein DC bias of the powered electrode varies less than 60 volts.

Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.

Abstract: The present invention is directed to a scrim comprised of a plurality of warp and weft tapes, and more specifically to a woven scrim comprised of warp tapes and weft tapes, wherein the warp tapes are positioned in first and second planes to increase the warp coverage by at least 150% such that the resulting scrim material is impervious to light and further deters bunching of the warp tapes.

Abstract: A backing material is made of low-density and/or high-density polyethylene(s) and/or a flexibilizer to provide high-strength, low-cost, and recyclable backing material for fabrics. The backing material can incorporate polypropylene(s), additional flexibilizers, fillers, flame-retardants, anti-microbials, odor minimizers/eliminators, scent, and protectants for further desired properties.

Abstract: The invention is a heat curable extruded adhesive laminate system for producing collapsible tanks. The laminate is a composite of a fabric; an extruded linear hydroxyl adhesive having an uretdione that serves as a latent thermally activated curing component, and a high cyrstallinity thermoplastic polyurethane. In the system, panels cut from the adhesive laminate are assembled and seamed in a compression press operating at about 260° F. to about 350° F. The bonding process takes about 20-45 minutes, which causes the latent thermally activated curing component to cure the adhesive. Following compression heating in the press, the resulting seams have a strength that exceeds the minimum acceptable performance of 25 lbs/in, after being immersed in water and/or fuel at 160° F. for six weeks.

Abstract: The present invention relates to a flexible sheet having a composite structure for stabilizing coatings, comprising a first layer of fiber material and a second layer of fiber material impregnated by a first and a second impregnating material, respectively, and a body layer set between said first layer and said second layer according to a general sandwich structure, where the body layer consists of a third material. The first and the second impregnating materials and the third material constituting the body layer are polymeric materials presenting a substantial affinity, so that the flexible sheet has a physically heterogeneous and chemically homogeneous structure.

Abstract: The invention relates to a nonwoven highloft flame barrier well suited for use in mattress, upholstered furniture and other end use applications where a highloft nonwoven material is desired for flame barrier purposes. A preferred nonwoven highloft flame barrier of the invention comprises a blend of fibers, that are inherently fire resistant and essentially nonshrinking to direct flame, with melamine fibers being preferred either alone or in conjunction with, for example, viscose rayon based fibers, fibers extruded from polymers made with halogenated monomers and preferably low-melt binder fibers, which are thermally activated in a highloft manufacturing process to provide low bulk density, resiliency and insulation properties in the end use application. The preferred fiber blends are designed to withstand extended periods of time exposed to open flame with minimal shrinkage of the char barrier; thereby preventing a flames from “breaking through” the char barrier and igniting underlying materials.