Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: A connector may include lead frame assemblies that each includes contacts arranged in a column. Differential signal pairs may be formed from contacts of adjacent lead frame assemblies. A contact of such differential signal pairs may be staggered along the lead frame assembly with respect to the other contact of the pair. Additionally, adjacent lead frame assemblies may be structurally identical but one of the lead frame assemblies may be rotated 1800 with respect to the adjacent lead frame assembly. A connector may include contacts that may be front loaded so that, after the connector is connected to a substrate, individual contacts may be removed without removing the connector from the substrate. The connectors may be capable of being rotated 90° relative to one another such that they may be connected to opposite sides of a substrate such as a midplane.

Abstract: The present invention relates to a device for capacitive position finding of an object, with a plurality of capacitive probes distributed over an area in which a position of the object is to be established. According to the invention the device is characterized in that the probes are in each case connected by means of coupling capacitances to a voltage source and can be supplied with a supply voltage and that an evaluating device connected to the probes is provided permitting the processing of the probe signals to an output signal, which is a measure for the position of the object to be established. In further aspects the invention relates to a probe/sensor arrangement and a method for capacitive position finding of an object.

Abstract: Cylindrical capacitance force sensing device/method is disclosed. In one embodiment, an apparatus includes a capacitor having two parallel conductive surfaces, a cylindrical housing with a cover plate to encompass the capacitor, and a sensor in the cylindrical housing to generate a measurement based on a change in a distance between the two conductive surfaces when the cover plate is deflected by a load applied on the cover plate. In another embodiment, a method may include applying a load on top of a housing which encompasses a capacitive sensor having two parallel conductive surfaces to produce a deflection of a cover plate of the housing, automatically generating a measurement from the capacitive sensor when a distance between the two parallel conductive surfaces is charged due to the deflection of the cover plate, and decreasing an error in the measurement via stabilizing to a mounting surface.

Abstract: An electronic pressure switch has only two terminals, a resistance measuring bridge pickup, an amplifier unit downstream of the resistance measuring bridge, a comparator connected to the amplifier unit and a switching stage downstream of the comparator achieves a lower residual current in the blocked state and a lower voltage drop in the switched state. The resistance measuring bridge has a high internal resistance and the amplifier unit supplies both an analog measurement signal corresponding to the analog measured value of the resistance measuring bridge and a threshold value to the comparator at low resistance. A high-resistance balancing network is assigned to the resistor network, and an in-phase regulator on the input side limits and controls the supply voltage of the resistance measuring bridge, the amplifier unit, the comparator and the balancing network and the switching stage is made as a shunt controller triggered by the output of the comparator.

Abstract: A circuit arrangement for detecting a load current through a load includes a main transistor, a sensing transistor through which a load current flows that is a measure of the load current flowing through the main transistor, a means of resistance which is connected in series with the load path of the sensing transistor, a current source which is connected to a node which is arranged between the sensing transistor and the means of resistance, and a detector which detects the load current flowing through the main transistor by measuring the voltage across the means of resistance.

Abstract: A system for detecting the position and/or the dimensions of mechanical pieces (3) includes a checking probe (1) with detection devices (2) and a remote transmitter (4), a receiver (7) being remotely placed from the probe to wirelessly receive, from the remote transmitter, pulse signals (5) indicative of the state of the probe. The receiver includes automatic control circuits that detect the presence of noises (NS) on the basis of attributes, e.g. the distribution in amplitude, of the received signal and, consequently, dynamically vary the sensitivity of the receiver, e.g. by acting on the amplification of the received signal or on a threshold (VTH) with which the received signal is compared. The pulse signals can be of optical type and the automatic control of sensitivity can be active in the presence of noise signals emitted by lamps located in the environment.

Abstract: Systems and methods for providing a stack with a guard plane embedded in the stack are disclosed. An electrical apparatus can be made by forming a stack comprising an electrically conductive signal structure, an electrical guard structure, and an electrically insulating structure disposed between the signal structure and the guard structure. The signal structure, insulating structure, and guard structure can be aligned one with another in the stack.

Abstract: A guided wave radar level gauge for determining a process variable of a product in a tank, comprising a feed through fitting, a probe extending into the tank, transceiver circuitry mounted on a circuit board, a housing having a body portion for accommodating said circuit board, and a neck portion for attachment of said housing to said feed through fitting, a rigid, essentially straight, coaxial connector arranged in said neck portion, said connector having a central lead portion without detachable connections, a first end of said lead portion protruding into said body portion, and a second end of said lead potion in electrical contact with said probe when said housing is attached to said feed through fitting, wherein said circuit board is mounted in direct contact with said first end of said lead portion, so that said connector provides electrical contact between said probe and said transceiver circuitry.

Abstract: A novel structure for a probe card that comprises a deformable metal or other deformable material for detecting excess overdrive and a method for using the same are disclosed. This detection structure may be positioned on the substrate along the bending path of the probe, such that should the probe experience excess overdrive, then the detection structure will permanently deform where it is hit by any portion of the probe. Alternatively, the detection structure may be embedded in the substrate, and may also function as a fiducial for alignment detection. Inspection of the probe card, and specifically the detection structure, will reveal whether any probe has experienced excess overdrive. Should the inspection reveal that certain regions of the card experienced excess overdrive, this may indicate a planarity problem that affects production line yield.

Abstract: A sheet-like probe and a method of producing the probe. In the probe electrode structure bodies do not come out from an insulation film and achieve high durability, and in a burn-in test for a wafer having a large area and for a circuit device having to-be-inspected electrodes with small intervals, positional displacement, caused by temperature variation, between the electrode structure bodies and the to-be-inspected electrode can be reliably prevented for stable connection conditions. The sheet-like probe includes an insulation layer and a contact film provided with electrode structure bodies arranged on the insulation layer to be apart from each other in the surface direction of the insulation layer and penetratingly extend in the thickness direction of the insulation layer. The electrode structure bodies each are composed of a surface electrode section exposed to the front surface of the insulation layer.

Abstract: A probe assembly having a switch that selectively electrically connects, for example, either a Kelvin connection or a suspended guard element with the probe assembly.

Abstract: A robot for medical ultrasonic examination has an articulated robot arm with a plurality of arm units (14-16), mounted one on the other to be pivotable, and a computerized system for controlling the movements of the arm, the outermost arm unit being arranged to carry a probe. The outermost arm unit has a carrying member rotatable about a longitudinal axis (IV), and carries a probe holder pivotable about a transverse axis (V) perpendicular to the longitudinal axis (IV). The probe holder has a housing rotatable about the transverse axis, and a holder sleeve rotatable about a longitudinal axis (VI). The three axes (IV, V, VI) intersect at a single point. The probe holder has an opening through which the probe can be inserted from the back and locked in position in the probe holder.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: A wafer holder with which probing can be performed with little or virtually no noise due to the wafer being shielded from electromagnetic waves; and a wafer prober on which the wafer holder is mounted. The wafer holder of the present invention includes a chuck top for mounting a wafer, and a resistance heat generator for heating the chuck top. At least part of the resistance heat generator is covered by an insulating layer, and an electrically conductive layer is present on an opposite side of the resistance heat generator having the insulating layer. The electrically conductive layer blocks electromagnetic waves that adversely affect inspection. The insulating layer preferably covers the entire surface of the resistance heat generator, and the electrically conductive layer preferably covers the entire surface of the resistance heat generator comprising the insulating layer.

Abstract: A wafer holder is provided having high rigidity and an enhanced heat-insulating effect that allow positional accuracy and heating uniformity to be improved, a chip to be rapidly heated and cooled, and the manufacturing cost to be reduced, and a wafer prober apparatus on which the wafer holder is mounted. The wafer holder of the present invention includes a chuck top for mounting a wafer, a support member for supporting the chuck top, and a stand for supporting the support member. The chuck top has a thermal conductivity K1 and a Young's modulus Y1; the support member has a thermal conductivity K2 and a Young's modulus Y2; and the stand has a thermal conductivity K3 and a Young's modulus Y3. K1>K2 and K1>K3; and Y3>Y1 and Y3>Y2.

Abstract: A device is provided for subjecting a plurality of singulated semiconductor components to functional verification, which includes contact pins that are integrated in a test socket and establish a mechanical and electrical contact between the test socket and the integrated semiconductor circuits, a holding fixture (DUT board) connected to the test socket for transmitting electrical signals to and from a program-controlled electronic switching system, and lines and control devices for operating at least one pneumatic transport and holding device for picking up, orienting and positioning the singulated semiconductor components, an inert gas is provided as the medium for operating the pneumatic devices.

Abstract: A interface board is provided with a first and second contact instruments each comprising a first and second contact terminal groups to which a first to third type semiconductor devices having different numbers of external terminals used can be connected. The first contact terminal group of the first contact instrument is connected to the corresponding terminals of the second contact terminal group of the second contact instrument using bridging lines. One end of each bridging wire is connected to a driver output pin of an IO channel provided in pin electronics. The other end of the bridging wire is connected to a comparator input pin of the IO channel provided in the pin electronics. The first contact terminal group of the second contact instrument is connected, using different connection lines, to a driver output pin and a comparator input pin of an IO channel provided in the pin electronics.

Abstract: A technique of monitoring strain on a printed circuit board assembly involves the use of a strain detector mounted on a printed circuit board. The strain detector is formed of a non-ductile material. The strain detector has a narrowed portion forming a weak link that has a characteristic of breaking when a critical strain limit is exceeded. The method of monitoring can include visual or electrical inspection. The electrical inspection can include having a strain monitoring device. The strain monitoring device has a timer connected to at least one strain detector and a memory for storing results connected to the timer. The capacitance of at least one of the strain detectors is sampled and any change in capacitance is recorded to the memory. In one embodiment, a time stamp occurs in the memory based on when an electrical property changes across at least one of the strain detectors.

Abstract: The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

Abstract: The present invention discloses a method and an apparatus for silent current detection. By measuring voltage of a control output of a driver control circuit for driving an application device, leakage current of the driver control circuit can be detected. If the application device has an energy bandgap, short or open states of the device can further be detected. These detections are achieved, no matter whether the application device is driven or not.

Abstract: A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Abstract: A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: A motor system utilizes a single feedback output to determine various fault states for a 3-phase motor in a non-operational condition. The same single feedback output may be used to determine the applied phase voltage for a 3-phase motor in an operational condition.

Abstract: A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.

Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: An aggregation interconnect scheme for a programmable logic device provides low-skew routing of high fan-out signals by aggregating regional routing resources, which provide low-skew routing utilizing under-utilized global routing resources.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a data input signal in response to a first control signal and a second control signal. The second circuit may be configured to (i) generate the first control signal and the second control signal and (ii) determine whether the first circuit is coupled to (a) a first logic level circuit when in a first state and (b) an impedance circuit and a second logic level circuit when in a second state.

Abstract: An electrical system including a signal line and a driver. The signal line is terminated via a passive component. The driver is configured to receive an input signal and provide an output signal via the signal line. The driver is configured to provide an output logic level in the output signal at a first drive strength and to switch and provide the output logic level in the output signal at a second drive strength. The first drive strength is greater than the second drive strength.

Abstract: A pulse generation section generates a pulse which is at H-level for the predetermined period of time from the timing of the input signal DATA changing to L-level. A main output section outputs a signal of L-level with transistors P1, N1, and N2 turned ON, while the pulse generation section outputs a pulse. When the pulse falls, the transistors P1 and N1 are turned OFF, and a potential of an output node is held at L-level by resistors of a L-level holding section.

Abstract: The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control terminals of at least one transistors (MN1, MN2) of first and second transistor pairs (MP1, MN1 and MP2, MN2) that constitute first and second inverters, respectively, are connected to inputs of first and second inverters through first and second capacitances (C1, C2), respectively. At resetting, inputs (1, 2) and outputs (OUT, OUTB) of first and second inverters are not mutually cross-connected, wherein a reference signal (VR) is supplied in common to inputs (1, 2) of the first and second inverters. The one transistors (MN1, MN2) are diode-connected. Voltage differences between reference signal (VR) and respective control terminals of the one transistors are stored in the first and second capacitances (C1, C2), respectively.

Abstract: The present invention provides a sense amplifier including a current sense circuit that outputs a detection voltage corresponding to an electric current intended for comparison, a current sense circuit that outputs a reference voltage corresponding to an electric current for reference, and a comparison circuit that compares the detection voltage and the reference voltage and outputs the result of comparison thereby. In the sense amplifier, the current sense circuit is operated in accordance with a chip control signal, and the current sense circuit is operated by a delay chip control signal obtained by delaying the chip control signal by a predetermined time by means of a delay circuit. Thus, since the current sense circuit outputs a predetermined reference voltage when the operation of the current sense circuit is started, the detection voltage rapidly converges on a predetermined level without performing such a feedback operation as to repeat its abrupt rise and fall.

Abstract: An electronic circuit includes a semiconductor device which has an internal circuit that uses a positive power supply voltage and a negative power supply voltage, and which controls the operation of the above-mentioned internal circuit by an external input. The semiconductor device includes an input signal detection circuit that operates using a voltage that is input into the external input, and a signal output circuit which outputs a signal that controls the negative power supply voltage applied to the internal circuit in accordance with an output of the input signal detection circuit. The circuit can switch a negative-side circuit on and off without depending on a positive power supply voltage and also without depending on the order of starting a positive power supply voltage and a negative power supply voltage.

Abstract: Embodiments of the present invention are directed to current driver circuits and methods for driving a load. The current driver circuit includes a first transistor (Q1) and a second transistor (Q2) each having a gate, a drain and a source. The drain of the second transistor (Q2) forms the output of the current driver circuit. The first and second transistors (Q1) and (Q2) function as a current mirror when the gates of the first and second transistors (Q1) and (Q2) are selectively connected together. The current driver circuit also includes a current source, a load mimic circuit, and a control loop (e.g., including an op-amp), which are configured to cause the voltage at the drain of the first transistor (Q1) to substantially equal the voltage at the output of the current driver circuit.

Abstract: Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the timing circuit are also biased from a current of a lock loop circuit to further adjust slew rate of the output signal. Transmit pre-emphasis of the output signal is adjusted by selecting a polarity of a selected delayed data signal in each of the plurality of adjustable impedance circuits. Each adjustable impedance circuit also includes a predriver and driver for adjusting impedance in response to a signal indicating an impedance value.

Abstract: A first transistor is provided in a first route and a second transistor is provided in a second route, the first route and the second route constituting a current mirror circuit. The sources of the transistors are grounded. In order to match VDS of the first transistor and that of the second transistor match each other, there are provided an operational amplifier receiving the drain voltages of the transistors, and a third transistor having a gate thereof connected to the output of the operational amplifier. The third transistor is provided in the first route. As a result, the current fed to the third transistor is controlled so that VDS of the first transistor and that of the second transistor match each other.

Abstract: A circuit for reducing jitter and/or phase jump problems in a clock amplifier device due to variations in the voltage supplied to the clock amplifier device has an input terminal connected to the supply voltage to allow the circuit to sense the actual supply voltage, and an output terminal connected to an output of the clock amplifier device. The circuit is provided to draw a current from, or feed a current to, the output of the clock amplifier device via the output terminal in response to a difference between the sensed actual supply voltage and a desired supply voltage. The circuit is preferably implemented in a first stage of a CMOS inverter chain in a GPS navigator device.

Abstract: This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.

Abstract: In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.

Abstract: A phase-locked loop (PLL) circuit includes a phase/frequency detector (PFD), a charge pump, a loop filter, a control circuit, a VCO, and a feedback circuit. The control circuit generates a digital control signal in response to the up signal, the down signal, and the oscillation-control voltage. The VCO generates an output signal of which a frequency is changed in response to the oscillation-control voltage and the digital control signal. Accordingly, the PLL circuit can automatically tune the frequency of the output signal of a VCO using a digital circuit having a simple structure.

Abstract: Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.

Abstract: Method and apparatus for sampling a high-speed digital signal include providing a data signal to a differential data input circuit, an offset control signal, and a strobe pulse. In response to the strobe pulse, the data signal is resolved into an output logic state based to a relatively greater extent on the differential data signal and to a relatively lesser extent on the offset control signal.

Abstract: A delaying circuit is capable of constantly maintaining its delay regardless of process condition or voltage variation and a pulse generating circuit uses the delaying circuit. The delay circuit for delaying a signal that is inputted to an input stage by a predetermined time to output to an output stage, comprises a pull-up unit for pulling up the output stage in response to the signal that is inputted to the input stage, the pull-up unit including a first resistor device and a first MOS transistor that is maintained in turn-on state and is coupled to the first resistor device in parallel to delay the signal that is inputted to the input stage by the predetermined time; and a pull-down unit for pulling down the output stage in response to the signal that is inputted to the input stage.

Abstract: The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit.

Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. The control circuitry detects a voltage at the first signal input that exceeds the specified maximum supply voltage by a given amount and, in response, applies a drive signal to the input of the gate circuit.

Abstract: An apparatus and method is disclosed for generating path length information for two (usually redundant) receive paths in a receiving device such as a server blade so that the proper amount of equalization and/or pre-emphasis may be applied to receiver and driver circuits in the server blade. In one embodiment, the path length information comprises a longer or shorter path determination, and may also include a estimation of the slot location. In another embodiment, the path length information comprises a representation of the length of two receive paths. The path length information generating circuit is connected to the two receive inputs of the receiving device though high impedance elements, and the path length information may be utilized by hardware or a processor to set the equalization or pre-emphasis in the receiver and/or driver.