Abstract: A ball glove includes impact detection and annunciation circuitry for detecting an impact event, such as contact of a caught ball with the glove. Upon detection of an impact, annunciation circuitry provides a visible light signal, such as flashing a sequence of lights located in the web portion of the glove.

Abstract: A lighting assembly that includes a light fixture adapted to be disposed in relation to an opening defined in a surface of a structure such that a lamp may be installed in the light fixture through the opening, a trim having an outer surfaces, and an intumescent layer on the outer surface of the trim. The trim is adapted to engage the light fixture so that the outer surface of the trim on which the intumescent layer is disposed is positioned in proximity to the opening in the structure. The intumescent layer is adapted to expand to form a fire resistant seal between the trim and the structure when the intumescent layer reaches a predetermined temperature.

Abstract: Methods and apparatus for downloading one or more lighting programs including one or more lighting effects. The lighting program(s) may be downloaded from a web site to one or more LED-based lighting devices that are configured to execute the downloaded lighting program(s) so as to reproduce the lighting effect(s). In various examples, a variety of programming devices may be employed to facilitate wired or wireless downloading, including one or more computers, personal digital assistants (PDAs), cell phones, media players (e.g., MP3 players), and the like. Information may be uploaded to the web site to facilitate selection and/or creation of lighting effect(s) that are included in the downloaded lighting program(s).

Abstract: An adjustable lighting fixture has a moveable housing. A first housing has a first opening and a second opening. A second housing is adapted to movably engage the first housing. A resilient member is connected to the second housing and adapted to be received by one of the first and second openings in the first housing. The first opening corresponds to a contracted position of the lighting fixture and the second opening corresponds to an expanded position of the lighting fixture. A lamp disposed in the lighting fixture has a longitudinal axis that is substantially perpendicular to a direction of movement of the first and second housings.

Abstract: A contact lens case is described which, in some embodiments, includes a housing having at least one contact lens receiving receptacle, an electrical power source mounted to the housing; and at least one light emitting device mounted to the housing. At least a portion of the contact lens receiving receptacle is substantially light transmittable. When a contact lens is placed in a receptacle and light is emitted from the light emitting device, light is transferred through the receptacle and the contact lens is illuminated to improve visual detectability of the contact lens.

Abstract: Disclosed is a mountable lighting module that uses solar energy to charge a power source for LEDs used in night illumination of both sides of a double-faced sign with the mountable lighting module comprising housing for the electronics conjoined with a clamp for mounting to a sign support and a pair of sign illuminating members with each extending over opposing sides of the sign directly illuminating the sign's copy area.

Abstract: An illuminating lamp device comprises a conductive casing having a transparent portion; a seat installed below the casing; a power source; a switch for actuating the power source and movably installed in the seat and passing through the seat to protrude out of a bottom of the casing; a conductive sheet extending from the switch; one end of the conductive sheet being connected to the power source; a lamp for emitting light; the lamp having two electrodes; one electrode being in contact with the casing; another electrode being placed above the conductive sheet; when the electrode being in contact with the conductive sheet, the circuit is conducted so that the lamp lights up. When the switch is pressed, the conductive sheet extending from the switch will contact the electrode so as to form an electric loop including the power source, conductive sheet, electrode, lamp and casing; and thus the lamp lights up.

Abstract: A fluorescent lamp unit employing a fluorescent tube having a double spiral configuration is provided. The fluorescent lamp unit include a double spiral configured fluorescent tube having an upper central portion from which two spiral portions extend at a downward incline and wind around a vertical axis such that an outer diameter of the double spiral configuration increases as the spiral portions extends from the upper central portion to sealed ends of the fluorescent tube. The fluorescent lamp unit further includes a ballast housing having an electronic ballast contained therein. The ballast housing is partially enclosed by the spiral portions of the fluorescent tube.

Abstract: The invention relates to a system for reducing the coherence of a wave front-emitting laser radiation, especially for a projection lens for use in semiconductor lithography, wherein a first partial beam of a laser beam incident on a surface of a resonator body is partially reflected. A second partial beam penetrates the resonator body and emerges from the resonator body at least approximately in the area of entry after a plurality of total internal reflections. The two partial beams are then passed on jointly to an illumination plane. The resonator body is adapted, in addition to splitting the laser beam into partial beams, to modulate the wave fronts of at least one partial beam during a laser pulse. The partial beams reflected on the resonator body and penetrating the resonator body are superimposed downstream of the resonator body. The resonator body is provided with a phase plate having different local phase distribution.

Abstract: A light source module includes a light source for generating light beams, a first lens array positioned on a side of the light source, and an invisible-light cut filter positioned on a side of the first lens array away from the light source, wherein the invisible-light cut filter is nonparallel with the first lens array.

Abstract: Embodiments of the present invention are directed to an illuminating optical device for forming a field of illumination. The optical device includes a first one-dimensional homogenizer positioned to homogenize a first dimension/axis of the field of illumination and a second one-dimensional homogenizer positioned to homogenize a second dimension/axis of the field of illumination.

Abstract: A luminaire capable of selectively directing light from a lamp therein generally upwardly, downwardly, and outwardly, the combination comprising an electrical housing having a generally downwardly directed socket adapted to receive and support a generally vertically oriented lamp, and having a plurality of coupling members positioned around the socket; an upper reflector, coupled to the housing, and having at least a first portion located to reflect light from a lamp received in the socket; at least one reflector module; at least one fastener for coupling the at least one reflector module to at least one of said plurality of coupling members supported by the housing in a selected location to reflect light emitted from the lamp in a selected direction; and a refractor coupled to and extending downwardly from the housing, substantially enclosing the socket, upper reflector, and reflector module, and transmitting light from the lamp to the outside of the luminaire.

Abstract: The invention relates to a packaging or support comprising a receiving pocket or a fastening means for a lamp. According to the invention, the on/off switch of the inserted flashlight is freely accessible, or an externally actuated means is provided for actuating a pressure switch, or an external switch is provided which is separated from the packaged lamp and forms part of an electrical circuit along with a wiring that is disposed in the packaging or the support, said electrical circuit also encompassing the flashlight battery and the light source.

Abstract: A roof structure for a trailer includes a roof sheet, a roof bow attached to the roof sheet, and a member attached to one of said roof sheet and said roof bow. The member has a plurality of LED lights attached thereto.

Abstract: A vehicle lighting system for attachment to a vehicle spoiler, a vehicle spoiler and a vehicle that includes the vehicle spoiler and vehicle lighting system. The vehicle lighting system includes a light support that is shaped and dimensioned for attachment to a vehicle spoiler, and attachment means, such as screws, bolts or clips for attaching the light support to the vehicle spoiler. A plurality of light emitting diodes is attached to the light support. A substantially transparent lens is attached to the light support and dimensioned such that the lens covers the plurality of light emitting diodes. At least one electrical connector is placed in communication with the plurality of light emitting diodes and is adapted for connection to a source of electrical power of the vehicle.

Abstract: A door handle portion illumination system for illuminating a door handle portion including a door handle, and a concave portion that is formed on a vehicle body in a position which lies at the rear of the door handle, the door handle portion illumination system including a light transmitting element that is incorporated in the door handle and which includes a luminous surface including, in turn, an area which is exposed on a front side of the door handle and an area which faces an edge portion of the concave portion, and a light source which emits a light that is introduced into the light transmitting element.

Abstract: Undercarriage lights are positioned under a truck adjacent to parts of the truck requiring regular visual safety inspections to light up the parts. A control module operates the lights in coordination with an ignition switch, a manual switch outside the truck, a timer, a low light sensor, and an indicator light.

Abstract: The present invention generally relates to video and/or television projection systems, and more particularly, to LED based light source systems utilizing generally non-rotationally symmetric, preferably oblong or rectangular, non-imaging collection optics for providing improved projection systems relative to arc lamp and other LED based light source systems. The non-rotationally symmetric non-imaging collection optics are configured to operate with LEDs to provide preferred, generally, uniform light distributions whose étendues match those of downstream applications such as those encountered in projection systems. Also provided are various arrangements for coupling LED output to the entrance aperture of collection optics and for coupling the outputs from a plurality of collection optic outputs to form single beams of illumination of preferred patterns, intensities, and color.

Abstract: A light guide member illuminates with uniform light intensity distribution using the point light source light. On the lower end of the light guide member having a pair of side faces disposed oppositely, a groove is provided for receiving light output from each point light source and diffusing the above received light to at least three directions from the incident side toward the output side. Light components having directions using side-face reflection are generated in the light guide member, enabling light output to multiple directions from the cylindrical-shaped light guide member, and uniform illumination over a wide range. By using the ring-shaped light guide member, cost reduction is effectively achieved, and miniaturization of the illumination mechanism and the image capturing mechanism can also be attained.

Abstract: A prism sheet includes a main body. The main body includes an incident surface, an emitting surface opposite to the incident surface, and a plurality of micro-protrusions formed on the incident surface. Each micro-protrusion includes two side surfaces and an arced ridge of intersection of the two side surfaces. Each side surface is a conical surface of an imaginary cone. The imaginary cone has a conical base whose circumference is defined by the arced ridge. The conical bases defined by the arced ridges of the micro-protrusions are parallel to each other. The present prism sheet and the backlight module using the same can efficiently decrease interference.

Abstract: In some embodiments of the invention, a solar powered decorative product can include a base having a plurality of connectors. A plurality of decorative structures can attach to and be detached from the connectors. A solar panel can be configured to provide electrical power for lighting the decorative structures.

Abstract: The present invention provides a control power supply capable of stably operating to output a desired voltage as electric power, even when the input voltage thereof varies over a wide range. A power supply includes a rectification circuit 2 for rectifying the AC output from a power generator 1 and a non-insulation type DC/DC converter 3 for stepping down the DC output from the rectification circuit 2. A self-excited oscillation type converter (RCC) 4 is provided at the following stage of the non-insulation type DC/DC converter 3. The input voltage which has been stepped down by the converter 3 is input to the primary side of the RCC 4, and the RCC 4 stably operates with the input voltage which varies largely to supply, from its secondary side, a power supply to an ECU 5 or the like.

Abstract: A power supply including an inverter receiving a DC input signal from a DC input source (11). The inverter is implemented as a single-ended inverter. Each inverter is driven by a signal source (13A, 13B), which outputs an AC signal. The output from each inverter is input to a first stage harmonic filter. The power supply includes an output circuit that includes a rectifier (D1) arranged about a point so that if the inverter attempts to drive the point beyond a predetermined voltage, the rectifier conducts in order to return at least one of power and current to the DC input source. The output from the first harmonic filter (L1A, C1; L1B, C1) is output to a second harmonic filter (L2, C2) and is then output from the power supply.

Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.

Abstract: A semiconductor memory according to an example of the present invention is provided with a memory cell array, a plurality of word lines provided on the memory cell array, and a plurality of transfer transistors each one of which is connected to each of the plurality of word lines. Direction of one of the plurality of transfer transistors is different from direction of another one of the transfer transistors.

Abstract: A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

Abstract: A protection device provides write-once, read many capabilities for computer long-term storage devices, such as hard drives. The blocking device is placed between a host computer and a storage device. The blocking device intercepts communications between the host and the storage device and examines any commands from the host to the storage device. Certain commands, such as commands that may modify the storage device, may be discarded. Additionally, commands that may modify the state of previously written storage areas on the storage device may be discarded.

Abstract: An electrical fuse device includes at least one electrical fuse cell having a first switch device serially coupled with an electrical fuse representing a logic value; and at least one dummy cell having a second switch device coupled to the first switch device via a common word line, the second switch device having a trigger-on voltage lower than that of the first device, such that the second switch becomes conductive earlier than the first switch device for bypassing an electrostatic discharge (ESD) current therethrough during an ESD event.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp by a bit-line precharge circuit and a source-line precharge circuit, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, by a bit-line write bias generation circuit, while the source line is grounded by a source-line write bias generation circuit. At the time of a reset operation, in contrast to the set operation, the bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp, for example.

Abstract: In a semiconductor memory device, comprising: a memory cell including a flip-flop; and a memory cell power supply circuit for supplying a low voltage cell power supply voltage to the memory cell, the memory cell power supply circuit supplies a cell power supply voltage in a first period and a different cell power supply voltage in a second period, a predetermined first power supply voltage in a case where the cell power supply voltage is supplied in a data read cycle and in a case where data is not written to a memory cell to which the cell power supply voltage is supplied in a write cycle, and a second power supply voltage higher than the first power supply voltage in a case where data is written to a memory cell to which the cell power supply voltage is supplied in a write cycle.

Abstract: A multi-bit magnetic memory device using a spin-polarized current and methods of manufacturing and operating the same. The magnetic memory device includes a switching device and a magnetic storage node connected to the switching device, wherein the magnetic storage node includes a first magnetic layer, a second magnetic layer and a free magnetic layer which are vertically and separately disposed from one another. The first and second magnetic layer have transmission characteristics opposite to each other for spin-polarized electrons, and have magnetic polarizations that are opposite to each other. The free magnetic layer may include first and second free magnetic layers, which are separately disposed from each other. The magnetic storage node may further include third and fourth magnetic layers that are separately disposed between the first and second free magnetic layers.

Abstract: A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

Abstract: A nonvolatile hybrid memory cell is provided. The cell is comprised of a magnetic spin storage element and one or two semiconductor FET isolation elements. The magnetic spin storage element is an electron spin-based memory element situated on a silicon based substrate and includes a first ferromagnetic layer with a changeable magnetization state, and a second ferromagnetic layer with a non-changeable magnetization state. A current of spin polarized electrons has a magnitude which can be varied so that a data value can be stored in the memory element by varying a relative orientation of the two ferromagnetic layer. An output of the device is coupled to a conventional CMOS amplifier to determine such relationship.

Abstract: A memory includes transistors in rows and columns providing an array, first conductive lines in columns across the array, and second conductive lines encapsulated by dielectric material in rows across the array. Each second conductive line is coupled to one side of the source-drain path of the transistors in each row. The memory includes phase change elements between the second conductive lines and contacting the first conductive lines and self-aligned to the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of a transistor.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a plurality of memory blocks, a main word line, a plurality of local word lines and a plurality of section word line drivers connected between the main word line and each of the plurality of local word lines and adapted to adjusting voltage levels of the plurality of local word lines in response of voltages applied to the main word line and block information. The plurality of section word line drivers include at least one first section word line driver and at least one second section word line driver. The first section word line drivers include pull-down devices while not including pull-up devices.

Abstract: A phase change memory system includes M phase change memory cells, where M is an integer greater than or equal to one. A write module selectively writes at least one of the M phase change memory cells based on a write parameter. A read module selectively reads back a resistance value for the at least one of the M phase change memory cells. A control module communicates with the write module and the read module and triggers write/read cycles N times where N is an integer greater than one. The control module also adjusts a write parameter of one of the N write/read cycles based on at least one prior resistance value and a target resistance value.

Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

Abstract: A nonvolatile memory device improves the accuracy of screening testing while applying a voltage at or lower than the limit of the withstand voltage of an element for high voltage in the screening testing. The nonvolatile memory device includes a high voltage production circuit that produces a high voltage, a high voltage waveform conversion circuit to which the high voltage is input and which converts the voltage waveform, and a memory cell section provided with memory cells in which data rewriting is performed as a result of applying the converted high voltage. The high voltage waveform conversion circuit includes a test signal input section TEST and applies the high voltage input from the high voltage production circuit to the memory cell section without converting the voltage waveform when a test signal is input to the test signal input section.

Abstract: A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and to the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver circuit configured to set the plate line to a first potential causing the first node to serve as a source node of the first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node of the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.

Abstract: The method of fabricating a multi-bit flash memory cell begins with forming an ion implantation mask exposing a portion of a channel region in a semiconductor substrate. Ions are implanted into the exposed region thereby partially coding the threshold voltage to create one ion implanted channel region with a first threshold voltage, and a second region without implanted ions having a second threshold voltage. A tunnel dielectric layer is formed over the channel region and floating and control gates are formed over the tunnel dielectric layer.

Abstract: A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in aeries together is disclosed. A select gate translator is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate translator is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.

Abstract: A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, a first page buffer block for storing data from said first memory cell array, said first page buffer block being arranged in said first memory cell array along a first direction, a second page buffer block for storing data from said second memory cell array, said second page buffer block being arranged in said second memory cell array along said first direction, a pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said pad section having a plurali

Abstract: A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes the device to output selected memory pages.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

Abstract: Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.