Patents Issued in September 11, 2007
-
Patent number: 7268004Abstract: An active matrix display that does not require a transistor or similar current switching device at each pixel. Instead, the display employs in each pixel a temperature-controlled current source that provides to the field emitters of the pixel an amount of electrical current which varies in response to the temperature of a temperature sensor. Each pixel further includes a thermoelectric heat transfer circuit which transfers heat to or from the sensor in an amount which varies in response to the video signal. Consequently, the video signal controls the temperature of the sensor within a pixel's temperature-controlled current source, which controls the current flow through the pixel's field emitters.Type: GrantFiled: January 13, 2003Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: John K. Lee
-
Patent number: 7268005Abstract: An apparatus for stacking photonic devices is disclosed. The apparatus can include a base, first and second spaced apart rail portions disposed on the base, and a vacuum guide disposed on the base between the rail portions for forming a vacuum gradient that pulls a plurality of photonic devices and spacer bars together into a stack. Optionally, spaced apart photonic device supports can be placed on the base between the rail portions to lift the photonic devices off of the surface of the base. The apparatus can also include a clamping system to hold the stack in place so that a vapor deposition process can be used to apply coatings to the photonic devices. In one exemplary embodiment, the photonic devices can be laser bars.Type: GrantFiled: October 27, 2003Date of Patent: September 11, 2007Assignee: Finisar CorporationInventors: John Chen, Chun Lei, Robert Shih
-
Patent number: 7268006Abstract: A process for forming an electronic device includes forming a first layer over a substrate and placing a first liquid composition over a first portion of the first layer. The first liquid composition includes at least a first guest material and a first liquid medium. The first liquid composition comes in contact with the first layer and a substantial amount of the first guest material intermixes with the first layer. An electronic device includes a substrate and a continuous first layer overlying the substrate. The continuous layer includes a first portion in which an electronic component lies and a second portion where no electronic component lies. The first portion is at least 30 nm thick and includes a first guest material, and the second portion is no more than 40 nm thick.Type: GrantFiled: December 30, 2004Date of Patent: September 11, 2007Assignee: E.I. du Pont de Nemours and CompanyInventors: Charles Douglas Macpherson, Gordana Srdanov, Matthew Stainer, Gang Yu
-
Patent number: 7268007Abstract: A first semiconductor layer consisting of AlGaInP is formed on a substrate consisting of GaAs by crystal growth while adding magnesium (Mg) that is a p-type dopant to the first semiconductor layer. A second semiconductor layer consisting of GaAs is then grown on the first semiconductor layer without adding any magnesium to the second semiconductor layer. Thus, the second semiconductor layer can prevent unintended doping (memory effect) produced by magnesium.Type: GrantFiled: October 7, 2004Date of Patent: September 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshikazu Onishi, Kenichi Inoue
-
Patent number: 7268008Abstract: A method for manufacturing a pressure sensor includes the steps of: preparing a semiconductor substrate; forming an insulation film on the substrate; forming a first metal film on the insulation film; forming a first protection film on the first metal film and the insulation film; forming a second protection film on the first metal film and the first protection film; performing reduction treatment of adhesive force on the second protection film, the force between the second protection film and a second metal film; forming the second metal film on the first metal film and the first protection film; and removing a part of the second metal film.Type: GrantFiled: January 5, 2006Date of Patent: September 11, 2007Assignee: DENSO CorporationInventors: Manabu Tomisaka, Yoshifumi Watanabe, Hiroaki Tanaka
-
Patent number: 7268009Abstract: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor is disclosed. An example method forms a metal pad in a pad area of a substrate having an active area and a pad area defined thereon, forms a protective layer on an entire surface of the substrate including the metal pad and selectively removing the protective layer to open the metal pad, and forms a barrier layer having a predetermined thickness on the entire surface of the substrate including the opened metal pad. Additionally, the exampled method forms red, green, and blue color filter layers on the barrier layer corresponding to the active area, forms a micro-lens over each of the color filter layers, and removes the barrier layer on the pad area.Type: GrantFiled: December 28, 2004Date of Patent: September 11, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Joon Hwang
-
Patent number: 7268010Abstract: The present invention related to a method of manufacturing an LED, including the steps of: first, forming a tape coppery metal strip; then, continuously pressing circuits on the tape coppery metal strip so as to form a carrier having circuit patterns of electric contacts on which the diode dies can be placed; next, electroplating a plurality of metal layers on the surface of the carrier; then, performing continuous injection molding on the carrier so as to form a protector having a designated shape; and curing and fixing the diode die on the carrier to connect to the terminal contact of the carrier via metal wire. A conductive or non-conductive adhesive is dropped onto the bonding position between the metal wire and the terminal of the carrier, and a soft paste is Anther applied to cover the diode die, the metal wire and the terminal.Type: GrantFiled: April 5, 2005Date of Patent: September 11, 2007Assignee: Kingbright Electronic Co., Ltd.Inventor: Wen Joe Song
-
Patent number: 7268011Abstract: Diamond heat spreaders are produced having thermal properties approaching that of pure diamond. Diamond particles of relatively large grain size are tightly packed to maximize diamond-to-diamond contact. Subsequently, smaller diamond particles may be introduced into the interstitial voids to further increase the diamond content per volume. An interstitial material is then introduced which substantially fills the remaining voids and should have favorable thermal properties as well as form chemical bonds with the diamond. Alternatively, the packed diamond may be subjected to ultrahigh pressures over 4 GPa in the presence of a sintering aid. The resulting diamond heat spreader has diamond particles which are substantially sintered together to form a continuous diamond network and small amounts of a sintering agent.Type: GrantFiled: January 30, 2004Date of Patent: September 11, 2007Inventor: Chien-Min Sung
-
Patent number: 7268012Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.Type: GrantFiled: August 31, 2004Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Li Li, William M. Hiatt
-
Patent number: 7268013Abstract: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.Type: GrantFiled: November 2, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Jerry M. Brooks, Steven G. Thummel
-
Patent number: 7268014Abstract: The invention provides a fabrication method of an LED package for easily fabricating LED packages of excellent heat radiation characteristics. In the method, a metallic package substrate having a recess and a reflecting surface formed in the recess is prepared, and the package substrate is selectively anodized and divided into two package electrode parts divided from each other. Then, an light emitting device is mounted on the bottom of the recess. Preferably, the package substrate is a metal substrate made of Al or Al-based metal.Type: GrantFiled: December 22, 2005Date of Patent: September 11, 2007Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young Ki Lee, Seog Moon Choi, Yong Sik Kim, Sang Hyun Shin
-
Patent number: 7268015Abstract: A method for wafer stacking employing substantially uniform copper structures is described herein.Type: GrantFiled: February 21, 2006Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Vijayakumar S. RamachandraRao, Shriram Ramanathan
-
Patent number: 7268016Abstract: A housing including a base and rectangular frame-shaped ribs is resin molded in one piece with a plurality of metal lead pieces, forming internal terminal portions and external terminal portions with the metal lead pieces, an imaging element is fixed onto the base inside an internal space of the housing, electrodes of the imaging element are connected respectively to the inner terminal portions of the metal lead pieces, and a transparent plate is joined to an upper face of the ribs. In order to position the transparent plate, a stepped portion is formed on the top face of the ribs by providing a lower step that is lowered along an internal periphery. The transparent plate has a size capable of being mounted onto an upper surface of the lower step within a region inward of an inner wall formed by the stepped portion of the ribs.Type: GrantFiled: July 28, 2004Date of Patent: September 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Hikari Sano
-
Patent number: 7268017Abstract: The productivity of a multilayered structure etc. is improved by easily forming insulating films for insulating internal electrode layers from side electrodes. The multilayered structure includes: a first internal electrode layer including a first conducting material extending to a first side surface of the multilayered structure and having magnetism at a predetermined temperature and a second conducting material extending to a second side surface of the multilayered structure and having no magnetism at the predetermined temperature; a dielectric layer formed on the first internal electrode layer; a second internal electrode layer including the second conducting material extending to the first side surface and the first conducting material extending to the second side surface; a first insulating film formed on the first internal electrode layer in the first side surface; and a second insulating film formed on the second internal electrode layer in the second side surface.Type: GrantFiled: September 7, 2005Date of Patent: September 11, 2007Assignee: Fujifilm CorporationInventor: Atsushi Osawa
-
Patent number: 7268018Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.Type: GrantFiled: April 5, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Stephen F. Moxham
-
Patent number: 7268019Abstract: Embodiments of methods and apparatus for high temperature operation of electronics according to the invention are disclosed. One embodiment of the invention generally includes an integrated circuit package having a substrate. A plurality of integrated circuits are coupled to a surface of the substrate. A lid is positioned above the substrate facing the surface. One or more pieces of compliant and thermally conductive material are compressed between at least one of the integrated circuits and the lid. The lid defines in part an enclosed volume containing the compliant and thermally conductive material.Type: GrantFiled: September 22, 2004Date of Patent: September 11, 2007Assignee: Halliburton Energy Services, Inc.Inventors: Christopher Golla, Roger L. Schultz, James Masino
-
Patent number: 7268020Abstract: An embedded heat spreader includes a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.Type: GrantFiled: January 25, 2007Date of Patent: September 11, 2007Assignee: Intel CorporationInventor: Pete D. Vogt
-
Patent number: 7268021Abstract: A lead frame having a structure that can discharge hydrogen adsorbed during deposition and can reduce a galvanic potential difference between plating layers and a method of manufacturing the same are provided. The method includes forming a Ni plating layer formed of Ni or a Ni alloy on a base metal layer formed of a metal, forming a Pd plating layer formed of Pd or an Pd alloy on the Ni plating layer, heat-treating the Ni plating layer and the Pd plating layer, and forming a protective plating layer on the heat-treated Pd plating layer.Type: GrantFiled: November 4, 2004Date of Patent: September 11, 2007Assignee: Samsung Techwin Co., Ltd.Inventors: Sung-kwan Paek, Se-chuel Park, Sang-hun Lee
-
Patent number: 7268022Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.Type: GrantFiled: August 25, 2004Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
-
Patent number: 7268023Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.Type: GrantFiled: May 5, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Nirmal Ramaswamy, Eric Blomiley, Joel Drewes
-
Patent number: 7268024Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.Type: GrantFiled: November 29, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, How-Yu Chen, Chien-Chao Huang, Wen-Chin Lee, Fu-Liang Yang, Chenming Hu
-
Patent number: 7268025Abstract: A pixel structure and a fabricating method thereof are described. The method comprises forming a conductive layer, a data line and a source/drain at the same time. The conductive layer has a coupling portion and a connecting portion. The coupling portion is used as a top electrode of a pixel storage capacitor, and the connecting portion connects the coupling portion and the drain. Thereafter, a contact window is defined on the connecting portion, and a pixel electrode formed subsequently can be electrically connected to the connecting portion through the contact window. Thus, the pixel electrode, the conductive layer (includes the coupling portion) and the drain are electrically connected each other. Since the contact window is not formed above the pixel storage capacitor, the leakage of the pixel storage capacitor will not occur when the etching process of the contact window etches away the gate insulating layer.Type: GrantFiled: September 28, 2005Date of Patent: September 11, 2007Assignees: Au Optronics Corporation, Sharp CorporationInventors: Chih-Hung Chiang, Daisuke Nishino
-
Patent number: 7268026Abstract: A method of forming a crystal grain for use in a semiconductor manufacturing process, the method including the steps of forming an oxide silicon film on a glass substrate, etching at least one hole at a predetermined location in the oxide silicon film, forming an amorphous silicon film over the oxide silicon film, heating the amorphous silicon film such that a portion of the amorphous silicon film in the at least one hole is in a non-melting state and a substantial remainder of the amorphous silicon film is brought into a melting state, and allowing the amorphous silicon film to cool such that crystal growth is generated using the non-melting state portion as a crystal nucleus.Type: GrantFiled: March 13, 2006Date of Patent: September 11, 2007Assignee: Seiko Epson CorporationInventor: Hiroyuki Shimada
-
Patent number: 7268027Abstract: Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrier layer, and the cap layer with the exception of a region corresponding to HEMT and MSM PD; forming a source electrode and a drain electrode of HEMT; removing the cap layer from a region corresponding to a gate electrode of HEMT and a Schottky electrode of MSM PD; forming the gate electrode of HEMT and the Schottky electrode of HEMT on the cap layer-removed region; and removing the cap layer, the barrier layer and the channel layer from a region corresponding to an optical waveguide, to expose the optical waveguide.Type: GrantFiled: September 15, 2005Date of Patent: September 11, 2007Assignee: Korea Advanced Institute of Science and TechnologyInventors: Young Se Kwon, Jung Ho Cha
-
Patent number: 7268028Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.Type: GrantFiled: April 17, 2006Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
-
Patent number: 7268029Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.Type: GrantFiled: November 19, 2004Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-kuk Chung, Joon Kim, Suk-Chul Bang, Jong-Sun Ahn, Sang-hoon Lee, Woo-soon Jang, Yung-jun Kim
-
Patent number: 7268030Abstract: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).Type: GrantFiled: February 3, 2006Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
-
Patent number: 7268031Abstract: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.Type: GrantFiled: August 11, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 7268032Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.Type: GrantFiled: September 21, 2005Date of Patent: September 11, 2007Assignee: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
-
Patent number: 7268033Abstract: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.Type: GrantFiled: January 26, 2006Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
-
Patent number: 7268034Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid pervious material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid pervious material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid pervious material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.Type: GrantFiled: June 30, 2006Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Gurtej S. Sandhu
-
Patent number: 7268035Abstract: The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cerium oxide and titanium oxide. The dielectric materials can be incorporated into any suitable semiconductor devices, including, for example, capacitor devices, transistor devices, and flash memory devices. The invention also includes methods of utilizing atomic layer deposition to form laminates of cerium oxide and titanium oxide.Type: GrantFiled: February 23, 2005Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
-
Patent number: 7268036Abstract: A semiconductor device includes: a conductive plug formed through an insulating film; a conductive oxygen barrier film formed on the insulating film so as to be electrically connected to the conductive plug and to cover the conductive plug; a lower electrode formed on the oxygen barrier film and connected to the oxygen barrier film; a capacitive insulating film formed on the lower electrode, following the lower electrode; and an upper electrode formed on the capacitive insulating film, following the capacitive insulating film. The capacitive insulating film has a bent portion that extends along the direction in which the conductive plug penetrates through the insulating film.Type: GrantFiled: December 1, 2004Date of Patent: September 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Ito, Eiji Fujii
-
Patent number: 7268037Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.Type: GrantFiled: January 24, 2005Date of Patent: September 11, 2007Assignee: Infineon Technologies, AGInventors: Stefan Jakschik, Thomas Hecht, Uwe Schröder, Matthias Goldbach
-
Patent number: 7268038Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.Type: GrantFiled: November 23, 2004Date of Patent: September 11, 2007Assignee: Newport Fab, LLCInventors: Dieter Dornisch, Kenneth M. Ring, Tinghao F. Wang, David Howard, Guangming Li
-
Patent number: 7268039Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.Type: GrantFiled: February 15, 2007Date of Patent: September 11, 2007Assignee: Micron Technology, Inc.Inventors: Fred Fishburn, Forest Chen, John M. Drynan
-
Patent number: 7268040Abstract: Disclosed herein is a method of manufacturing a flash memory device.Type: GrantFiled: April 8, 2005Date of Patent: September 11, 2007Assignee: Hynix Semiconductor Inc.Inventor: Keon Soo Shim
-
Patent number: 7268041Abstract: The present invention relates to a method of forming a source contact of a flash memory device.Type: GrantFiled: May 27, 2005Date of Patent: September 11, 2007Assignee: Hynix Semiconductor Inc.Inventor: Tae Kyung Kim
-
Patent number: 7268042Abstract: A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.Type: GrantFiled: December 7, 2004Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Kan Yasui
-
Patent number: 7268043Abstract: A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.Type: GrantFiled: November 30, 2006Date of Patent: September 11, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Nak-Jin Son, Ji-Young Kim
-
Patent number: 7268044Abstract: Under one aspect, a field effect device includes a gate, a source, and a drain, with a conductive channel between the source and the drain; and a nanotube switch having a corresponding control terminal, said nanotube switch being positioned to control electrical conduction through said conductive channel. Under another aspect, a field effect device includes a gate having a corresponding gate terminal; a source having a corresponding source terminal; a drain having a corresponding drain terminal; a control terminal; and a nanotube switching element positioned between one of the gate, source, and drain and its corresponding terminal and switchable, in response to electrical stimuli at the control terminal and at least one of the gate, source, and drain terminals, between a first non-volatile state that enables current flow between the source and the drain and a second non-volatile state that disables current flow between the source and the drain.Type: GrantFiled: October 2, 2006Date of Patent: September 11, 2007Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal, Bernhard Vogeli, Darren K. Brock, Venkatachalam C. Jaiprakash
-
Patent number: 7268045Abstract: An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.Type: GrantFiled: July 12, 2005Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, Taylor R. Efland
-
Patent number: 7268046Abstract: A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.Type: GrantFiled: December 3, 2004Date of Patent: September 11, 2007Assignee: Koninklijke Philips Electronics N.V.Inventors: Theodore J. Letavic, Mark R. Simpson
-
Patent number: 7268047Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.Type: GrantFiled: February 21, 2006Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
-
Patent number: 7268048Abstract: Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation.Type: GrantFiled: August 6, 2004Date of Patent: September 11, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yin-Min Felicia Goh, Simon Chooi, Teck Wee Lim, Vincent Sih, Chian Yuh Sin, Ping Yu Ee, Zainab Ismail, Cher Sian Chua
-
Patent number: 7268049Abstract: The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.Type: GrantFiled: September 30, 2004Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Huilong Zhu, Effendi Leobandung, Anda C. Mocuta, Dan M. Mocuta
-
Patent number: 7268050Abstract: A method for fabricating a MOS transistor in a semiconductor device is disclosed. An example method subjects a surface of a semiconductor substrate to thermal oxidation to form an oxide film for forming a gate insulating film, deposits a polysilicon layer on the oxide film for forming a gate, applies a coat of photoresist onto the polysilicon layer, and performs exposure and development by using an exposure mask which defines the gate to form a photoresist pattern covering a region where the gate is to be formed. The example method also performs dry etching to remove the polysilicon layer for forming the gate and the oxide film for forming the gate insulating film, which are not protected with the photoresist pattern, to form a gate pattern, performs annealing under a nitrogen environment to form a nitrided oxide film, and forms buried lightly doped impurity ion layers on opposite sides of the gate pattern.Type: GrantFiled: December 28, 2004Date of Patent: September 11, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Min Ho Jeong
-
Patent number: 7268051Abstract: Methods and apparatus provide for: a silicon on insulator structure, comprising: a glass substrate; a layer of semiconductor material; and a deposited barrier layer of between about 60 nm to about 600 nm disposed between the glass substrate and the semiconductor material, where the glass substrate and semiconductor material are bonded together via electrolysis.Type: GrantFiled: August 26, 2005Date of Patent: September 11, 2007Assignee: Corning IncorporatedInventors: James Gregory Couillard, Kishor Purushottam Gadkaree
-
Patent number: 7268052Abstract: In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.Type: GrantFiled: September 8, 2004Date of Patent: September 11, 2007Assignee: Cypress Semiconductor CorporationInventors: Yanzhong Xu, Oliver Pohland
-
Patent number: 7268053Abstract: A semiconductor wafer includes (a) a first principal side and a second principal side opposite to each other, (b) a first bevel contour and a second bevel contour provided at an outer periphery of the first principal side and the second principal side, (c) a first recess formed in the first bevel contour, and (d) a first type of ID mark configured by a protruding dot provided on a bottom face of the first recess.Type: GrantFiled: March 11, 2005Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masao Iwase, Soichi Nadahara