Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A method of fabricating a semiconductor device is provided. Before covering the isolation structures with a conductive layer, a material layer is formed on the isolation structures. The fluid-like material layer allows the material layer formed between the isolation structures to be thicker than that formed on the top of the isolation structures. The isolation structures are then effectively etched back. The material layer at the top of the isolation structures is removed and a portion of isolation structures is also removed to lower the height of the isolation structures.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is removal of a portion of the oxide with an etch. A third step is an oxide deposition under a pressure of less than or equal to 10 mTorr. Methodology of the present invention can be utilized for forming trenched isolation regions, such as, for example, shallow trench isolation regions.

Abstract: Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

Abstract: A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least temporarily secure the semiconductor device component and the other element to each other. The pressure-sensitive component of the adhesive material temporarily secures the semiconductor device component and the other element to one another. When the semiconductor device component and the other element are properly aligned, the curable component of the adhesive material may be cured to more permanently secure them to one another. For example, when a thermoset material is used as the curable component, it may be cured by heating, such as at a temperature of lower than about 200° C. and as low as about 120° C. or less.

Abstract: A method for fabricating a substrate containing a useful semiconductor layer on a support having high resistivity by: preparing a base substrate of a semiconductor material containing a controlled quantity of interstitial oxygen, heat treating the base substrate to achieve at least partial precipitation of the interstitial oxygen therein, removing a superficial layer over a controlled depth from a surface of the base substrate that intended to receive a useful layer, forming the useful layer on the surface of the base substrate, with the base substrate serving as a support for the useful layer. This method is applicable in particular to SOI substrates having high resistivity for use in forming high frequency electronic circuits.

Abstract: A method for attaching a substrate such as a semiconductor wafer in which cracking or chipping can be prevented when the substrate is thinned involves applying adhesive liquid onto a circuit (element)-formed surface of a semiconductor wafer. The adhesive liquid undergoes preliminary drying, so that its flowability is reduced and it can keep its shape as an adhesive layer. For the preliminary drying, heating is conducted for 5 minutes at a temperature of 80° C. by using an oven. The thickness of the adhesive layer is determined based on the irregularities of the circuit which has been formed on the surface of the semiconductor wafer. Next, a supporting plate is attached to the semiconductor wafer on which the adhesive layer of a desired thickness has been formed.

Abstract: There is provided an optical system for reducing faint interference observed when laser annealing is performed to a semiconductor film. The faint interference conventionally observed can be reduced by irradiating the semiconductor film with a laser beam by the use of an optical system using a mirror of the present invention. The optical system for transforming the shape of the laser beam on an irradiation surface into a linear or rectangular shape is used. The optical system may include an optical system serving to convert the laser beam into a parallel light with respect to a traveling direction of the laser beam. When the laser beam having passed through the optical system is irradiated to the semiconductor film through the mirror of the present invention, the conventionally observed faint interference can be reduced. Besides, the optical system which has been difficult to adjust can be simplified.

Abstract: A process is disclosed for in-situ fabricating a semiconductor component imbedded in a substrate. A substrate is ablated with a first laser beam to form a void therein. A first conductive element is formed in the void of the substrate with a second laser beam. A semiconductor material is deposited upon the first conductive element with a third laser beam operating in the presence of a depositing atmosphere. A second conductive element is formed on the first semiconductor material with a fourth laser beam. The process may be used for fabricating a Schottky barrier diode or a junction field effect transistor and the like.

Abstract: Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Accordingly, the interfacial properties of the polysilicon film can be improved. It is thus possible to improve an operating characteristic of a device by prohibiting concentration of an electric field at the portion.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: A method of fabricating a semiconductor device includes forming a lower wiring layer on a semiconductor substrate, forming an interlayer insulating film on the lower wiring layer, layer, forming a plurality of. contact plugs in the interlayer insulating film so that the contact plugs are brought into electrical contact with the lower wiring layer, thereby forming an interlayer wiring layer, forming an upper wiring, layer on the interlayer wiring layer so that the upper wiring layer is brought into electrical contact with the contact plugs, and patterning the upper wiring layer so that the upper wiring layer corresponds to the contact plugs. In the patterning, after the upper wiring layer has been etched, the exposed interlayer insulating film and the exposed contact plugs are etched.

Abstract: There is a grain phenomenon issue of rough sidewall for patterning. Thus, imprecise grain profiles would be observed. As the critical dimensions of integrated circuit microelectronics fabrication device have decreased, the effect of grain phenomenon have become more pronounced. A profile improvement method with a thermal-compressive material and a thermal-compressive process is provided to solve the grain phenomenon issue for baseline of 0.09 um generation and beyond. With this material, the profile can be improved no matter in top view or lateral view. Furthermore, there are 0.1 um IDOF improvement and better physical etching performance.

Abstract: A method and apparatus is provided for fabricating a dual damascene interconnection. The method begins by forming on a substrate a dielectric layer that includes an organosilicon material, forming a via photoresist pattern over the dielectric layer, and etching a via in the dielectric layer using the via photoresist pattern as an etch mask. The via photoresist pattern is removed and a trench photoresist pattern is formed over the dielectric layer. A trench, connected to the via, is etched in the dielectric layer using the trench photoresist pattern as an etch mask. The trench photoresist pattern is removed and carbon ions are implanted into exposed surfaces of the via and the trench. A barrier layer is formed that overlies the via and the trench. Finally, interconnections are completed by filling the trench and the via with copper.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer (30) is formed on an exposed surface (26a) of a copper structure (26) prior to performance of metrology operations (206), so as to inhibit corrosion of the copper structure (26). All or a portion of the corrosion protection layer (30) is then removed (214) in forming an opening in an overlying dielectric (44) in a subsequent interconnect layer.

Abstract: A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

Abstract: Embodiments of the present invention provide methods to reduce the copper line roughness for increased electrical conductivity in narrow interconnects having a width of less than 100 nm. These methods reduce the copper line roughness by first smoothing the surface on which the copper lines are formed by performing a short electrochemical etch of the surface. The electrical conductivity of the interconnects is increased by reducing the copper line roughness that in turn reduces the resistivity of the copper lines.

Abstract: Physical vapor deposition and re-sputtering of a barrier layer in an integrated circuit is performed by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into said vacuum chamber. A target-sputtering plasma is maintained at the target to produce a stream of principally neutral atoms flowing from the target toward the wafer for vapor deposition. A wafer-sputtering plasma is maintained near the wafer support pedestal to produce a stream of sputtering ions toward the wafer support pedestal for re-sputtering. The sputtering ions are accelerated across a plasma sheath at the wafer in a direction normal to a surface of the wafer to render the sputter etching highly selective for horizontal surfaces.

Abstract: A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.

Abstract: A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.

Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.

Abstract: A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the resist layer are stripped to expose a first layer. The first layer is etched to remove exposed portions of the first layer not covered by the negative of the contact and to expose a second layer. A pattern reversal is performed to cure exposed portions of the second layer not covered by the first layer.

Abstract: Techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices. In one implementation, a carrier wafer is fabricated to include a membrane on one side of the carrier wafer. The membrane on the carrier wafer is then bond to a surface of a different, device wafer by a plurality of joints. Next, the carrier wafer is etched away by a dry etching chemical to expose the membrane and to leave said membrane on the device wafer. Transfer of membranes with a wet etching process is also described.

Abstract: Disclosed is a method of selectively etching nitride in a chemical downstream etching process. The invention begins by placing a wafer having oxide regions and nitride regions in a chamber. Then, the invention performs a chemical downstream etching process using CH2F2 to etch and convert the nitride regions into surface mediated uniform reactive film (SMURF) regions comprising (NH4)2SiF6. This process then rinses the surface of the wafer with water to remove the surface mediated uniform reactive film regions from the wafer, leaving the oxide regions substantially unaffected. The chemical downstream etching process is considered selective because it etches the nitride regions at a higher rate than the oxide regions.

Abstract: A plasma etching apparatus includes: a chamber capable of reducing pressure; a substrate support provided inside the chamber to place a substrate; a first electrode which is arranged outside and in proximity to the chamber and to which high frequency power is applied to generate plasma of an etching gas in the chamber; and a second electrode comprising a plurality of separated electrodes which are arranged between the chamber and the first electrode and to each of which high frequency power is applied independently.

Abstract: A method of treating a substrate includes disposing the substrate in a processing chamber having a first chamber portion configured to define a plasma space and a second chamber portion configured to define a process space, introducing a first gas to the plasma space and introducing a second gas to the process space. A plasma is formed in the plasma space from the first gas using a plasma source coupled to the upper chamber portion, and a process chemistry for treating the substrate is formed in the process space by providing a grid positioned between the first chamber portion and the second chamber portion such that the plasma can diffuse from the plasma space to the process space.

Abstract: The present invention relates to a method for forming a storage node contact of a semiconductor device. The method includes the steps of: depositing sequentially a conductive layer, a nitride layer and a polysilicon layer on a substrate having an insulating structure and a conductive structure; etching selectively the polysilicon layer, the nitride layer and the conductive layer to form a plurality of conductive patterns with a stack structure of the conductive layer and a dual hard mask including the polysilicon layer and the nitride layer; forming an insulation layer along a profile containing the conductive patterns; and etching the insulation layer by using a line type photoresist pattern as an etch mask to form a contact hole exposing the conductive structure disposed between the neighboring conductive patterns.

Abstract: A method of reducing critical dimension is provided. A dielectric layer is formed on a substrate. Then, a patterned photoresist is formed on the dielectric layer to expose part of the dielectric layer, wherein the patterned photoresist has a first line width. An etching process is performed to remove the exposed dielectric layer by using the patterned photoresist as an etching mask, wherein the final line width of the dielectric layer is smaller than the first line width. The conditions of the etching process include an etching pressure at 80 torr to 400 torr, an etching gas that includes a fluorocarbon compound and oxygen, wherein the ratio of the fluorocarbon compound to the oxygen is large than 0 and less than 10. Consequently, the etching process can be stabilized to form a smooth sidewall for the gate and to provide a uniform critical dimension.

Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.

Abstract: One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed by a nitridation process that adds nitrogen to a semiconductor substrate.

Abstract: A method of forming a PE-TEOS layer of a semiconductor IC device provides uniformly thick PE-TEOS layers on a batch of wafers. First, a loading wafer cassette is prepared to provide the wafers to be processed. Next, a process atmosphere is pre-created in a processing chamber. Then the wafers are supplied in sequence into the chamber from the loading wafer cassette and the wafers are mounted on a heater table in the chamber. Next, the PE-TEOS layer is deposited on the wafers by spraying a process gas into the chamber through showerheads. Next, the wafers are discharged from the chamber. Once the chamber is cleared of wafers, the inside of the chamber is cleaned by supplying a cleaning gas into the chamber, and exciting the cleaning gas with RF power. Subsequently, more TEOS gas is supplied into the chamber through the showerheads without being excited by RF power to especially reduce the temperature of the showerheads and that prevailing inside the chamber.

Abstract: A method of manufacturing flash memory devices, comprises the steps of forming an oxide film on a semiconductor substrate, performing a pre-annealing process under N2 gas atmosphere, nitrifying the oxide film by performing a main annealing process under N2O atmosphere having the flow rate of 5 to 15 slm for 10 to 60 minutes, thus forming an oxynitride film, and performing a post-annealing process under N2 gas atmosphere.

Abstract: A fiber mat of improved wet web strength and a process of making same is disclosed. The fiber mat comprises fibers; a resinous fiber binder; and a vinylpyrrolidone/acrylic acid/lauryl methacrylate terpolymer.

Abstract: A composite part made from a sheet molding compound is disclosed as having improved characteristics over traditional sheet molding compound composite parts. The fibrous material is introduced as a veil layer adjacent a paste layer, the veil flows well during the molding process. The improved flow and surface characteristics of a composite part are attributed to the elongation of the veil during molding and to the improved filling capabilities.

Abstract: A glaze composition can be used to provide a glaze layer having excellent antifouling performance and visual beauty. The glaze composition contains a glaze forming material, which has a composition determined such that a baked product obtained by baking the glaze composition comprises 55.0 to 67.0 wt % of SiO2; 8.0 to 11.0 wt % of Al2O3; 2.0 to 8.0 wt % of SnO2; 15.0 to 21.0 wt % of a divalent metal oxide; and 4.0 to 6.0 wt % of a monovalent metal oxide, with respect to a total weight of the baked product. When a glaze layer is formed by use of this glaze composition, it resists contamination. Even when a dirt deposits on the glaze layer, the dirt can be easily removed from the glaze layer. In addition, the glaze composition can provide a beautiful semi-opaque glaze layer with luster and a reduction in pore generation amount.

Abstract: The present invention provides a method for preparing silica containing molecular sieves which may be mixed with an organic polymer to create a mixed matrix membrane. Further, this invention includes a method of making such a mixed matrix membrane and the membrane itself. A process for separating component gases from a mixture using the subject mixed matrix membrane is also described. The method for preparing silica containing molecular sieves comprises super water washing silica containing molecular sieves to produce water washed molecular sieves which are substantially free of surface remnants. Super water washing also ideally lowers the concentration of alkali metals in the molecular sieves.

Abstract: A compound of the formula Ia or Ib; where, in the formula Ia, E1 is O, S, Se, Te, NR, CR2, or PR; E2, E3 are each CR, N, or P; E4 is N, or P; E5 is OH, SH, NHR, OR?, SR?, or NRR?; E6 is NH, PH, NR?, or PR?; R5, R6 are each hydrogen or a linear, branched or cyclic alkyl radical or an aryl radical; R1, R2, R3, R4 are each hydrogen, a linear, branched or cyclic alkyl radical, an aryl radical, a halogen or a nitro group; R is hydrogen, a linear, branched or cyclic alkyl radical; R? is a linear, branched or cyclic alkyl radical; where at least one of the groups E5 and E6 contains a hydrogen atom; and in the formula Ib, the symbols E1, E4, E5, E6, R5, R6, R1, R2, R3, R4, R and R? are as defined in formula Ia; and E?2 and E?3 are each O, S, Se, Te, NR, CR2, or PR.

Abstract: Novel ?-diimine metal complexes, particularly iron complexes are disclosed. The ?-diimine metal complexes are produced by forming one of the ?-diimine metal complex imine bonds in the presence of a metal salt or an ?-acylimine metal complex. ?-diimine metal complexes having two different ?-diimine nitrogen groups may be produced. The ?-diimine metal complexes are useful for polymerizing or oligomerizing olefins.

Abstract: A desulfurizing agent comprising a silica-alumina carrier having an Si/Al mole ratio of 10 or less and nickel carried thereon; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a specific surface area of pores having a pore diameter of 3 nm or less of 100 m2/g or more; an Ni-Cu based desulfurizing agent comprising a carrier and, carried thereon, (A) nickel, (B) copper, and (C) an alkali metal or another metal; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a hydrogen adsorption capacity of 0.4 mmol/g or more; and methods for producing these nickel-based and nickel-copper-based desulfurizing agents. The above desulfurizing agents are capable of adsorbing and removing with good efficiency the sulfur contained in hydrocarbons derived from petroleum to a content of 0.2 wt. ppm or less and have a long service life.

Abstract: A thermally printable commercially functional cash register tape produced from a thin oriented, heat stabilized, thermoplastic film is described. This thermoplastic tape replaces the currently used paper cash register tape. It will accept printing, has sufficient machine direction stiffness and sufficiently reduced surface electrical charges to function in conventional commercial cash register printers. The thermoplastic tape is much thinner than the conventional paper tape so a roll of the plastic register tape contains about 4.7 times the paper length of a typical cash register roll.

Abstract: In the present invention, a superconducting (sc) ceramic filament is enclosed in a silver sheath which is sealed therearound by applying silver powder between the surfaces of said sheath, pressing the surfaces and powder into contact and then applying sufficient heat to fuse them together, which heat is below the melting point of the surfaces and powder and then sintering the so enclosed ceramic filament, which upon cooling, forms a superconductor.

Abstract: An under-balanced drilling fluid additive is disclosed which reduces reactive shale and/or clay swelling during under-balanced drilling operations, where the additive includes an effective amount of a choline salt. A method for under-balanced drilling is also disclosed including the step of circulating a drilling fluid including an effective amount of a choline salt to reduce reactive shale and/or clay swelling during under-balanced drilling operations.

Abstract: A liquid gel concentrate for forming a high viscosity treating fluid is provided which can be premixed and stored before being used. The concentrate is comprised of an aqueous formate solution, at least one hydratable polymer which yields viscosity upon hydration and optionally an inhibitor having the property of reversibly reacting with the hydratable polymer in a manner whereby the rate of hydration of the polymer is retarded. Upon the selective reversal of the hydration inhibiting reaction the polymer is hydrated and high viscosity yielded thereby. The concentrate can be diluted with water to hydrate the hydratable polymer and form a large volume of high viscosity treating fluid.

Abstract: Cooling lubricant (concentrate or solution) comprising a cooling lubricant base based on mineral and/or synthetic oil and preservative comprising (a) one or more 1- or 2-(C3 to C24 alkyl) glyceryl ethers.

Abstract: The invention relates to the use of esters of hydroxycarboxylic acids with alkoxylated fatty alcohols as solubilizers for perfume oils in water. These esters not only have a strong solubilizing effect on water-insoluble perfume oils, they are also capable of dispersing calcium ions.