Abstract: Embodiments include systems and methods of improving processing in a decoder in a multimedia transmission system. Multimedia data may include one or more of motion video, audio, still images, or any other suitable type of audio-visual data. One embodiment includes a system and method of parsing fixed and variable length codes from a bit-wise stream of multi-media data by maintaining and reading the data in a processor aligned (e.g., word aligned) way. Another embodiment includes a system and method of decoding variable length codes, particular as received from such a variable length code using multiple levels of decoding tables to speed up decoder table lookup.

Abstract: Disclosed is a method for generating codewords through a repetition having a number of repetitions by means of multiple code symbols generated by a mother code and included in a slot. The method including the steps of generating the code symbols through a channel coding for input information symbols, and mapping the code symbols so that copies generated by the repetition are located within a bit sequence in an order different from an order of the code symbols in a bit sequence before the repetition, and performing the repetition.

Abstract: A logic device for the transformation of the output of the RDC into series A-B pulses according to the present invention comprises: a chip with its two minimal bits (LSB-LSB-1) simulating as the clock source of A-B pulses, a signal-processing pin (BUSY) which output a TTL pulse wave as a control signal resource while LSB shifts from a low level to a high level and contrariwise, and a logic processing circuit as well as a buffer to output the displacement and velocity of a rotor in the form of A-B serial pulses.

Abstract: An amplitude-compensated digital-to-analog converter circuit and method of compensation. A unipolar digital-to-analog converter is provided, having a reference connection and a pair of differential, unipolar signal outputs. A sensing circuit senses the common mode component of the differential outputs and produces a common mode signal. A reference source produces a first reference signal, and a differential control amplifier compares the common mode signal to the first reference signal and applies a second reference signal applied to the reference connection of the digital-to-analog converter, thereby stabilizing the reference current for the digital-to-analog converter. The circuit includes a single signal output reference to ground and a multiple-pole low-pass filter.

Abstract: An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.

Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.

Abstract: A rapid response measurement is accomplished by providing to a programmable gain amplifier an input to be measured, providing to an analog to digital converter having a predetermined output rate, the output from the programmable gain amplifier, determining when the output is greater than full scale input range of the analog to digital converter in an interval shorter than the period of the predetermined output rate of the analog to digital converter and adjusting the gain of the programmable gain amplifier to reduce the output below the full scale of the analog to digital converter at a rate faster than the predetermined output rate of the ADC.

Abstract: Automatic gain control is provided in a sigma-delta analog-to-digital converter. The automatic gain control is entirely or partly provided by an amplifier and an attenuator within the sigma-delta analog-to-digital converter. The amplifier within the sigma-delta time continuous loop prior to quantization and an attenuator in the feedback prior to summation with incoming signals. Scaling within the sigma-delta analog-to-digital converter results in lower current requirements for automatic gain control without disturbing or minimizing disturbance of the stability of a sigma-delta topology. By providing at least part of the automatic gain within the analog-to-digital converter, the specifications or requirements of the LNA or baseband amplifiers may be reduced or limited.

Abstract: A DA converter comprises a high-pass filter that outputs a multibit digital signal with a predetermined frequency or lower thereof attenuated if a signal level of the input multibit digital signal is less than a predetermined threshold, the high-pass filter outputting the multibit digital signal without attenuation if the signal level is at the threshold or higher; a ?? modulator that performs ?? modulation of the signal output from the filter unit; a dynamic element matching circuit that divides the signal output from the ?? modulator to a plurality of signals; and a plurality of internal DA converters that convert the plurality of signals output from the dynamic element matching circuit to an analog signal.

Abstract: A display driver circuit may include, a shift register configured to shift a first clock signal to generate at least one second clock signal, a digital-to-analog conversion unit configured to convert digital gray-scale data to an analog gray-scale signal, a first sample/hold output circuit configured to sample/hold the analog gray-scale signal in response to the at least one second clock signal, and configured to provide the sampled/hold analog gray-scale signal to a plurality of first channels in response to a first latch enable signal, and a second sample/hold output circuit configured to sample/hold the analog gray-scale signal in response to the second clock signal, and configured to provide the sample/hold analog gray-scale signal to a plurality of second channels in response to a second latch enable signal.

Abstract: A digital-to-analog converter (DAC) compatible with CMOS technology and operable in low voltage applications. An input capacitor stores a charge sample according to a digital input signal and a previous output analog signal. An analog output circuit has a feedback capacitor to share the charge sample and accordingly generate a current output analog signal from an output node. The output node may be continually connected to the input capacitor through a pass resistor.

Abstract: In an A/D conversion device, each delay unit in a pulse delay circuit has inverters INV of m×n stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of i×n stages (i=1, 2, . . . , and m). Those delay lines DL1 to DLm output sampling clocks CK1 to CKm. Each of those inverters INV has a same characteristic. In the A/D conversion device, the delay time in each of the delay lines DL1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK1 to CKm of a different phase ?T with one another, namely whose phases are preciously shifted by ?T with one another.

Abstract: Reference network embodiments are disclosed that provide reference signals to, for example, switched-capacitor multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters (ADCs). These embodiments are configured to maintain accuracy of the levels of the reference signals in the presence of high speed charge-injection and charge-extraction currents which are presented by the MDACs.

Abstract: A car reversing radar sensor having a fine-tuning function includes a cylinder, a sensor module, a front cover, a packing block and a back cover. The sensor module is fitted in the cylinder and a sensing angle thereof can be adjusted. The packing block includes a push part a brake part, and a stick part. The packing block is mounted on the cylinder for securing the sensor module at a desired sensing position.

Abstract: For an angle-resolving antenna system, only two radar sensors are provided including separate transmitting and receiving antennas. The receiving antennas of the two radar sensors are switchable with reference to their main beam direction as well as to their beam width.

Abstract: A system and method for determining a position of a target within an acceptable tolerance using an iterative approach. A airborne or space-based measuring device is used to measure an estimated position of the target. The information from the measuring device is used in conjunction with either live captured or stored topography, or the like, information relating to the surface of the planet proximate the target to iteratively determine the actual position of the target.

Abstract: This monopulse processor provides target position information having an RMS error which is less than that of a conventional monopulse processor. A ?±j? vs. ? processor is modified to provide a position output signal equal to the smaller in absolute magnitude of the results obtained from the ?+j? vs. ? and the ??j? vs. ? processing. A conventional monopulse processor is modified to provide an output signal having a value equal to Re(?/?)/[1+|Im(?/?)|].

Abstract: An angular scan interval may be divided into one or more sweep sectors for display. Polar (r, ?) coordinates may be calculated for rectangular (x, y) coordinates at each pixel of a display interval by computing polar (r, ?) coordinates in an interval of 0 to ?/4 and by applying mapping equation sets. Bounds of a block of polar radar (, ?) coordinates that map to a given (x, y) coordinate may be computed. A mechanism to associate the bounds of the block in polar radar (, ?) coordinates and the rectangular (x, y) coordinates may be created. Bounds associated with the x-coordinate in a sweep sector may be calculated. A maximum of the x-coordinate bounds to xmax and a minimum to xmin may be assigned accordingly. Bounds associated with the y-coordinate in the sweep sector may be calculated for each x-coordinate. A maximum of the bounds of the y-coordinate to ymax and a minimum to ymin may be assigned accordingly.

Abstract: A method of correcting for beacon pointing errors is disclosed. A desired beacon value and a predicted measured beacon value are computed and used to generate the beacon correction. An antenna pattern calculator can be used to compute the predicted measured beacon value, and a beacon correction value generator can be used to compute the desired beacon value and to generate the beacon correction.

Abstract: A global navigation satellite system (GNSS) receiver system includes a processing unit; and one or more antenna units for receiving GNSS signals, each of the antenna units having a phase center; one or more inertial sensor units each positioned substantially adjacent the phase centers; and at least one communication channel between each antenna unit and the processing unit.

Abstract: A Moving Transmitter Correlation Interferometer Geo-Location (MT-CIGL) system is disclosed that permits locating both moving and stationary transmitters from moving DF equipment. A conjugate gradient based search routine is utilized which solves for the location of moving and stationary transmitters at the start of each measurement sequence and then solves for the velocity and direction of motion of the moving transmitter. This information is used to track the moving transmitter. Received signals are sampled, digitized and stored in covariance matrices. They are then summed and normalized using an equation that has velocity terms that are set to zero to minimize extraneous correlation peaks, and a maximum correlation peak is developed. A conjugate gradient search routine is used to find the correlation peak of the summed data. The value of the peak is then analyzed to see if it is above or below a predetermined value.

Abstract: A back-array, full-direction, circular polarization antenna is disclosed to include a power divider, which has two input contact holes and an output contact hole respectively electrically connected to an internal circuit thereof, and two patch antennas respectively symmetrically connected to two opposite sides of the power divider to produce two electric fields with a 90-degrees phase difference kept between the mechanical degrees and the electric degrees produced by each electric field, each patch antenna having a patch-like ceramic body, a radiation metal electrode printed on one side of the patch-like ceramic body, and a metal contact pin affixed to the radiation metal electrode and the patch-like ceramic body and connected to one input contact hole of the power divider.

Abstract: A small broadband monopole antenna having a perpendicular ground plane with an electromagnetically coupled feed is provided. The small broadband monopole antenna may be realized as a small antenna having a size of 0.085?0×0.085?0×0.085?0 by positioning a folded strip line under a shorted square disc. A resonance of the shorted square disc may be coupled to a resonance of the square folded strip line so as to form a wide bandwidth of about 36.6% of a central frequency of 2.313 GHz based on a VSWR?2. Also, rectangular slits may be inserted into the perpendicular ground plane to improve a distortion of a radiation pattern that forms on the perpendicular ground plane so as to reduce a backward radiation by 3 dBi or more. The small broadband monopole antenna exhibits a forward radiation pattern similar to that of a general monopole antenna and has a gain of about 2.6 dBi within a bandwidth.

Abstract: A folded monopole antenna that supports lower and upper frequency bands may be used in CDMA, WLAN, or other wireless communications systems. The folded monopole antenna may be located in a handset next to a vertical ground plane. The folded monopole antenna may be folded at least twice and connected to the ground plane through a reactance. The dimensions of different sections of the folded monopole antenna define lower and upper frequency band characteristics, and an offset location of an input feed affects the bandwidth of the frequency bands. The reactance between the antenna and ground plane can be selected to fine tune the frequency bands. Various input feeds, including a co-planar waveguide, may be employed. Dynamically adjustable reactances may be used in the input feed and ground line for adapting the antenna to various environments.

Abstract: The invention relates to a radar sensor (10) for use with automobiles. Said radar sensor emits pulsed radiation. The radar sensor is characterized in that it comprises an antenna with at least one layer-structured block (34) consisting of metal layers (36, 38, 40, 42) which are arranged according to the Yagi principle and which are respectively separated from each other by a dielectric intermediary layer (46, 48, 50). At least one of the metal layers (36, 38, 40, 42) is excited by a supply system (18) with a radar frequency.

Abstract: A high frequency and broad band glass antenna for automobiles has a strong directivity in one direction even if the antenna is provided near to the mental portion of a body. The antenna comprises an antenna line provided near to the metal portion of a body, one end of the antenna line neighboring the metal portion being fed; and a parasitic line positioned near to the antenna line for adjusting a directivity and a frequency characteristic of reception sensitivity of the glass antenna. The antenna line consists of a straight antenna line has the length (?/4)?. The parasitic line extends in parallel with the antenna line and consists of at least one straight conductor line having the length of (?/8)?. The length that the conductor line overlaps with the antenna line is (?/8)?. The distance between the conductor line and the antenna line is (?/64)?.

Abstract: Exemplary embodiments of mountable antenna apparatuses and methods are disclosed. In one exemplary embodiment, a mountable antenna apparatus generally includes a housing member, a bayonet adapter, and an antenna assembly disposed within the housing member. The housing member may include an aerodynamic configuration for reducing drag on and for eliminating or reducing fatigue as well as flutter of the antenna assembly. The aerodynamic configuration may include a feature such as an ogive, an ogivoid, a semi-ogivoid, a hemi-ogivoid, and a quasi-ogivoid.

Abstract: An antenna structure is composed of an antenna seat, a terminal, and an antenna set. The antenna set includes antennae, a matching circuit, conducting wires, and a lead wire. By the conducting wires and matching circuit connected on the antennae, an impedance matching can be achieved to be coupled with frequency of radio wave signal to be received for reducing a standing-wave ration, when the antenna are receiving the radio wave signal. In addition, the frequency and wavelength of radio wave signal received by the antennae can be adjusted by changing lengths of conducting wires.

Abstract: A small rectenna including a thin conductive layer formed on a surface of a dielectric substrate and a slot pattern arranged within the thin conductive layer. The small rectenna for an RFID transponder includes: a dielectric substrate; a thin conductive layer formed on a surface of the dielectric substrate; a slot pattern configured within the thin conductive layer so that the rectenna has an enhanced gain and a greater operating bandwidth; and an inlet of an electronic chip including an ASIC in the slot pattern.

Abstract: A high gain broadband planar antenna is provided for overcoming conventional antenna structure that cannot be applied to a high gain broadband. The antenna includes a microwave substrate having a first surface and a second surface, a first symmetric radiation unit having a first radiation part and a second radiation part disposed on the first surface, a second symmetric radiation unit having a third radiation part and a fourth radiation part disposed on the second surface, and at least one connecting unit connected to the microwave substrate and a reflector. An end terminal of each first radiation part, second radiation part, third radiation part and fourth radiation part adopts a step structure design. The planar antenna of the present invention can achieve a high gain broadband effect.

Abstract: An active antenna element to transmit and/or receive RF (Radio Frequency) signals is positioned in relation to a backplane that reflects RF signals. One or more passive antenna elements can be disposed on a similar side of the backplane as the active antenna element. Settings of the one or more passive antenna elements are adjusted to produce an input/output beam pattern that varies depending on whether the at least one passive antenna element is reflective or transmissive. Based on this technique, an RF input output beam pattern of an antenna assembly including the backplane, active antenna element and passive antenna elements can be controlled for better reception and transmission of RF signals.

Abstract: A second ground plane (18); has one end opposite to a connector (14), which end is connected to a first ground plane (17) by resistor connection element (41). Accordingly, it is possible to lower Q of resonance of the ground structure by the resistor connection element (41) and to prevent generation of an intense electromagnetic field attributed to an electromagnetic field of a data processing circuit. Especially when the resistor connection element (41) has a resistance value identical to a characteristic impedance of the ground structure, the ground structure is terminated in a matched way and it is possible to assure prevention of generation of an electromagnetic field attributed to resonance.

Abstract: A metalized circuit suitable for application as a radio frequency antenna is produced by forming an antenna coil pattern on a flexible substrate. The antenna coil pattern is formed using a conductive ink which is patterned on the substrate. The conductive ink is cured and an electrical-short layer is formed across the coils of the conductive ink pattern. An insulating layer is formed over top of the electrical-short layer, a metal layer electroplated on top of the conductive layer, and then the electrical-short layer is removed. The use of the electrical-short layer during the electroplating allows for the voltage at the different points on the conductive ink layer to be relatively similar, so that a uniform electroplate layer is formed on top of the conductive ink layer. This results in a better quality radio frequency antenna at a reduced cost.

Abstract: A single-element antenna system that provides a wide bandwidth and consistent polarization over the frequency range to which the antenna is impedance matched. In one embodiment, the wideband antenna system includes two parallel coupled sectorial loop antennas (CSLA) that are coupled along an axis of symmetry. In another embodiment, half of the coupled sectorial loop antenna is electrically coupled to a ground plane, where the antenna includes one pie-slice shaped sector and two arches. In alternate embodiments, sections of the sector can be removed to reduce the weight of the antenna system.

Abstract: An antenna arrangement including a first antenna module having a first antenna loop positioned in a plane for emitting a signal in a first spatial area, and at least one additional antenna loop positioned in substantially the same plane for emitting a signal in an additional spatial area. The arrangement includes at least one power source in communication with the first antenna module for providing current thereto. The first spatial area and the additional spatial area at least partially overlap, and the first antenna loop and the additional antenna loop are powered by the power source in a specified pattern. A method of identifying at least one item is also disclosed.

Abstract: An adjustable antenna bracket has an antenna bracket, a stanchion bracket, a connector panel and multiple fasteners. The antenna bracket has a fixed board with multiple circular assembled curved slots and the fixed board is combined with the antenna bracket. The stanchion bracket has a connecting board, two elevation boards and two adjusting boards. Each adjusted board has multiple adjusted slots. The connector panel is mounted on the antenna bracket at a side opposite to the stanchion bracket. The fasteners extend through the connector panel, the curved slots in the antenna disk and the adjusting slots in the adjusting boards to combine the connector panel, the antenna disk and the stanchion bracket together. Accordingly, an adjustable antenna bracket with two rotation stages is provided.

Abstract: A phased array antenna apparatus has a plurality of circuit portions which are each coupled to a respective antenna element. Capillary pressure of a cooling fluid within a wick in a loop is utilized to urge the fluid to travel around the loop, the wick being disposed in the region of the circuitry. In a variation, there are plural wicks in respective evaporators, and cooling fluid is distributed among the evaporators through a series of T-junctions. In another variation, cooling fluid is distributed to a plurality of evaporators in a sequence corresponding to a progressive increase in the respective amounts of heat accepted by the evaporators from structure being cooled.

Abstract: A quadri-filar helical antenna structure includes a cylindrical body having a relative dielectric constant greater than 4, and four radial metal plates on a distal end of the cylindrical body, and each radial metal plate is extended along the cylindrical body. The ends of every two adjacent radial metal plates are connected to form two antenna structures, and a circuit board is fixed. A ground surface is installed on one side of the circuit board and coupled to one of the antennas. An impedance matching circuit is installed on another side of the circuit board, and one end of the impedance matching circuit is coupled to another antenna. A feeder is installed at another end of the impedance matching circuit. Four radial metal plates having an electric length about odd multiples of a quarter of wavelength of the cylindrical body can receive satellite signals.

Abstract: A display 1 has two display panels 2, 3 each including an active matrix substrates 7, 8 including: source bus lines 4, 5 and gate bus lines 9 arranged to form a matrix; TFTs provided near respective intersections of the source bus lines 4, 5 and the gate bus lines 9; and pixel electrodes electrically connected to the source bus lines and the gate bus lines through the TFT. Of the source bus lines 4, 5, the source bus lines 5 are shared for use between the two active matrix substrates 7, 8. Meanwhile, the source bus lines 4 provided only to the active matrix substrate 7 have capacitances 6a, 6b formed thereon. Thus, the display with two display panels is prevented from developing block split and other display defects.

Abstract: A mobile phone is electronics with 2D and 3D display function, having a first casing and a second casing linked to allow the phone to be foldable, and including a first display unit located inside with the phone folded, and selectively switching and displaying 2D and 3D images, and a second display unit located outside with the phone folded, and displaying a 2D image. When the mobile phone is opened or open the first display unit displays an idle screen in a 3D image as desired.

Abstract: A cathode ray tube (CRT) device increases image resolution using spatial or temporal techniques. The CRT device includes a plurality of electron guns that each produce an electron beam and a plurality of separate phosphor dots, each corresponding to one of a plurality of primary colors. Certain ones of the phosphor dots form a color spot of a single primary color when impacted by an electron beam. The CRT device also includes steering electronics coupled to the plurality of electron guns to guide the electron beams to project on the phosphor dots to form a plurality of color spots each indicating a different one of the primary colors. The steering electronics direct the electron beams to separate and shift the color spots indicating the different primary colors from one another. In one embodiment, a subpixel clock is coupled to the steering electronics to effect subpixel rendering on the CRT device.

Abstract: A method for controlling electrodes in a plasma display panel (815), includes applying a voltage Ve to a sustain electrode during a setting up of the sustain electrode (710) for an addressing operation, where Ve2<Ve. Another method includes a) applying Ve2 to the sustain electrode during the addressing, where the sustain electrode is associated with a scan electrode (714) in an electrode pair, and b) applying a voltage Vs1 to the scan electrode during a discharging of the electrode pair after the addressing, where Ve2<Vs1.

Abstract: This invention discloses an arrangement for suppressing an erroneous display and suppressing damage to an image display apparatus when a power source is turned on, the power source is turned off, an outlet is removed, or power fails. Particularly, this invention discloses an arrangement for stopping, for a predetermined time, input of a scanning signal or modulation signal to a display panel or application of an accelerating potential in turning on the power source. This invention discloses an arrangement for stopping input of a scanning signal or modulation signal to the display panel, and then stopping supply of power in turning off the power source.

Abstract: A scanning wiring driving unit for generating a signal of a frequency Fb applies a scanning signal to a plurality of scanning wirings which are a part of a plurality of scanning wirings. In a next selection period following a predetermined selection period, by shifting by a portion of the scanning wiring to which the scanning signal was applied in a previous stage, a scanning signal is applied to a plurality of scanning wirings. Further, in any one of the selection periods, a scanning signal is applied to a plurality of scanning wirings simultaneously, and n pieces of scanning wirings are sequentially scanned by use of a frequency of n X Fb and below.

Abstract: Provided are an image brightness controlling apparatus and method, and an adaptive brightness controlling apparatus and method based on the brightness degree and/or brightness range of an image. The image brightness controlling apparatus includes a brightness increment arithmetic unit for outputting a brightness increment for a pixel, and an individual component brightness increment arithmetic unit for outputting the brightness increments of individual components constituting the pixel in response to the brightness increment for a pixel. The individual component brightness increment arithmetic unit multiplies the brightness increment of the pixel by each of the unit vectors of the components constituting the pixel to obtain the brightness increments of the individual components. The image brightness controlling apparatus further includes an adder for adding the components constituting the pixel to the brightness increments of the components.

Abstract: A pixel testing method is provided. The pixel testing method is adapted to measure device parameters within each pixel of a display. Before plating a lighting device into each pixel, a capacitor is formed such that one end of the capacitor is connected to an open-circuit terminal of an electronic device while the other end of the capacitor is connected to an added common line (or the original scan line or data line of the display). The parameters of the electronic device connected to the lighting device are tested through a charging/discharging of the capacitor so that all the devices within a pixel can be tested before forming organic functional layer in every pixel.

Abstract: An architecture for a smart liquid crystal display (LCD) panel interface is described. The architecture enables a circuit to transfer only updated display data to the interface. When there are no display data updates to transfer, the circuit is placed in the lowest power state to reduce power consumption while the interface displays information locally stored.

Abstract: A liquid crystal display device having analog buffer circuits, which is reduced in luminance fluctuation is provided. A source signal line driver circuit has a plurality of analog buffer circuits, the plurality of source signal lines and the plurality of analog buffer circuits constitute a circuit group, and source signal lines connected to the analog buffer circuits are switched their connections to different analog buffer circuits each time a new period is started. Therefore, output fluctuation among the analog buffer circuits is averaged and a uniform image can be displayed on the screen.

Abstract: A color Liquid Crystal Display (LCD) device for displaying a color image using at least four different primary colors, the device including an array of Liquid Crystal (LC) elements (214), driving circuitry (218) adapted to receive an input corresponding to the color image and to selectively activate the LC elements (214) of the LC array to produce an attenuation pattern corresponding to a gray-level representation of the color image, and an array of color sub-pixel filter elements (216) juxtaposed and in registry with the array of LC elements (214) such that each color sub-pixel filter element is in registry with one of the LC elements, wherein the array of color sub-pixel filter elements comprises at least four types of color sub-pixel filter elements, which transmit light of the at least four primary colors, respectively.

Abstract: A display and a method for manufacturing said display is disclosed wherein said display is comprised of at least a first set of subpixels and a second set of subpixels—said first set of subpixels comprising smaller area than said second subpixels. The thin film transistors that drive said first set of subpixels are formed substantially in the area of said second set of subpixels.