Abstract: The method for predicting seismic events includes supplying electricity by means of a detection unit (3) fitted with current electrodes (A, B) and potential probes (M, N) arranged in the ground and detecting electrical current and induced potentials by means of said electrodes (A, B) and said reception probes (M, N), for the calculation of resistivity in the ground. The resistivity data recorded is acquired and stored and then transferred to a means of analysis and processing (11). Finally, resistive drops in relation to preset values, corresponding to the approach of seismic events are evaluated.

Abstract: A tester for testing a circuit breaker includes a plurality of load elements each having a nominal fixed impedance and an electronic switch associated with each load element. The electronic switch, when turned on, electrically connects a corresponding load element in series with a circuit breaker load terminal and in parallel with none or with a number of other load elements. A controller turns on a number of the electronic switches selected to draw through a corresponding number of the load elements a test current selected as a function of a designated rated current for the circuit breaker and sufficient to trip open the same. A pulse width modulation circuit cooperates with the controller and with the electronic switches. The pulse width modulation circuit provides a constant magnitude of the test current to accommodate variations of the nominal fixed impedance or variations of the voltage of the load terminal.

Abstract: An apparatus for testing the life of a leakage current protection device having a leakage current detection circuit. In one embodiment, the apparatus a trip mechanism state generator, a fault alarm generator, a ground fault simulation unit. In operation, the ground fault simulation unit generates a simulated ground fault signal during every positive half-wave of an AC power, the simulated ground fault signal is detected by the leakage current detection circuit, the leakage current detection circuit responsively generates a signal to turn a switching device into its conductive state so as to allow a current to pass therethrough, the passed current is converted into a DC voltage in accordance with a trip mechanism state generated by the trip mechanism state generator, the fault alarm circuit receives and analyzes the DC voltage and indicates whether a fault exists in the leakage current protection device.

Abstract: A wideband device modeling method comprises using ultra-short time-domain impulse responses measurement and using a subsequent extraction of said ultra-short time-domain impulse responses measurement. The wideband device modeling method in the invention is to provide a model that could faithfully describe an ultra-short TD response and would conform to the wideband consideration. An ultra-short impulse with tens of pico-second width has been used in this work for characterizing the TD responses of the devices. Moreover, the wideband device modeling method in the invention is to provide a layer peeling technique, widely used in characterizing PCB interconnection or package, is mixed with a conventional spiral inductor physical model. The wideband device modeling method in the invention also provides an extension equivalent circuit combined with the BSIM3v3 model.

Abstract: An apparatus for detection of a USB host or a USB OTG device being attached to Vbus connector terminal of a USB device includes an attach detection pull down resistor isolated from the Vbus connector terminal. This attach detection feature guarantees USB attach detection and complies with current limits of both USB 1.1 and USB 2.0 OTG specifications.

Abstract: Detectable pipe and electric fence are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 50% of the weight of the conductive loaded resin-based material. The micron conductive powders are metals or conductive non-metals or metal plated non-metals. The micron conductive fibers may be metal fiber or metal plated fiber. Further, the metal plated fiber may be formed by plating metal onto a metal fiber or by plating metal onto a non-metal fiber. Any platable fiber may be used as the core for a non-metal fiber. Superconductor metals may also be used as micron conductive fibers and/or as metal plating onto fibers in the present invention.

Abstract: An apparatus for measuring spin polarization via Point Contact Andreev Reflection (PCAR) at a magnet-superconductor junction, with variable magnetic fields and temperature control. A cryostat probe investigates superconducting energy gap and Andreev reflection in superconductor-half metal junctions, in a wide range of magnetic fields and temperature from 2K-300K. The cryostat probe is integrated with a commercial physical properties measurement system. The measurement probe includes a rotary-translation stage with coarse and fine screws that enable a user to make point contacts in a cryogenic, evacuated environment where the point contact junction can be controlled at room temperature by turning a knob. Copper wires are connected as electrical leads from an aluminum housing, descend down to a copper housing, for measurement, when contact is made by tip with a half-metal sample, such as CrO2.

Abstract: In an apparatus for measuring a specific absorption rate (SAR), a first near magnetic field distribution of a radio wave radiated from an array antenna of a reference antenna including a plurality of minute antennas is measured, and an SAR distribution with respect to the radio wave radiated from the array antenna is measured with a predetermined phantom. Then a distribution of a transformation coefficient ? is calculated by dividing the measured SAR distribution by a square of the measured first near magnetic field distribution, a second near magnetic field distribution of a radio wave radiated from a measured radio communication apparatus is measured, and an SAR distribution with respect to the radio wave radiated from the radio communication apparatus is calculated by multiplying a square of the measured second near magnetic field distribution by the calculated distribution of the transformation coefficient ?.

Abstract: A system for detecting a rail break or train occupancy includes a current source adapted to deliver a current to an isolated block of a rail track. A voltage sensor is coupled to the isolated block and configured to detect voltage across the isolated block. A shunt device is coupled to the isolated block and configured to receive a shunt current from the current delivered by the current source. A shunt current sensor is coupled to the shunt device and adapted to detect the shunt current flowing through the shunt device. A control unit is adapted to receive input from the voltage sensor and the shunt current sensor and to monitor a variation of the shunt current with respect to the voltage to detect the rail break or train occupancy.

Abstract: A sensor circuit is provided that includes at least one pair of interconnected T-networks. Each pair has a first T-network including a first impedance serially connected to second impedance at a first junction and a first variable resistance sensor element connected to the first junction. Each pair also has a second T-network including a third impedance serially connected to a fourth impedance at a second junction and a second variable resistance sensor element connected to the second junction. The sensor circuit further includes an operational amplifier connected to the first T-network of a selected one of the at least one pair of T-networks and a constant voltage source connected to the second T-network of the selected T-network pair.

Abstract: An improved test probe assembly has an improved mounting assembly which provides the test probe multi-directional freedom of movement with respect to a base in order to resist damage frequently caused to the test probe. The improved mounting assembly may, for example, include at least a first resilient mount disposed on the base and having at least a first support and at least a first resilient element. The at least a first resilient element, which may, for example, be at least a first spring, is deflectable when the test probe engages a structure, such as a device under testing (DUT). Accordingly, the improved test probe assembly of the invention can be deflected an infinite number of positions, in order to resist damage caused, for example, by misalignment between the probe and the DUT.

Abstract: The invention aims to provide a vertical type probe card in which a probe can scrape an oxide film on a surface of an electrode of the measurement object, thereby ensuring stable contact with the electrode of the measurement object.

Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.

Abstract: An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

Abstract: A method and apparatus is provided for characterizing a contactor for automated semiconductor device testing, the method first comprising placing the contactor on a contactor test board positioned within an automated test apparatus. A first probe of the automated test apparatus is contacted to a conductive layer of the contactor test board, and a second probe is placed on a contactor pin of the contactor, wherein the contactor pin is operable to linearly translate within the contactor. A predetermined pressure is applied to the contactor pin via the second probe, wherein the contactor pin is translated toward the contactor test board. An electrical characteristic of the contactor pin is measured between the first probe and the second probe and compared to a desired electrical characteristic, wherein a condition of the contactor pin is determined, based on the comparison of the measured electrical characteristic and the desired electrical characteristic.

Abstract: An apparatus for generating a current source test stimulus signal having a constant current regardless of an internal impedance value of a device under test includes a voltage source generation unit and a voltage to current (V/I) converter. The voltage source generation unit converts source data stored in internal memory into analog signals, and combines the analog signals and a reference signal of D/C voltage level to generate voltage source test stimulus signals. The V/I converter converts the voltage source test stimulus signals into current source test stimulus signals and outputs the current source test stimulus signal to a device under test. The V/I converter maintains the current levels of the current source test stimulus signals at a predetermined value, regardless of the internal impedance of input pins of the device under test. In this manner, the operating efficiency of the device under test can be accurately determined.

Abstract: Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces are disclosed. An apparatus in accordance with one embodiment includes a first support member configured to releasably carry a microfeature workpiece, a second support member positioned proximate to the first support member and configured to carry an electrical testing device, wherein at least one of the first and second support members is movable toward and away from the other. The apparatus can further include a signal source (e.g., radiation source) positioned proximate to the support member, and a signal sensor (e.g., a radiation sensor) positioned at least proximate to the first support member and the signal source. The signal sensor can be configured to received at least a portion of the signal directed by the signal source and passing proximate to the first support member.

Abstract: A method includes measuring a gate leakage current of at least one transistor. A single stress bias voltage is applied to the at least one transistor at a given temperature for a stress period t. The stress bias voltage causes a 10% degradation in a drive current of the transistor at the given temperature within the stress period t. A negative bias temperature instability (NBTI) lifetime ? of the transistor is estimated based on the measured gate leakage current and a relationship between drive current degradation and time observed during the applying step.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).

Abstract: Providing a transmission circuit, which can transfer data normally with high speed even toward a host controller and a device, which does not meet design requirements defined in the standard, a data-transfer control device and electronic equipment. A current source coupled between a first source VDD and a node ND10; a first transistor SW1 formed between the node ND10 and a DP terminal; a second transistor SW2 formed between the node ND10 and a DM terminal; a first buffers outputting a first control signal HS_DPout 2 to the gate of the first transistor SW1; and a second buffer outputting a second control signal HS_DMout 2 to the gate of the second transistor SW2; are included. When any of the first control signal HS_DPout2 and the second control signal HS_Dmout 2 is set active, other of the control signals is set non-active. Each of the buffers includes a first inverter INV1 and a second inverter INV receiving an output from the first inverter INV1.

Abstract: A semiconductor integrated circuit includes at least one pad coupled to at least one bus line, the at least one pad having a first side, a second side, a third side, and a fourth side; a transmitter for transmitting a signal from an internal circuit externally via the at least one pad; and a termination circuit for terminating the at least one bus line. Either one of the transmitter and the termination circuit is disposed to face the first and second sides of the at least one pad and the other of the transmitter and the termination circuit is disposed to either one of the third and fourth sides of the at least one pad.

Abstract: A three-dimensional semiconductor device, comprising: a programmable logic circuit constructed in a first module layer, said logic circuit input to output responses configurable to a user specification by configuring a plurality of control signals, each control signal received at a regulatory node in the logic circuit; and a configuration circuit constructed in a second module layer, said configuration circuit further comprising: a plurality of memory elements, each memory element having either one or two outputs, each memory element capable of storing one of two binary data values, each output coupled to one of said control signals, each control signal having either the same polarity of the stored memory bit or the opposite polarity of the stored memory bit; and a memory programming method to access each of said memory elements to alter the stored data value between said two binary data values to configure the control signals; wherein, the second module layer is positioned substantially above the first modul

Abstract: A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

Abstract: An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

Abstract: A reconfigurable integrated circuit device, in which an arbitrary operating state is constructed based on configuration data, has a reconfigurable circuit unit, having a plurality of reconfigurable processor elements and a processor element network to connect the processor elements in an arbitrary state, and a reconfiguration control portion, which supplies configuration data to the processor elements and processor element network, to construct an arbitrary state in the reconfigurable circuit unit. In response to an external reset cancellation signal at the time power is turned on, at least a portion of the reconfigurable circuit unit is configured in a state of an initialization circuit, and in response to an internal reset cancellation circuit after completion of operation of the initialization circuit, the configuration control portion starts supplying the configuration data.

Abstract: A PLD having logic blocks capable of performing addition with a constant and non-constant value where the constant value is provided directly to an adder, without first passing it through a look up table. The PLD includes a plurality of logic blocks arranged in a two dimensional array. Row and column interconnects are provided to interconnect the plurality of logic blocks arranged in the two dimensional array. The plurality of logic blocks each include a look up table configurable to perform combinational logic and an adder circuit configured to perform adding functions. Each logic block also includes circuitry configured to directly provide a constant value to the adder circuit without passing the constant value through the look up table. The look up table is therefore available to perform other logic functions that would otherwise have to performed elsewhere on the chip.

Abstract: An aggregation interconnect scheme for a programmable logic device provides low-skew routing of high fan-out signals by aggregating regional routing resources, which provide low-skew routing utilizing under-utilized global routing resources.

Abstract: Some embodiments provide a first interconnect circuit for accessing stored data in a reconfigurable IC. The reconfigurable IC has at least one reconfigurable circuit and a set of storage elements for storing several data sets for the particular reconfigurable circuit. The first interconnect circuit includes second, third, and fourth interconnect circuits, where the fourth interconnect circuit connects to outputs of the second and third interconnect circuits. The second and third interconnect circuits connect to the storage element sets to provide data sets to the fourth interconnect circuit, which, in turn, provides the received data to the particular reconfigurable circuit. The fourth interconnect circuit operates at a different rate than the second and third interconnect circuits. In some embodiments, the stored data sets are configuration data sets for configuring the articular reconfigurable circuit.

Abstract: A programmable logic block provides N-bit and M-bit (e.g., (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Abstract: A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.

Abstract: An input/output buffer that protects a circuit from voltage signals provided from an external device. The input/output buffer includes a reference power generation circuit connected to a high voltage power supply and a low voltage power supply to convert the voltage of an external voltage signal and generate reference power. The reference power generation circuit has a protection circuit including a plurality of MOS transistors for decreasing the voltage of the external voltage signal to a predetermined voltage when the input/output buffer is not supplied with the voltage of the high voltage power supply. Each of the MOS transistors has a back gate connected to a predetermined node at which the voltage is less than the voltage of the high voltage power supply and greater than the voltage of the low voltage power supply.

Abstract: A circuit for providing an output current is provided. The circuit includes a differential amplifier, a transistor having a gate that is coupled to the output of the differential amplifier, a comparator, and a sense resistor that is coupled between the drain of the transistor and the input pin. One input of the differential amplifier is connected to the input pin and the other input is connected to a reference voltage. The inputs of the comparator are coupled across the sense resistor. If an external resistor is coupled to the input pin, the comparator trips. If the comparator is tripped, the current from the external resistor is mirrored to provide the output current. If the comparator is not tripped, the output current is provided from an on-chip current source.

Abstract: An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.

Abstract: A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current.

Abstract: A semiconductor device for driving a load includes a first semiconductor switching element interposed between a power supply terminal and a load, a second semiconductor switching element interposed between the load and a ground terminal, a high-side driver, a low-side driver, and a voltage regulator. The voltage regulator reduces a voltage applied to a control terminal of the second switching element, when a voltage of a load terminal of the second switching element is lower than a predetermined voltage. Then, a voltage applied between the load terminal and the ground terminal of the second switching element increases, and accordingly a voltage applied between the power supply terminal and the load terminal of the first switching element decreases.

Abstract: A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The feedback signals are then received and compared. Based on the comparisons, the skew between the output signals is adjusted.

Abstract: A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector (216) and a glitch detector (208) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.

Abstract: A semiconductor device for correcting a duty of a clock signal includes a first clock buffer for receiving an external clock signal through a non-inverting terminal of the first clock buffer and for receiving an external clock bar signal through an inverting terminal of the first clock buffer to thereby output a first clock input signal; a second clock buffer for receiving the external clock bar signal through the non-inverting terminal of the first clock buffer and for receiving the external clock signal through the inverting terminal of the first clock buffer to thereby output a second clock input signal; and a delay locked loop (DLL) for receiving the first clock input signal and the second clock input signal to thereby generate a duty corrected clock signal.

Abstract: A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting recovery of information from the plurality of lines is adjusted according to the transitions detected. Examples of such a signal include one or more signals carried on one or more of the plurality of lines and a timing signal carried on a line separate from the plurality of lines.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: A comparator includes a differential amplifier, and a hysteresis circuit. The differential amplifier amplifies a difference signal corresponding to a difference between input signals. The hysteresis circuit sets up a first transition threshold voltage and a second transition threshold voltage where the second transition threshold is different from the first transition threshold voltage. The hysteresis circuit generates a second signal that makes transition at the first transition threshold voltage when the difference signal changes in a first direction, and makes transition at the second transition threshold voltage when the difference signal changes in a second.

Abstract: A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmissions of the signal through the plurality of data paths. The delay circuit may additionally generate a plurality of signals based on the staggered transmissions. Each of the plurality of data paths in the delay circuit may comprise at least one of an inverter, a logic gate, a flip-flop, a latch, a register, or a resistor-capacitor (RC) delay element.

Abstract: An electronic signal processing apparatus has a signal switch with a first and a second transistor of normally-on type, having main current channels coupled between an internal node and a switch input and output, respectively. A diode provides a switchable signal coupling between the internal node and ground. A switch control circuit has a control output that is DC coupled to the main current channel of the first and the second transistor via the internal node to control conduction of the main current channels. The diode is also DC-coupled to the internal node so that a DC potential of a terminal of the diode that controls whether the diode is on or off is determined by a potential of the internal node. The diode is preferably incorporated in the DC current path from the control output to the internal node, so that the diode is forward-biased when a control voltage that makes the main current channels non-conductive is applied.

Abstract: An integrating capacitor circuit for an integrating amplifier and related methods are disclosed that allow for efficient detection of currents or charges, particularly those produced by pixel cells in a detector image array. By placing a capacitor-connected field-effect-transistor (FET) in parallel with an integration capacitor and setting its gate voltage to a selected voltage level, the current or charge from the detector depletes the charge on the gate of the FET capacitor while integrating on the capacitor. In addition, the gate voltage level can be adjusted to modify the current depleting characteristics of the capacitor-connected FET. The resulting operation of this integrating circuitry provides significant resulting advantages for the integrating amplifier.