Abstract: An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (ANx), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less than 1.0, and a second layer adhered to the first layer, the second layer including a nitride (ANy), where y is greater than or equal to 1.0. The multiple layer electrode allows the first layer to better adhere to chalcogenide based memory material, such as GST, than for example, stoichiometric TiN or WN, which prevents delamination. A phase change memory device and method are also disclosed.

Abstract: The invention refers to a memory, a method of fabricating an electrical structure, and an electrical structure containing a substrate, a solid state electrolyte layer, and an electrode layer. The electrical structure contains a layer region arranged at an interface between the solid state electrolyte layer and the electrode layer. The layer region has a higher oxygen concentration than the solid state electrolyte layer and the electrode layer.

Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current carriers: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.

Abstract: A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.

Abstract: A quantum dot semiconductor device securing sufficient gains without depending on polarization and a manufacturing method thereof. On a first barrier layer, a multilayer quantum dot is formed by repeatedly stacking alternately a quantum dot layer and a second barrier layer. On a quantum dot layer as an uppermost layer of the quantum dot, a third barrier layer which keeps local strains in the quantum dot layer is formed. On the third barrier layer, a fourth barrier layer which compensates compressive strains from the second barrier layer is formed. Therefore, the fourth barrier layer made of tensile strain materials compensates accumulation of compressive strains caused by stacking of a multilayer quantum dot layer. The third barrier layer prevents tensile strains in the fourth barrier layer from directly impacting on the quantum dot layer, so that local strains can be effectively cancelled. Thus, the above-described semiconductor device can be realized.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: The present invention relates to a pentathienyl-fluorene copolymer having structural units represented by formula (I): here R and R? are each independently a substituent or H. The invention also relates to a transistor containing this copolymer. The present invention addresses a problem in the art by providing an electroactive device with exceptionally low hysteresis.

Abstract: A photoelectric current caused by extraneous light is suppressed and variations in characteristics (for example, a threshold voltage) of a thin film transistor are reduced. An active layer (semiconductor layer) made of polycrystalline silicon, which is transformed from amorphous silicon by laser annealing, is formed on an insulating substrate. A drain region 2d and a source region 2s, which are facing to each other, are formed in the active layer. Each of the drain region 2d and the source region 2s is formed of an n? layer and an n+ layer adjacent to each other. A p-type channel region 2c is formed between the n? layer in the drain region 2d and the n? layer in the source region 2s. A light-shielding layer 3d is formed to cover only a boundary region between the n? layer in the drain region 2d and the channel region 2c to shield the boundary region from extraneous light incident upon the boundary region through the insulating substrate.

Abstract: The present invention provides a nitride semiconductor single crystal including gallium nitride (GaN) or aluminum nitride (AlN) which are formed as a film to have good crystallinity without forming a 3C—SiC layer on a Si substrate, and which can be used suitably for a light emitting diode, a laser light emitting element, an electronic element that can be operated at a high speed and a high temperature, etc., as well as a high frequency device. A GaN (0001) or AlN (0001) single crystal film, or a super-lattice structure of GaN (0001) and AlN (0001) is formed on a Si (110) substrate via a 2H—AlN buffer layer.

Abstract: A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.

Abstract: The invention relates to a test structure and methods of detecting electrical defects between adjacent metal contacts using such test structure at the first metal level within a semiconductor device. The test structure includes dual first metal level comb structures each having extending lines that are in direct electrical communication with contacts residing in the semiconductor. The extending lines of the first metal comb are interlaced with extending lines on the second metal comb such that adjacent metal contacts are in electrical communication with different metal combs. In this manner, upon testing for electrical continuity, an electrical current passing from the first metal comb to the second metal comb indicates an electrical defect existing between adjacent metal contacts.

Abstract: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline layer located immediately underneath the amorphous layer and in the lower portion of the intermediate structure. The method may also include bonding a receiving substrate on the upper face of the intermediate structure and removing the layer of the intermediate structure in which point defects have formed so that amorphous layer forms the upper layer of the intermediate structure. A structure made by such a method may comprise at least one thin layer of an amorphous material on a supporting substrate. The structure may comprise a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any EOR type point defect.

Abstract: An image display medium includes: a first substrate; a second substrate facing the first substrate; a first bonding layer provided inside at least one of the first substrate and the second substrate; and an insulating layer fixed to the at least one of the first substrate and the second substrate by the first bonding layer, wherein the first bonding layer has a Young's modulus smaller than the substrate formed with the insulating layer and the insulating layer.

Abstract: The display device according to an exemplary embodiment of the present invention includes an insulation substrate, a first signal line formed on the insulation substrate, a second signal line intersecting and insulated from the first signal line, an covering member formed on the second signal line, and a switching element having a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the first signal line and the second terminal is connected to the second signal line, and a pixel electrode is connected to the third terminal of the switching element. The covering member according to an embodiment of the present invention reduces the etching error in forming a fine pattern.

Abstract: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

Abstract: In conventional techniques, there has been a problem such that a pattern failure tends to occur in which electrode patterns formed by coating do not coincide with lyophilic patterns and the coating process is complicated to degrade the productivity. The present invention provides a thin film transistor substrate including: a substrate; a plurality of gate electrodes formed on a flat surface of the substrate so as to form an array constituted with ring-shaped flat patterns formed by continuously connecting the outer peripheries of a plurality of ellipses aligned along the major axis direction, or patterns each formed with the peripheral shape of an ellipse; a gate insulating film formed over the gate electrodes; and source electrodes and drain electrodes formed on the gate insulating film exclusive of the flat surface regions, on the gate insulating film, defined as the projected shapes of the gate electrodes.

Abstract: Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.

Abstract: A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

Abstract: A semiconductor device according to the invention for emitting light when a voltage is applied includes a first (3), a second (5) and a third active semiconductor region (7A-7C). While the conductivity of the first semiconductor region (3) is based on charge carriers of a first conductivity type, the conductivity of the second semiconductor region (5) is based on charge carriers of a second conductivity type, which have a charge opposite to the charge carriers of the first conductivity type The active semiconductor region (5 13) is arranged between the first and the second semiconductor regions (3, 5). Embedded in the active semiconductor region (5) are quantum structures (13) which are made from a semiconductor material which has a direct band gap. In that respect the term quantum structures is used to denote structures which in at least one direction of extent are of a dimension which is so small that the properties of the structure are substantially also determined by quantum-mechanical processes.

Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.

Abstract: A high power light emitting device assembly with electro-static-discharge (ESD) protection ability and the method of manufacturing the same, the assembly comprising: at least two sub-mounts, respectively being electrically connected to an anode electrode and a cathode electrode, each being made of a metal of high electric conductivity and high thermal conductivity; a light emitting device, arranged on the sub-mounts; and an ESD protection die, sandwiched and glued between the sub-mounts, for enabling the high-power operating light emitting device to have good heat dissipating path while preventing the same to be damaged by transient power overload of static surge.

Abstract: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer or the substrate. The non-rectifying conduction means may include a degenerate junction structure or a patterned metal layer.

Abstract: Embodiments of a light emitting device are provided. A light emitting device can include a first electrode, a first condition type semiconductor layer, an active layer, a second conduction type semiconductor layer, a second electrode, and a substrate. The first conduction type semiconductor layer can be formed on the first electrode. The active layer can be formed on the first conduction type semiconductor layer. The second conduction type semiconductor layer can be formed on the active layer. The second electrode can be formed on the second conduction type semiconductor layer. The substrate is on the lateral sides of the first conduction type semiconductor layer, the active layer, and the second conduction type semiconductor layer.

Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.

Abstract: An edge light-emitting device having, on a light permeable substrate, a stacked structure including a pair of electrodes and at least one light emitting layer interposed between the electrodes, in which light emission is taken-out from a light emitting edge of the stacked structure, wherein at least one non-light emitting edge other than the light emitting edge for taking out the light emission, an angle formed by the non-light emitting edge relative to a surface of the substrate supporting the stacked structure or a surface opposed to the surface of the substrate supporting the stacked structure is an acute angle, and the non-light emitting edge has a light reflection layer. An edge light-emitting device excellent in production feasibility and a manufacturing method thereof are provided.

Abstract: It is an object of the present invention to provide a light emitting element that realizes a high contrast. It is another object of the present invention to provide a light emitting device that realizes a high contrast by using the light emitting element with an excellent contrast. The light emitting element has a layer containing a light emitting substance interposed between a first electrode and a second electrode, and the layer containing the light emitting substance includes a light emitting layer, a layer containing a first organic compound, and a layer containing a second organic compound. The first electrode has a light-transmitting property, and the layer containing the first organic compound and the layer containing the second organic compound are interposed between the second electrode and the light emitting layer. Furthermore, color of the first organic compound and color of the second organic compound are complementary.

Abstract: A method of forming an electroluminescent device including the steps of providing a substrate including a first electrode for injection of charge carriers of a first type, forming a semiconductor region by depositing over the substrate a composition containing a first material for transporting charge carriers of the first type and a second material for emission and transporting charge carriers of the first type, and depositing over the semiconducting region a second electrode for injection of charge carriers of a second type.

Abstract: A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80nm and at most 1000nm. Here, the thickness of the first coat film is preferably at least 6nm and at most 200nm.

Abstract: A lead frame and a light emitting device package using the same are disclosed. More particularly, a lead frame and a light emitting device package using the lead frame which can be easily manufactured and employ a multi-chip structure. The light emitting device package includes a first frame including a heat sink, a second frame coupled to an upper side of the first frame, the second frame including at least one pair of leads and a mount formed with a hole, and a molded structure for coupling the first and second frames to each other.

Abstract: A phosphor nitride or a chalcogenide phosphor, which is used as a red phosphor, includes a wavelength of green light as an exciting wavelength. Therefore, in obtaining white light by using a conversion member in which a red phosphor and a green phosphor both exist, luminance efficiency is deteriorated as a result. In view of this, a lighting device according to the present invention is structured such that a film applied with two kinds of phosphors is provided in an optical path of blue light or ultraviolet LED, the two kinds of phosphor including a phosphor for converting blue light or violet light into green light through excitation thereof and a phosphor for converting blue light or violet light into red light through excitation thereof, the phosphors being provided in layers different from each other.

Abstract: Aiming at providing a method of fabricating a light emitting device having an AlGaInP light emitting section, less causative of crack by cleavage, on the edge portions on the back surface of the device chip in process of dicing or breaking, a light emitting device wafer is diced along a dicing line inclined at an angle of 15° to 30°, both ends inclusive, away from a dicing line angle reference direction defined as the <110> direction on the (100) main surface.

Abstract: A monolithically integrated light-activated thyristor in an n-p-n-p-n-p sequence consists of a four-layered thyristor structure and an embedded back-biased PN junction structure as a turn-off switching diode. The turn-off switching diode is formed through structured doping processes and/or depositions on a single semiconductor wafer so that it is integrated monolithically without any external device or semiconductor materials. The thyristor can be switching on and off optically by two discrete light beams illuminated on separated openings of electrodes on the top surface of a semiconductor body. The carrier injection of the turning on process is achieved by illuminating the bulk of the thyristor with a high level light through the first aperture over the cathode to create high density charge carriers serving as the gate current injection and to electrically short the emitter and drift layer.

Abstract: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.

Abstract: A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

Abstract: A guard ring applied to an ion implantation equipment is disposed between a bushing and an ion beam source housing of the ion implantation equipment. The guard ring is made of high-density ceramic material. The guard ring can prevent arcing generated by the high voltage used for ion implantation from causing unpredicted damage to the bushing, thereby effectively protecting the ion implantation equipment, increasing the lifetime of use of the ion implantation equipment, and lengthening the maintenance cycle.

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.

Abstract: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.

Abstract: Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or maximizing a production yield. The method comprises: after first removing a first hard mask layer used to form a contact pad electrically connected to a semiconductor substrate, forming a lower electrode to be electrically connected to the contact pad through a first contact hole in a first interlayer insulating layer formed on the contact pad and to have a thickness equal or similar to a thickness of the first interlayer insulating layer; and forming a phase change layer and an upper electrode on the lower electrode.

Abstract: A GaN semiconductor device which has a low on-resistance, has a very small leak current when a reverse bias voltage is applied and is very excellent in withstand voltage characteristic, said GaN semiconductor device having a structure being provided with a III-V nitride semiconductor layer containing at least one hetero junction structure of III-V nitride semiconductors having different band gap energies; a first anode electrode arranged on a surface of said III-V nitride semiconductor by Schottky junction; a second anode electrode which is arranged on the surface of said III-V nitride semiconductor layer by Schottky junction, is electrically connected with said first anode electrode and forms a higher Schottky barrier than a Schottky barrier formed by said first anode electrode; and an insulating protection film which is brought into contact with said second anode electrode and is arranged on the surface of said III-V nitride semiconductor layer.

Abstract: A semiconductor device, wherein: a first fabricating option provides a plurality of user configurations to configure the device functionality; and a second fabricating option hard-wires a said functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to the first option.

Abstract: A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BPSG film 4, and a process of forming contact holes 8 through the BPSG film 4 and the dielectric film 5 so as to reach the semiconductor substrate 1, in a case in which gate electrodes are densely formed in some areas and sparsely formed in other areas. The above-described contact hole formation method allows a thickness of the BPSG film 4 to be uniform irrespective of the density of the gate electrodes, whereby an etching rate becomes uniform over the entire area of the semiconductor device. Thus, it is possible to form contact holes having minimized variations in a contact resistance and a value of leakage current.

Abstract: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract: In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the gate, the diffusion region, and the other diffusion region. The trench may be filled with a metal to form electrical connections. The trench may be formed in a dielectric layer using a self-aligned etch step, for example.

Abstract: A GaAs power transistor unit cell is provided with one of its transistor contacts on its bottom surface, and its other two transistor contacts on its frontside surface. In one arrangement, the GaAs power transistor unit cell has a N+ GaAs substrate that cooperates with an N? GaAs material to form a transistor collector. A collector contact is on a bottom surface of the collector, and a transistor base is provided on the collector. An emitter is arranged on the base. Accordingly, the collector contact is on the bottom of the unit cell, while a base contact and emitter contact are oriented to the frontside of the unit cell. It will be understood that the emitter and collector portions may be exchanged in other constructions. In use, the GaAs transistor unit cells are interconnected to form a GaAs power transistor, with the power transistor having externally available contacts. In one specific construction, a connection pad is provided on a laminate substrate.

Abstract: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.

Abstract: An active pixel sensor and method of operating an active pixel sensor comprising an N well of n type silicon formed in a p type silicon substrate and a P well of p type silicon is formed in the N well. A deep N well is formed of n type silicon underneath the P well. The edges of the deep N well contact the bottom of the N well forming an overlap region which can either be not depleted of charge carriers thereby electrically connecting the N well to the deep N well or depleted of charge carriers thereby electrically isolating the N well from the deep N well. N regions formed in the P well and P regions formed in the N well are used to reset the pixel and to read the pixel after a charge integration period. An array of P wells formed within N wells can be used to form an array of active pixel sensors. In this array an overlap region is formed between each N well and the deep N well.

Abstract: In a CCD type solid-state image sensor (CCD) of this invention, a potential gradient is provided in which potentials about electric signals gradually change from a photodiode toward a gate electrode. Specifically, impurities forming the photodiode are diffused in the shape of character “X”, and the width of the impurities is enlarged gradually from the photodiode toward the gate electrode. With such a gradient, the electric signals are smoothly transferred along the potential gradient, without the electric signals stagnating in movement from the photodiode to the gate electrode. As a result, the electric signals can be transferred at high speed from the photodiode to the gate electrode.

Abstract: It is an object of the present invention to obtain a photoelectric conversion device having a favorable spectral sensitivity characteristic and no variation in output current without such a contamination substance mixed into a photoelectric conversion layer or a transistor. Further, it is another object of the present invention to obtain a highly reliable semiconductor device in a semiconductor device having such a photoelectric conversion device.

Abstract: A solid-state image sensor prevents shading while maintaining the wider dynamic range of an image signal without reducing its optical resolution. The image sensor has plural pairs of higher- and lower-sensitivity photodiodes and micro-lenses each of which is provided over particular one of the higher- and lower-sensitivity photodiodes for collecting the light incident on corresponding one of the higher- and lower-sensitivity photodiodes. The micro-lenses provided over the lower-sensitivity photodiodes have the curvature thereof smaller than that of the other micro-lenses, thereby providing for the lower-sensitivity photodiode a significant amount of light even for a change of the exit pupil position or incident angle or the like that causes the position of an image circle to shift.