Abstract: A photoelectric conversion device (10) includes a first conductivity type first semiconductor region (10a) located in a pixel region (11), a second conductivity type second semiconductor region (12) provided in the first semiconductor region (10a), for storing a signal charge, interconnecting portions (13 and 14) for connecting the second semiconductor region (12) with a circuit element provided outside the pixel region (11), and an organic film (16) which is provided above a portion located in the pixel region (11) in the interconnecting portions (13 and 14) through an insulating protective film (15) and held at a predetermined potential. The organic film (16) is made of a thermoplastic polyimide resin containing one of a conductive particle and a conductive fiber.

Abstract: Provided is a photoelectric conversion device including: a semiconductor substrate (3) of a first conductivity type; a photoelectric conversion region (7) of a second conductivity type which is located in the semiconductor substrate (3), the second conductivity type being opposite to the first conductivity type; and a buried layer (17) of the first conductivity type which is formed in an inner portion of the semiconductor substrate (3) to cover a lower side of the photoelectric conversion region (7), the buried layer (17) including a higher impurity concentration than the semiconductor substrate (3).

Abstract: A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to a vertical signal line, and an FD wire. The FD wire is provided in a first wiring line, and the vertical signal line is provided in a second wiring line positioned over the first wiring layer. Since the potential of the FD wire follows the potential of the vertical signal line, it is possible to suppress a variation in capacitance occurring in the FD when a position of the vertical signal is shifted, depending on a position of the cell.

Abstract: A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.

Abstract: In an optical unit including a photoelectric conversion chip adapted to be optically connected to an optical fiber, and a semiconductor chip for driving the photoelectric conversion chip, both the photoelectric conversion chip and the semiconductor chip are wrapped with a flexible sheet, to thereby produce an enveloper enveloping the photoelectric conversion chip and the semiconductor chip therein. At least a part of the enveloper is formed as a transparent area for allowing an optical connection between the optical fiber and the photoelectric conversion chip.

Abstract: A trench type junction barrier rectifier has silicon dioxide spacers at the bottom of trenches in a silicon surface and beneath the bottom of a conductive polysilicon filler in the trench. A Schottky barrier electrode is connected to the tops of the mesas and the tops of the polysilicon fillers. Further oxide spacers may be formed in the length of the polysilicon fillers.

Abstract: A varactor including a substrate, a P well disposed in the substrate, a gate structure disposed over the substrate, a p+ source disposed in the substrate at one side of the gate structure, a p+ drain disposed in the substrate at the other side of the gate structure, and a deep N well disposed in the substrate under the P well is provided. The gate oxide of the varactor is thicker so as to reduce the probability of the current leakage occurrence.

Abstract: A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench.

Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

Abstract: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.

Abstract: A semiconductor device includes a first interlayer insulating film, a second interlayer insulating film formed on the first interlayer insulating film, a plug having a lower portion surrounded by the first interlayer insulating film and an upper portion projecting from the first interlayer insulating film and surrounded by the second interlayer insulating film, a wire formed in the second interlayer insulating film, and having a connected portion that is connected to the plug and a non-connected portion that is not connected to the plug, and a stopper insulating film formed in a region between the first interlayer insulating film and the non-connected portion of the wire and between the second interlayer insulating film and the upper portion of the plug.

Abstract: A laser ablated wafer for a semiconductor device, such as a MOSFET or other power device, and a method of producing such a wafer to achieve a lower electrical resistance are provided. The method includes forming first holes, slots or trenches on a first surface of the wafer and focusing a laser beam to form second trenches on a bottom surface of the wafer, and filling the trenches, for example using aluminum or other metallic filling, to provide conductive electrodes or conductive surfaces for the semiconductor device. In such a wafer each trench on the second surface may be deeper, for example hundreds of microns deep and tens of microns wide.

Abstract: It is an object of the present invention to provide an integrated circuit device structured to uniformly apply a voltage to side oxide films formed in a trench at both sides in an SOI substrate. The semiconductor integrated circuit device of the present invention comprises a substrate which supports a first insulation layer below an active device region, trench formed in the active device region to come into contact with the first insulation layer, second insulation film formed on the trench side wall, polycrystalline silicon with which the trench is filled, and third insulation film formed on the polycrystalline silicon, wherein the thickness ratio of the third insulation film to the first insulation film is 0.25 or more to uniformly apply a voltage to the oxide insulation films formed in the trench at both sides.

Abstract: A semiconductor device having improved capacitance may include a semiconductor substrate, a gate electrode on the semiconductor substrate, a capacitor lower electrode formed of substantially the same material as the gate electrode and being in the same layer as the gate electrode, an interlayer insulating film that covers the gate electrode and capacitor lower electrode, the interlayer insulating film including an opening through which the top surface of the capacitor lower electrode may be exposed, a capacitor upper electrode that fills the opening, and a dielectric film between the capacitor lower electrode and capacitor upper electrode.

Abstract: A semiconductor component has a drift path (4) in a semiconductor body (5) of a semiconductor chip (6). The semiconductor component has an edge area (7) and a cell area (8), which is surrounded by the edge area (7). A trench structure (9), which surrounds the semiconductor component (6) in the edge area (7), is arranged in the edge area (7) of the semiconductor component (6). At least the trench walls (10) are covered by an insulation material (11). The trench structure (9) which surrounds the semiconductor component (6) has overlapping trench zones (12) with semiconductor material (13) arranged between them.

Abstract: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

Abstract: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a ?-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

Abstract: Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

Abstract: Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: The invention is directed to an anti-fuse comprised of a substrate, a gate electrode, and a gate dielectric layer. The gate electrode is located on the substrate. The gate dielectric layer is placed between the gate electrode and the substrate. The method of programming the anti-fuse is accomplished by applying a bias voltage to between the gate electrode and the substrate to break down the gate dielectric layer and convert the resistance between the gate electrode and the substrate to be smaller than that before the breakdown of the gate dielectric layer happens. By using the anti-fuse, area occupied by the anti-fuse in the chip is decreased and the programming of the anti-fuse can be done after the chip is packed.

Abstract: A capacitor structure has a plurality of stacked conductive patterns, and each conductive pattern has a closed conductive ring, a plurality of major conductive bars arranged in parallel and electrically to the closed conductive ring, and a plurality of minor conductive bars arranged alternately with the major conductive bars and not electrically connected to the closed conductive ring. The major conductive bars and the minor conductive bars of an odd layer conductive pattern are respectively corresponding to the minor conductive bars and the major conductive bars of an even layer conductive pattern.

Abstract: Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.

Abstract: A memory includes a semiconductor layer provided on an insulation film provided on a first conductivity type substrate; a first well of a second conductivity type provided in the substrate; second wells of the first conductivity type provided in the first well; a third well of a second conductivity type provided in the substrate; a memory cell including a first source, a first drain and a body region, the first source and drain being formed in the semiconductor layer located above one of the second wells; a first logic circuit including a second source, a second drain and a channel region, the second source and drain being formed on the semiconductor layer above another one of the second wells; and a second logic circuit including a third source, a third drain and a channel region, the third source and drain being formed on the semiconductor layer above the third well.

Abstract: An electrostatic discharge protection device of a semiconductor integrated circuit, comprising a first diffusion layer that is a diffusion layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type and serves as a collector, a second diffusion layer that is a diffusion layer of the first conductivity type provided in the first diffusion layer and serves as a base, a third diffusion layer that is a diffusion layer of the second conductivity type provided in the second diffusion layer and serves as an emitter, a collector contact region provided in the first diffusion layer, a fourth diffusion layer that is a diffusion layer of the second conductivity type provided in the first diffusion layer in a downward region of the collector contact region in a substrate-thickness direction, wherein the fourth diffusion layer is formed shallower in a depth than that of the first diffusion layer in the substrate-thickness direction, deeper in a depth than that of the second diffu

Abstract: A plastic substrate is provided, on which is disposed a sacrificial polymer layer and a thin metal film over the sacrificial polymer layer. The thin metal film is laser-delamination patterned. The sacrificial polymer layer is at least partially removed via laser delamination where the thin metal film has been removed via laser delamination.

Abstract: The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.

Abstract: A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated.

Abstract: An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with a protruding section, a semiconductor chip formed on the protruding section of the supporting board, a dielectric layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on the dielectric layer. The circuit layer is electrically connected to electrode pads of the semiconductor chip via a plurality of conducting structures formed inside the dielectric layer such that the semiconductor chip can be electrically connected to an external element through the circuit layer. By varying the thicknesses of the protruding section, the dielectric layer and the supporting board, warpage of the package structure resulted from temperature change during the fabrication process can be prevented.

Abstract: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.

Abstract: An integrated circuit package system is provided providing a first structure, forming a compression via in the first structure, forming a stud bump on a second structure and pressing the stud bump into the compression via forming a mechanical bond.

Abstract: A semiconductor system (100) enabled by an interposer (101) with non-reflow metal studs (251), preferably gold, coated with reflow metals (252), preferably solder. The studs are on exit ports (220, 230, etc) of the interposer surface; selected exit ports may be spaced apart by less than 125 ?m center to center. A first electrical device (102), such as one or more semiconductor chips with contact pads matching the locations of the interposer exit ports, contacts the studs on one interposer surface. A second electrical device (104), such as a semiconductor chip, a passive component, or both, is attached to the other interposer surface. A carrier (106) supports the first device and provides electrical connections (109) to external parts.

Abstract: Methods and apparatus are provided for an electronic panel assembly (EPA) (82, 83), comprising: providing one or more electronic devices (30) with primary faces (31) having electrical contacts (36), opposed rear faces (33) and edges (32) therebetween. The devices (30) are mounted primary faces (31) down on a temporary support (60) in openings (44) in a warp control sheet (WCS) (40) attached to the support (60). Plastic encapsulation (50) is formed at least between lateral edges (32, 43) of the devices (30) and WCS openings (44). Undesirable panel warping (76) during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. After encapsulation cure, the EPA (82) containing the devices (30) and the WCS (40) is separated from the temporary support (60) and, optionally, mounted on another carrier (70) with electrical contacts (36) exposed.

Abstract: Embodiments of the present invention provide a die stack including a first substrate, a first die bonded to the first substrate, a second substrate having a cavity sized and shaped to fit over the first die, and a second die bonded to at least a portion of a rim of the cavity.

Abstract: A package structure with embedded electronic devices is provided. The package structure includes a substrate, a multi-layered circuit board, an adhesive film and at least an electronic device. The electronic device is disposed on the substrate. The electronic device is press-adhered to the multi-layered circuit board through the adhesive film and the composite bump thereon, so that the electronic device is embedded within the package structure and between the substrate and the circuit board. Due to the deformity of the composite bump, the electronic device is protected from being cracking in the pressing process.

Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.

Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or purifier material is deposited on the base by a variety of techniques and a layer for temporary protection of the purification material is placed on top of the purification material. The temporary protection material is compatible for use in the microdevice and can be removed during the manufacture of the microdevice.

Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.

Abstract: The invention provides an integrated device comprising a plurality of non-individually-encapsulated chip arrangements, each of which having a plurality of contact elements for contacting a contact pad, wherein the plurality of chip arrangements are stacked on each other such that the respective contact elements provide electrical connections to the respective chip arrangement, and a common integral mold arranged to encapsulate the plurality of stacked chip arrangements.

Abstract: The structure of stacked integrated circuits includes a substrate having an upper surface formed with first electrodes, and a lower surface formed with second electrodes. A lower integrated circuit is formed with bonding pads, and is located on the upper surface of the substrate. First adhered glue is coated on the periphery of the lower integrated circuit to form a plurality of points having same height. Second adhered glue is coated on the lower integrated circuit, and is located on the periphery of the first adhered glue. An upper integrated circuit has bonding pads, and is arranged on the lower integrated circuit, and is supported and is adhered by the first adhered glue and the second adhered glue. A plurality of wirings are electrically connected the bonding pads of the lower integrated circuit and the upper integrated circuit to the first electrodes of the substrate. And a compound layer is encapsulated on the upper integrated circuit and the lower integrated circuit.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.

Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.

Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: Microelectronic device assemblies, including assemblies with recurved leadframes, and associated methods are disclosed. An assembly in accordance with one embodiment includes a microelectronic device having a first surface, a second surface facing opposite from the first surface, and a plurality of bond sites accessible from the first surface. An operable microelectronic feature can be located between the first and second surfaces. The assembly can further include a leadframe positioned proximate to the microelectronic device, with the leadframe having a plurality of conductive leadfingers, each being electrically coupled to a corresponding bond site of the microelectronic device, and extending around the microelectronic device to face toward the second surface. This arrangement can be used to support single microelectronic devices, and/or stacked microelectronic devices.

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Abstract: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: The invention relates to a power semiconductor module comprising a plurality of power semiconductors that are fixed to a first side of a printed circuit board (26), and a cooling device that acts by means of a coolant, on a second side of the printed circuit board (26), opposite the first side, the cooling device comprising a plurality of cells through which the coolant is guided. The aim of the invention is to minimise the risk of failure of one such power semiconductor module. To this end, a non-cooled region (d, e, f is arranged between at least two cells.