Abstract: Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Abstract: A method and system for exposing the delicate structures of a device encapsulated in a mold compound such as an integrated circuit (IC). A laser is used to ablate the mold compound and thus remove it, exposing the underlying structure. The laser beam can be steered in a desired raster pattern onto the surface of the device or the device can be moved in the desired pattern relative to the laser beam. Spectral analysis can be performed on the laser plume emitted by the ablation process in order to determine the composition of the ablated material. Thus, in addition to exposing defects in the underlying structure, the system can also be used to analyze the encapsulating material in order to determine whether it contained any defects or anomalies. A system for precisely cutting a circuit board or an IC in a user-selected pattern is also described. The system directs a laser along a path that a user can specify using a graphical interface.

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: A probe card is formed of a main board and a sub-board located above the principal surface of the main board. The sub-board is located inside of an internal circumferential pad region of the main board. Relays are arranged in a line along the external circumference of the upper surface of the sub-board. Electrical components, such as the relays, a capacitor, a crystal-controlled oscillator, and an IC, are selected from components which are reduced in size as much as possible. The circuit for inspection is formed of the electrical components provided over the sub-board and the wiring layers within the sub-board. As a result, the yield of the probe card can be improved.

Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: Methods and apparatus for testing a semiconductor device are disclosed. A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging, assembly qualification, and the like. A first set of pads is configured in a predetermined pattern on the bottom surface of a flexible substrate. Similarly, a second set of pads is configured in substantially the same pattern on the top surface of the flexible substrate, wherein each of the pads in the second set of pads is electrically continuous with a corresponding pad in the first set of pads. A third set of pads is configured in the same pad pattern on the top surface of the flexible substrate. One or more conductive traces are formed to connect one or more pads in the first set of pads with spatially-corresponding pads in the third set of pads.

Abstract: An electroluminescent display device includes first and second substrates facing each other, data and gate lines crossing each other on the first substrate to define a plurality of pixel regions, a switching transistor connected to the gate and data lines, a driving transistor connected to the switching transistor, a dummy pattern on the first substrate, a connection electrode on the dummy pattern and connected to the driving transistor, a power line connected to the driving transistor, and an emitting diode on the second substrate and connected to the connection electrode.

Abstract: A semiconductor die package having an elastomeric substrate with a first support frame and a second support frame. The first support frame has a cavity within which a semiconductor die is placed. The second support frame may have an optional cavity. The optional cavity in the second support frame may have an optional rigid structure. The rigid structure may have a heating element formed within it.

Abstract: Disclosed are a semiconductor device and method of manufacturing the same comprising a substrate, a mesa region adjacent to the substrate, an electroplated metal layer, for reducing the thermal resistance of the device, surrounding the mesa region, an insulator layer separating a side portion of the mesa region from the electroplated metal layer, a heat sink, a bonding layer adjacent to the heat sink, and a second metal layer in between the substrate and the heat sink, wherein the substrate is adjacent to the bonding layer, and wherein the electroplated metal layer dimensioned and configured to have a thickness of at least half a thickness of the mesa region; and to laterally spread heat away from the mesa region. The mesa region comprises a first cladding layer adjacent to the substrate, an active region adjacent the first cladding layer, and a second cladding layer adjacent to the active region.

Abstract: A light emitting diode (LED) covered with a reflective layer by imprinting process is provided. The imprinting process includes coating a plastic layer on a mold to form an imprinting substrate; coating a reflective layer on the plastic layer and modifying the shape of the reflective layer to fit the shape of outer surfaces of the light emitting diode; softening the plastic layer and impressing the mold covered with the reflective layer upon the LED structure so that the reflective layer adheres to the surfaces of LED; and removing the mold. Because the reflective layer has high reflectivity, the light emitted from the top surface and side surfaces of LED is reflected back to the light extraction direction, and thereby the light extraction efficiency is enhanced.

Abstract: A light emitting device includes a substrate, an epitaxial structure positioned on the substrate, an ohmic contact electrode positioned on the epitaxial structure and a current blocking structure positioned in the epitaxial structure. The epitaxial structure includes a bottom cladding layer, an upper cladding layer, a light-emitting layer positioned between the bottom and the upper cladding layer, a window layer positioned on the upper cladding layer and a contact layer positioned on the window layer. The current blocking structure can extend from the bottom surface of the ohmic contact electrode to the light-emitting layer. According to the present invention, at least one ionic implanting process is performed to implant at least one proton beam into the epitaxial structure to form the current blocking structure.

Abstract: The present invention relates to a process for forming microstructures on a substrate. A plating surface is applied to a substrate. A first layer of photoresist is applied on top of the plating base. The first layer of photoresist is exposed to radiation in a pattern to render the first layer of photoresist dissolvable in a first pattern. The dissolvable photoresist is removed and a first layer of primary metal is electroplated in the area where the first layer of photoresist was removed. The remainder of the photoresist is then removed and a second layer of photoresist is then applied over the plating base and first layer of primary metal. The second layer of photoresist is then exposed to a second pattern of radiation to render the photoresist dissolvable and the dissolvable photoresist is removed. The second pattern is an area that surrounds the primary structure, but it does not entail the entire substrate. Rather it is an island surrounding the primary metal.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

Abstract: An imager pixel utilizing a silicon-on-insulator substrate, a photodiode in said substrate below the buried oxide, and a dual contact to said photodiode and methods of forming said imager pixel. The photodiode has an increased fill factor due to its increased size relative to the pixel.

Abstract: The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a respective first and second kerf area; providing a first redistribution layer on the first integrated structure on the substrate, said first redistribution layer at least partially extending beyond the area of the first integrated structure into the first kerf area, thereby forming a first integrated device area, wherein a first contact pad is arranged on the first redistribution layer in a first contacting area overlapping the first kerf area; providing a second redistribution layer on a second integrated structure on the substrate, including a second contact pad, thereby forming a second integrated device area; separating the first and second integrated device areas along a separation line defined by at least one of

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: This is an interconnection between electronic devices and other assemblies (e.g. printed circuits). The electronic devices are mounted on high temperature insulating bases, such as ceramic substrates. The insulating base has a conductive pattern to connect the electronic device to another assembly. The conductive pattern terminates in metal bumps capable of being connected to another assembly (e.g. a printed circuit) by a conductive adhesive or metallurgically by soldering, thermocompression, thermosonic or ultrasonic bonding. The bumps are formed by applying a metal with a melting point over 350° C. to contact pads of the conductive pattern of the insulating base, and raising the temperature of the base above the melting point of the metal causing the molten metal to draw back on to the contact pads forming a convex bump.

Abstract: A package-ready light-sensitive integrated circuit and process for preparing a light-sensitive semiconductor substrate for packaging that provide for a reduced exposure of a light-sensitive integrated circuit to light. The package-ready light-sensitive integrated circuit includes a semiconductor substrate (e.g., a silicon wafer) with an upper surface and a lower surface and lateral edges, an individual light-sensitive integrated circuit formed in and on the upper surface of the semiconductor substrate, and an opaque material layer covering the lower surface and lateral edges of the semiconductor substrate. The opaque material layer prevents light from entering the semiconductor substrate and interfering with operation of the light-sensitive integrated circuit. The process includes first providing at least one semiconductor substrate with a plurality of light-sensitive integrated circuits formed in and on its upper surface.

Abstract: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: Provides semiconductor devices and method for fabricating devices having a high thermal dissipation efficiency. An example device comprises a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of connected fins. A process for fabricating such a semiconductor device includes forming a thermally conducting structure on a carrier and attaching the thermally conducting structure formed on the carrier to a surface of the semiconductor device via soldering.

Abstract: A semiconductor device manufacturing method comprises etching a front side of a conductive board to form plural sets of a die pad portion and bonding areas, each set corresponding to one semiconductor device. Semiconductor chips are mounted on respective ones of the die pad portions using conductive paste. Electrodes of the respective semiconductor chips are electrically connected with metal wires to the bonding areas, and then the front side of the conductive board, including the semiconductor chips, the bonding areas and the metal wires, are sealed with a molding resin to form a resin-sealed body. Thereafter, the whole back side of the conductive board is removed to a depth sufficient to expose the die pad portions and the bonding areas. Then the resin-sealed body is separated into individual semiconductor devices.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The downset has an upward slope extending from the edge of the frame and levels off with the rest of the frame at a first transition point. The upward slope facilitates the upward flow of the molding compound entering from a bottom gate. Likewise, the leadframe also directs flow in a top gated mold by reversing the orientation of the leadframe or by forming a reverse downset on the leadframe.

Abstract: A ruthenium (Ru) film is formed on a substrate as part of a two-stage methodology. During the first stage, the Ru film is formed on the substrate in a manner in which the Ru nucleation rate is greater than the Ru growth rate. During the second stage, the Ru film is formed on the substrate in a manner in which the Ru growth rate is greater than the Ru nucleation rate.

Abstract: A method for manufacturing a radiofrequency identification device which includes a manufacturing process for an antenna which includes screen-printing turns of an electrically conductive polymer ink onto a transfer paper sheet, and then subjecting the support to heat treatment to bake and polymerize the conductive ink, connection of a chip 14, provided with contacts, to the antenna 12, lamination which includes making the transfer paper sheet integral with a layer of plastic material 16 which constitutes the support for the antenna, by hot press molding, in such a way that the screen-printed antenna and the chip are both embedded within the layer of plastic material, and removal of the transfer paper sheet.

Abstract: A p-type impurity layer is formed in an n-type semiconductor substrate. Since the p-type impurity layer has a low impurity concentration and a sufficiently shallow depth of 1.0 ?m or less, the carrier injection coefficient can be reduced. In the p-type impurity layer, a p-type contact layer of a high impurity concentration is formed for reducing a contact resistance. Since the p-type contact layer has a sufficiently shallow depth of 0.2 ?m or less, it does not influence the carrier injection coefficient. Further, a silicide layer is formed between the p-type contact layer and an electrode such that the contact-layer-side end of the silicide layer corresponds to that portion of the p-type contact layer, at which the concentration profile of the contact layer assumes a peak value. The silicide layer further reduces the contact resistance.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to the semiconductor film by which a temperature holding layer comprising water vapor is formed on the surface of the semiconductor film in irradiating the laser beam and the laser annealing operation can be performed effectively.

Abstract: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.

Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

Abstract: A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in a collector region 13 is formed on the surface of the semiconductor substrate 1; and a base semiconductor layer 14B is formed in contact with the collector region through the first opening 51. The base semiconductor layer 14B is formed such that the edge thereof extends onto the first insulating layer 31.

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

Abstract: A storage capacitor plate for a semiconductor assembly comprising a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent the conductive material, a capacitor cell dielectric overlying the silicon nanocrystals and an overlying conductive top plate. The conductive storage plate is formed by a semiconductor fabrication method comprising forming silicon nanocrystals on a surface of a conductive material and on a surface of an insulative material adjacent the conductive material, wherein silicon nanocrystals contain conductive impurities and are adjoined to formed a substantially continuous porous conductive layer.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.

Abstract: A method of forming a capacitor includes forming a first conductive capacitor electrode layer over a substrate. The first electrode layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a capacitor dielectric layer onto the outer surface. A conductive capacitor electrode layer is formed over the capacitor dielectric layer. A method of forming an electronic device includes forming a conductive layer over a substrate. The conductive layer has an outer surface comprising a noble metal in at least one of elemental and alloy forms. A gaseous mixture comprising a metallorganic deposition precursor and an organic solvent is fed to the outer surface under conditions effective to deposit a dielectric layer onto the outer surface.

Abstract: A ferroelectric capacitor has the property that polarization of a ferroelectric thin film can readily be reversed and polarization-reversal charge increased. The ferroelectric capacitor has a bottom electrode, a ferroelectric thin film and a top electrode. The top electrode includes a metal crystalline phase and 0.5 to 5 atm % interstitial oxygen atoms in the metal crystalline phase.

Abstract: Methods of forming MIM comprise forming a lower electrode on a semiconductor substrate, forming a lower dielectric layer on the lower electrode, and forming an upper dielectric layer on the lower dielectric layer. The lower dielectric layer may be formed of dielectrics having larger energy band gap than that of the upper dielectric layer. An upper electrode is formed on the upper dielectric layer. The upper electrode may be formed of a metal layer having a higher work function than that of the lower electrode.

Abstract: The present invention discloses a STI-first process for making trench DRAM devices. According to the preferred embodiment, the etching recipe for etching the STI region in the memory array is completely compatible with the logic STI process.

Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

Abstract: A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergrate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

Abstract: The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than the components of the memory array region. The methods can include laterally recessing nitride-containing masking structures associated with the peripheral region to a greater extent than nitride-containing masking structures associated with the memory array region, followed by thermal oxidation of the substrate to form dielectric material adjacent the masking structures.