Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

Abstract: A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

Abstract: A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the FLASH memory device, the word lines being spaced from each other a distance less than a minimum feature size which can be imaged by a selected photolithography process used in forming at least a portion of the mask layer pattern, and etching the control gate polysilicon layer through the mask layer.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.

Abstract: Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a source region and a drain region separated by a channel region in a horizontal substrate. A first vertical gate is separated from a first portion of the channel region by a first oxide thickness. A second vertical gate is separated from a second portion of the channel region by a second oxide thickness. The total capacitance of these memory devices is about the same as that for comparable source and drain spacings. However, the floating gate capacitance (CFG) is much smaller than the control gate capacitance (CCG) such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide.

Abstract: Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.

Abstract: The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species; i.e.

Abstract: The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. In one implementation, a substrate is provided which has a first substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms. The first substrate surface has a first degree of roughness. Within a chamber, the first substrate surface is exposed to a PF3 comprising atmosphere under conditions effective to form a second substrate surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms which has a second degree of roughness which is greater than the first degree of roughness. The substrate having the second substrate surface with the second degree of roughness is ultimately removed from the chamber.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.

Abstract: Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.

Abstract: A method for bonding two plate-shaped objects (5) with an adhesive which is cured by ultraviolet light irradiation and by heating. The two plate-shaped objects (5) with the adhesive in between are transported into a cure chamber (11) comprising an ultraviolet lamp (12) and a heating element (13). A moveable heat-shielding member (3) is temporary present between the objects (5) and the heating element (13) during at least the first part of the irradiation treatment. Preferably, the heat-shielding member (3) is positioned outside the cure chamber (11) during a part of the curve treatment.

Abstract: A method of manufacturing a thin film integrated circuit device according to the present invention includes steps of forming a peel-off layer over a thermally oxidized silicon substrate, forming a plurality of thin film integrated circuit devices over the peel-off layer with a base film interposed therebetween, forming a groove between the plurality of thin film integrated circuit devices, and separating the plurality of thin film integrated circuit devices by introducing one of a gas and a liquid including halogen fluoride into the groove to remove the peel-off layer.

Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

Abstract: A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a channel ion implantation layer by an implantation of arsenic ions in a predetermined region of the active area of the semiconductor substrate at a predetermined density, the channel ion implantation layer having a predetermined doping profile according to the predetermined density of arsenic ion implantation. The implantation may be a low-density implantation of 1.0×1012˜1.5×1013atoms/cm2 performed at an energy level of 10˜100keV.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate to define an active region. A source region, a buried N+ region and a drain region are serially disposed at the active region. A memory gate is disposed to cross-over the buried N+ region. A first channel region is formed between the source region and the buried N+ region. A tunnel region is located between the buried N+ region and the memory gate and self-aligned with the buried N+ region.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method includes the steps of: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer, The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

Abstract: A substrate processing apparatus includes a plurality of evacuable treatment chambers connected to one another via an evacuable common chamber, and the common chamber is provided with means for transporting a substrate between each treatment chamber. More specifically, a substrate processing apparatus includes a plurality of evacuable treatment chambers, at least one of said treatment chambers having a film formation function through a vapor phase reaction therein, at least one of said treatment chambers having an annealing function with light irradiation and at least one of said treatment chambers having a heating function therein. The apparatus also has a common chamber through which said plurality of evacuable treatment chambers are connected to one another, and a transportation means provided in said common chamber for transporting a substrate between each treatment chamber.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusions from the contact pad and the ball pad are sized and arranged to have overlapping upper portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

Abstract: A method of fabricating a semiconductor interconnect structure is disclosed. The method includes forming a first metal plug in a first opening defined by a first layer of photoresist, forming a first metal layer in a second opening defined by a second layer of photoresist, forming a second metal plug in a third opening defined by a third layer of photoresist, forming a second metal layer on the third layer of photoresist, and removing the first, second and third layers of photoresist. The first metal plug is also formed in contact with a substrate assembly. The first metal layer is also formed in contact with the first metal plug. The second metal plug is also formed in contact with the first metal layer. The second metal layer is also formed in contact with the second metal plug.

Abstract: Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

Abstract: A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual damascene interconnection includes a lower metal interconnection film, an intermetal insulating film having a via hole and a trench and formed on the lower metal interconnection film, first and second insulative spacer films formed on sidewalls of the via hole and the trench, respectively, a barrier metal layer covering the first and second insulative spacer films and the lower metal interconnection film in the via hole and the trench, and an upper metal interconnection film formed on the barrier metal layer, the via hole and the trench being filled with the upper metal interconnection film.

Abstract: Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

Abstract: A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and treating the dielectric layer with a plasma formed from a methane-containing gas. The treating seals the exposed pores. The method includes depositing a barrier layer over the surface, the barrier layer being continuous over the sealed pores. The porous dielectric may be low K. The plasma may be formed at a bias of at least about 100 volts.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.

Abstract: A method for forming a metal pattern in a semiconductor device which is capable of reducing contact resistivity with an interconnection contact. The method includes forming a tungsten interconnection contact passing through a lower insulating layer on a semiconductor substrate, forming an upper insulating layer covering the interconnection contact, and forming a groove having the same line width as a damascene trench on the upper insulating layer. The method also includes forming a mask spacer on a sidewall of the groove, forming the damascene trench having an inclined bottom profile for exposing a top surface and a portion of a sidewall of the interconnection contact, and forming a metal pattern with which the damascene trench is filled, the metal pattern electrically connected to the interconnection contact.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard layer; forming a third hard layer on the dielectric layer; forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and filling the hole with metal to establish an interconnect. The second and third hard layers are each made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas.

Abstract: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform.

Abstract: A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from positive resist. The copper core of the interconnects and contact surfaces is surrounded by a nickel-gold layer by means of a second resist mask. The interconnects and contact surfaces are produced by means of two resist masks arranged one on top of the other, in such a way that the copper which forms the core of the interconnect is completely surrounded by the nickel-gold layer, which extends above the copper core, and an adjoining layer that extends beneath the copper core and comprises a diffusion barrier and seed layer.

Abstract: A gas delivery device useful in material deposition processes executed during semiconductor device fabrication in a reaction chamber, including the gas delivery device of the present invention and a method for carrying out a material deposition process, including introducing process gas into a reaction chamber using the gas delivery device of the present invention. In each embodiment, the gas delivery device of the present invention includes a plurality of active diffusers and a plurality of gas delivery nozzles, which extend into the reaction chamber. Before entering the reaction chamber through one of the plurality of gas delivery nozzles, process gas must first pass through one of the plurality active diffusers. Each of the active diffusers is centrally controllable such that the rate at which process gas flows through each active diffuser is exactly controlled at all times throughout a given deposition process.

Abstract: A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is applied, without an increase in an area of the semiconductor device. The semiconductor protection element is made up of an N-type well, P-type semiconductor substrate having a pair of N+ diffusion layers each having an impurity concentration being higher than that of the N-type well, and a silicide layer partially formed on each of the two N+ diffusion layers. The N-type well has a first exposed region being exposed on the semiconductor substrate and the silicide layer is so formed that a part of each of the two N+ diffusion layers has a second exposed region being exposed successively so as to be in contact with the first exposed region. The first exposed region is sandwiched by two N+ diffusion layers.

Abstract: Provided is a method forming a desired pattern of electronically functional material 3 on a substrate 1. The method comprises the steps of: creating a first layer of patterning material 2 on the substrate whilst leaving areas of the substrate exposed to define said desired pattern; printing a suspension comprising particles of the electronically functional material 3 in a liquid dispersant, to which the patterning material is impervious, on the patterning material and the exposed substrate; removing at least some of the liquid dispersant from the suspension to consolidate the particles; and applying a first solvent to said consolidated particles which is capable of solubilizing the patterning material 2 and to which the consolidated particles are pervious so that the patterning material is removed from the substrate 1 together with any overlying electronically functional material 3.

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method of etching a silicon layer to avoid non-uniformity. First, a patterned silicon layer is provided. Next, an etching buffer layer is conformally formed on the surface and the top layer of the patterned silicon layer. Finally, the etching buffer layer and the patterned silicon layer are etched until the thickness of the patterned silicon layer is reduced. The conformal oxide layer provides etching resistance as an etching buffer layer, such that the etching rate is uniform on the whole subject matter, thereby, reducing the thickness of the patterned silicon layer uniformly after etching.

Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Abstract: A method of micro-machining a semiconductor substrate to form one or more through slots therein. The semiconductor substrate has a device side and a fluid side opposite the device side. The method includes diffusing a p-type doping material into the device side of the semiconductor substrate in one or more through slot locations to be etched through a thickness of the substrate. The semiconductor substrate is then etched with a dry etch process from the device side of the substrate to the fluid side of the substrate so that one or more through slots having a reentrant profile are formed in the substrate.

Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.

Abstract: Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the resist elements on the surface of the masking structure. Features in the pattern can also be enlarged by depositing polymer on the resist elements or by sloping an underlying layer. In one preferred embodiment, features of the pattern are shrunk before being enlarged in order to reduce line edge roughness.

Abstract: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through the sidewall layer, wherein the features have widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed. An additional mask is formed over the etch layer wherein the additional mask defines a plurality of spaces with widths. A sidewall layer is formed over the additional mask. Features are etched into the etch layer through the sidewall layer, wherein the widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed.

Abstract: A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the spaces defined by the first mask. A first set of features is etched into the etch mask stack through the sidewall layer. The mask and sidewall layer are removed. An additional feature step is performed, comprising forming an additional mask over the etch mask stack, forming a sidewall layer over the additional mask, etching a second set of features at least partially into the etch mask stack. A plurality of features is etched into the etch layer through the first set of features and the second set of features in the etch mask stack.

Abstract: In etching using an etching solution, irradiating ultraviolet light is irradiated into a resist patterned on an etching substrate or a film formed on the etching substrate and then an etching solution is applied to the etching substrate while rotating the etching substrate. Also, ozone water is applied in contact with the resist and then an etching solution is applied to the etching substrate while rotating the etching substrate. In crystallization using a metal element such as nickel for promoting crystallization of silicon, irradiating ultraviolet light is irradiated into a resist patterned on an substrate or a film formed on the substrate and then a nickel solution is applied to the substrate while rotating the substrate. Also, ozone water is applied in contact with the resist and then the nickel solution is applied to the substrate while rotating the substrate.

Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).