Abstract: A monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A source region of the first conductivity type is located over each body region. A contact opening extends between the pair of trenches to a depth below the source regions. An interconnect layer fills the contact opening so as to electrically contact the source regions and the second silicon region. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.

Abstract: A semiconductor device such as a reverse blocking type switching element is provided with a switching element made of a wide band gap semiconductor on the side of a first major plane where a first terminal is formed, while the wide band gap semiconductor is operable at a high voltage and in low loss. In a reverse blocking type switching element having a hetero junction diode for blocking a reverse direction current on the side of a second major plane where a second terminal is formed, a silicon semiconductor region is provided in a side surface of the semiconductor so as to prevent a deterioration of a withstanding voltage of the hetero junction diode.

Abstract: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0.9<x?1, wherein a top surface and a back surface of the substrate are flattened.

Abstract: A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.

Abstract: A semiconductor device according to one embodiment of the present invention includes: a fin including a buffer layer made of SiGe and formed on a Si layer, and a SiGe layer formed on the buffer layer, the SiGe layer having a Ge concentration corresponding to a Ge concentration of the buffer layer in an interface between the buffer layer and the SiGe layer; a gate electrode formed on a side face of the fin through a gate insulating film; a channel region formed in a region within the fin facing the gate electrode through the gate insulating film, the channel region being selectively provided within the SiGe layer of the buffer layer and the SiGe layer included in the fin; and a source region and a drain region formed within the fin, the channel region being formed between the source region and the drain region.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer 12, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Abstract: A circuit board includes: a substrate; source and drain electrodes formed on the substrate; an organic semiconductor layer formed on the source and drain electrodes; a gate insulating layer formed on the organic semiconductor layer; and a gate electrode formed on the gate insulating layer, wherein: the substrate includes a first part, a second part, and a third part interposed between the first and second parts and a thickness of the first part or a thickness of the second part is greater than that of the third part; the source electrode is formed on the first part; the drain electrode is formed on the second part; a part of the organic semiconductor layer is formed on the third part; and a thickness of the gate insulating layer disposed on the first and second parts is smaller than that of the gate insulating layer disposed on the third part.

Abstract: A raised source/drain field effect transistor has a surface of a raised source/drain that tapers downward in a direction of a gate electrode that is also included within the field effect transistor. The downward tapered surface is preferably an end surface. Due to the downward taper, the field effect transistor has a reduced gate to raised source/drain region capacitance. The downward taper also facilitates forming a halo region within the field effect transistor. Due to the raised source/drain, a silicide layer may be included within the raised source/drain region absent silicide penetration through a thin junction within an intrinsic source/drain region also included within the raised source/drain region.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.

Abstract: In one embodiment, the present invention includes a hybrid device having a first die including a semiconductor device and a second die coupled to the first die, where the second die includes a magnetic structure. The first die may be a semiconductor substrate, while the second die may be a magnetic substrate, and the first die may be stacked on the second die, in one embodiment. Other embodiments are described and claimed.

Abstract: An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.

Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.

Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

Abstract: A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).

Abstract: A transistor of a semiconductor device comprises a gate dielectric layer formed over a semiconductor substrate and comprising a hafnium oxide; and a gate electrode formed over the gate dielectric layer.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type silicon substrate. In the epitaxial layer, P type diffusion layers as a base region, N type diffusion layers as collector regions and an N type diffusion layer as an emitter region are formed. In this event, the P type diffusion layers are formed so as to have a double diffusion structure, and an impurity concentration in a surface of the base region and in a region adjacent thereto is set high. This structure enables improvement in high frequency characteristics and in a current amplification factor while maintaining breakdown voltage characteristics of an NPN transistor.

Abstract: In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an n-channel type MISFET, which are formed of metal silicide. Subsequently, an insulating film is formed so as to cover the gate electrode but expose the dummy electrode, and then, a metal film formed of a second metal having a work function lower than that of the first metal. The metal film contacts with the dummy gate but not with the gate electrode due to the insulating film interposing therebetween. Thereafter, through heat treatment, the dummy gate electrode and the metal film are reacted with each other to form a gate electrode of the n-channel type MISFET.

Abstract: A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: A solid-state imaging device includes: a plurality of photodiodes arranged in a matrix on a semiconductor substrate 1 for storing a signal charge converted from incident light; MOS transistors for reading the signal charge stored in the photodiode, an element isolation region for isolating the photodiode from the MOS transistors, an implanted isolation layer formed below the element isolation region, and an impurity region surrounding the photodiode, the sides and bottom of the element isolation region and the implanted isolation layer. The implanted isolation layer covers the sides and bottom of the element isolation region. The solid-state imaging device can efficiently suppress the sensitivity degradation caused by the outflow of electric charge.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

Abstract: A method of fabricating trench capacitors is provided. A plurality of trenches is formed in the substrate by performing a patterning process with a patterned mask layer on a substrate. A bottom electrode is formed in the substrate of the surface of the trench. A portion of the patterned mask layer is removed so as to expose a portion of the substrate at two sides of the top of the trench. A capacitor dielectric layer is formed on the substrate and the surface of the trench. A conductive layer is formed over the substrate. The conductive layer is at least filled into the trench and covers the capacitor dielectric layer. The patterned mask layer and a portion of the conductive layer are removed and the portion of the conductive layer which covers the capacitor dielectric layer is reserved as to form a top electrode.

Abstract: A semiconductor device has: a substrate provided with a trench; and a device isolation structure formed in the trench. The device isolation structure has: a silicon oxynitride film formed on a surface of the substrate through an interfacial oxide film; and an embedded insulating film formed on the silicon oxynitride film.

Abstract: The semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a heat diffusion member mounted on the substrate while covering the semiconductor element, and a resin seal for covering the semiconductor element. An integrated capacitor is mounted on the heat diffusion member in an opposed relationship to the semiconductor element and electrically connected to the semiconductor element. The integrated capacitor and the semiconductor element are electrically connected over a distance as shortest as possible. The heat diffusion member includes a first conductive layer and a second conductive layer isolated from each other by an insulating layer, some terminals of the integrated capacitor are connected to the corresponding terminals of the substrate through the first conductive layer, and the other terminals of the integrated capacitor are connected to the corresponding terminals of the substrate through the second conductive layer.

Abstract: At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.

Abstract: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

Abstract: A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

Abstract: The ratio of capacitance between a floating gate and a control gate to total capacitance in a semiconductor storage device is raised and reliability at read-out is improved by adopting a structure comprising select gates disposed on a substrate in first areas; floating gates disposed in second areas adjacent to the first areas; local bit lines disposed in third areas adjacent to the second areas; and control gates disposed on the floating gates. It is so arranged that capacitance between the select gate and the floating gate is smaller than capacitance between the substrate and the floating gate. It is so arranged that the thickness of a sidewall between the select gate and the floating gate is less than that of an insulating film between the substrate and the floating gate.

Abstract: An electronic non-volatile memory device comprising a base substrate doped with a source region and a drain region. The base substrate can be, for example, a silicon wafer with implanted source and drain regions. A channel region is disposed between the source region and the drain region with a floating gate formed substantially over the channel region. The floating gate may be comprised of a plurality of nanocrystals. A control gate is formed over the nanocrystal floating gate with an erase gate disposed between the nanocrystal floating gate and the control gate. The separate erase gate allows for low voltage operation coupled with a fast erase speed.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor layer; a gate insulating film provided on the semiconductor layer; a floating gate electrode provided on the gate insulating film; a control gate electrode opposed to an upper face of the floating gate electrode; a first dielectric film interposed between the upper face of the floating gate electrode and the control gate electrode; and a second dielectric film. The second dielectric film is provided adjacent to a side face of the floating gate electrode and has a lower relative dielectric constant than the first dielectric film.

Abstract: A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.

Abstract: A memory device, which includes a memory layer having quantum dots uniformly dispersed in organic material disposed between an upper electrode layer and a lower electrode layer. The memory device is advantageous because it is nonvolatile and inexpensive, and realizes high integration and high speed switching. Further, size and distribution of the quantum dots may be uniform, thus realizing uniform memory behavior. Furthermore, the memory device is suitable for application to portable electronic devices that must have low power consumption, due to low operating voltages thereof.

Abstract: A split gate-type non-volatile semiconductor memory device includes a floating gate having an acute-angled portion between a side surface and an upper surface above a semiconductor substrate; a control gate provided apart from the floating gate to oppose to the acute-angled portion; and an insulating portion provided on the floating gate. A side surface of the insulating portion on a side of the control gate is inclined to a direction apart from the control gate with respect to a vertical line to the semiconductor substrate.

Abstract: A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.

Abstract: Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

Abstract: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.

Abstract: A castellated-gate MOSFET I/O device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, and a channel-forming region is also disposed therein between the source and drain regions. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming region. The channel-forming region includes a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements, and a top gate member interconnects the gate elements at their upper vertical ends to cover the channel elements.

Abstract: A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.

Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.

Abstract: The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

Abstract: A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor (3) is connected in series to a power supply voltage supply terminal of a load circuit, an enhancement type MOS transistor (4) for detecting current through the load circuit to operate as a current source is connected to the load circuit, a depletion type MOS transistor (5) is connected in series to the transistor (4), and a gate terminal of the transistor (5) is connected to a source terminal of the transistor (5), in which the gate terminal of the depletion type transistor (3) is connected to the source terminal of the depletion type transistor (5).

Abstract: A driving circuit includes a power supply, an input capacitor, a Hall sensor, a first amplifier, a second amplifier, a full-bridge driver circuit, and a first operational amplifier. The input capacitor is coupled to the power supply. The input end of the first amplifier and the second amplifier is coupled to the output end of the Hall sensor. The control end of the full-bridge driver circuit is coupled to the output end of the first amplifier and the output end of the second amplifier. The first operational amplifier includes a first input end for receiving a first reference voltage and a second input end coupled to the first output end of the full-bridge driver circuit.

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.

Abstract: A semiconductor device includes a gate electrode, and a source region and a drain region proximate the gate electrode. A silicide region is disposed over a top surface of the gate electrode, the source region, or the drain region. A non-silicide region is disposed proximate the silicide region over an edge region of the top surface of the gate electrode, the source region, or the drain region.

Abstract: A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.