Abstract: A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance from the general signal line and the differential signal line, and has a non-formed portion in a region to be electromagnetically coupled to the differential signal line.

Abstract: The invention includes methods of forming semiconductor interconnect structures. A substrate is provided having metal bumps associated with contact pads. A plate having a plurality of cavities containing solder is provided. The metal bumps are inserted into the cavities. The invention includes methods of forming surface-mounting structures. A wafer having a plurality of dies is provided. Each die has contact pads with associated projecting metal bumps. A plate is provided having a pattern of solder-filled cavities corresponding to a layout of the contact pads. The metal bumps are inserted into the cavities and the solder is reflowed to form metal-cored solder bumps. The invention includes constructions such as integrated circuitry chips, wafers and chip package assemblies having a plurality of interconnect structures. The interconnect structures comprise a metal core within an outer solder bump, and are electrically and physically associated with contact pads.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A design for stacking integrated circuits is described. Some integrated circuits have multiple signal pads that are common between a top integrated circuit and a bottom integrated circuit in an integrated circuit pair. These common pads are placed symmetrically on the integrated circuit. Unique signal pads are provided independently to each integrated circuit in a stack. An optional array of solder bumps placed over a central area of the integrated circuit may be used, which provides for heat transfer through the stack. When stacking multiple pairs of integrated circuits, the top integrated circuit in the integrated circuit stack pair serves as a spacer between the first and second pair of integrated circuits.

Abstract: A micro-electro-mechanical systems (MEMS) component includes a panel, a chip having an underside containing active component structures, where the chip is mounted on the panel via bumps, a frame structure on the panel and enclosing an installation site of the chip, and a jet-printed structure closing a seam between frame structure and chip. The jet-printed structure has an upper edge that is above a lower edge of the chip.

Abstract: Embodiments of the present invention provide an apparatus, a system, and a method, and include a generally rectilinear body having a first surface and a second surface. The second surface is substantially perpendicular to the first surface. An electrically operative element is disposed on the first surface, and has opposite ends. Spaced apart terminations are disposed on the second surface, and are electrically coupled with the opposite ends of the electrically operative element. The terminations are designed to be coupled with a substrate.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: In some embodiments, direct power delivery into an electronic package is presented. In this regard, a substrate is introduced having a conductive substrate core designed to physically connect with a power cable. Other embodiments are also disclosed and claimed.

Abstract: A power semiconductor module having a housing, a substrate with conductor tracks and power semiconductor components arranged on the conductor tracks, and a connecting device. The connecting device comprises a film composite with first and second conductive layers, which are respectively patterned and thus form conductor tracks, and an insulating layer disposed between the two conductive layers. The first conductive layer has first contacts, formed as spot-welded joints, for power connecting areas of power semiconductor components, second contacts for control connecting areas of power semiconductor components and third contacts for the load connection to a printed circuit board. The second conductive layer connects to the first conductive layer and fourth contacts for providing control connection to an external printed circuit board. The film composite also has film sections between the first and second contacts and between the third and fourth contacts, which are arranged in guide sections of the housing.

Abstract: The semiconductor module includes a heat spreader and at least two semiconductors coupled thereto. Each of the semiconductors comprises a die containing integrated circuitry and electrical connectors coupled to the die. The module also includes a flexible circuit having opposing first and second sides. The first side of the flexible circuit coupled to the heat spreader, while the second side is coupled to the electrical connectors. The module also includes a termination resistor electrically coupled to the integrated circuitry of at least one of the semiconductors.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: An electronic device capable of varying appearance includes a first cover, a second cover, and a third cover. The second cover is rotatably connected to the first cover. The third cover is movably connected to the first cover. The third cover is moved relative to the first cover from a retracted position to an extended position when the second cover is rotated relative to the first cover from a near position to a distant position. The third cover is moved relative to the first cover from the extended position to the retracted position when the second cover is rotated relative to the first cover from the distant position to the near position.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric.

Abstract: The dielectric device includes a substrate, a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is bonded onto the substrate. The dielectric layer is bonded onto the lower electrode. The dielectric layer is obtained through thermal treatment of a film layer formed by spraying of a powdery dielectric material and a fine-particulate metal. In the thus-formed film layer, the metal is dispersed in the matrix of the dielectric material. Thermal treatment of the film layer causes migration of the metal in the film layer. This metal migration causes a lower-electrode-adjacent portion and upper-surface-adjacent portion of the dielectric layer to have different metal contents.

Abstract: Disclosed are a semiconductor device having a multilayered interconnection structure formed by using a Cu damascene method, and a method of fabricating the same. A Cu interconnection is buried on a first barrier metal layer in a trench formed in the surface of an insulating film. An interlayer dielectric film is formed on the insulating film, first barrier metal layer, and Cu interconnection, and a hole is formed in a position corresponding to the Cu interconnection. An Al-based interconnection is electrically connected to the Cu interconnection in the hole of the interlayer dielectric film. A stacked film is interposed at least between the Cu interconnection and Al-based interconnection. This stacked film includes a second barrier metal layer for preventing the reaction between Cu and Al, and a third barrier metal layer for increasing the fluidity of Al with respect to the second barrier metal layer.

Abstract: A semiconductor integrated circuit device according to an embodiment of the invention includes: a protective element formed on a semiconductor substrate; and a plurality of wiring layers composed of insulating layers including a layer that is a low dielectric-constant film, and metal lines, in which a metal line in a second wiring layer and a metal line in a first wiring layer among the plurality of wiring layers extend from the other region above the semiconductor substrate to a region electrically connected with the protective element.

Abstract: In a contactor contact piece members can be arranged at a fine pitch, and a contact can be made surely by a small contact pressure. The contact piece members electrically connect an electronic part to an external circuit. The contact piece member is formed of an electrically conductive material in a generally spherical shape. A molecular density of a central part of the contact piece member is lower than a molecular density of a part near a surface. The electrically conductive material may include at least one of an electrically conductive fine particle, an electrically conductive fiber and an electrically conductive filler.

Abstract: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.

Abstract: A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.

Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

Abstract: A method of providing an electric device with a vertical component and the device itself are disclosed. The electric device may be a transistor device, such as a FET device, with a vertical channel, such as a gate around transistor, or double-gate transistor First an elongate structure, such as a nanowire is provided to a substrate. Subsequently, a first conductive layer separated from the substrate and from the elongate structure by a dielectric layer is provided. Further, a second conductive layer being separated from the first conductive layer by a separation layer is being provided in contact with at least a top section of the elongate structure.

Abstract: An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion. A display device having a low electric resistivity can be obtained.

Abstract: A semiconductor device is provided that includes a substrate, a lower dielectric layer located on a substrate, and at least one lower conductive interconnect located in the lower dielectric layer. A cap layer is located over the lower conductive interconnect and at least a first dielectric layer is located on the cap layer. At least a first trench/via is formed through the first dielectric layer and the cap layer and is at least in part located over a portion of the lower conductive interconnect. The portion of the lower conductive interconnect defines a chamfered shoulder. A barrier layer lines the first trench/via. A conductive material fills the first trench/via and also fills a region of the lower dielectric layer adjacent the chamfered shoulder of the lower conductive interconnect.

Abstract: A composite semiconductor device includes a substrate, a plurality of circuits, a semiconductor thin film layer, and a dummy pattern. The circuits are formed on the substrate, and include one or more wiring layers. The semiconductor thin film layer includes semiconductor elements and is disposed on an uppermost surface of the one or more layers. A dummy pattern is formed in an area where the one or more wiring layers are absent. A spin-coated layer is formed between the semiconductor thin film layer and the wiring layers. The spin-coated layer may be formed of an organic material or an oxide material.

Abstract: A semiconductor device includes a first copper-containing conductive film formed on a substrate, insulating films formed on the first copper-containing conductive film with a concave portion reaching the first copper-containing conductive film, a second barrier insulating film formed to cover the side wall of the concave portion of these insulating films, a second adhesive alloy film made of copper and a dissimilar element other than copper, and coming in contact with the first copper-containing conductive film at the bottom surface of the concave portion and in contact with the second barrier insulating film at the side wall of the concave portion to cover the inside wall of the concave portion, and a second copper-containing conductive film containing copper as a main component, and formed on the second adhesive alloy film in contact with the second adhesive alloy film to fill the concave portion.

Abstract: The method of manufacturing a wiring substrate includes the steps of: forming a photocatalyst containing layer which is made of a material containing a photocatalytic material, on a substrate made of an insulating material; forming a resin layer in regions other than wire regions on the photocatalyst containing layer; radiating ultraviolet light on the photocatalyst containing layer while the substrate provided with the resin layer and the photocatalyst containing layer is immersed in a solution containing at least a metal ion and a sacrificial reagent, in such a manner that metal is deposited on exposed regions of the photocatalyst containing layer.

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

Abstract: A semiconductor integrated circuit device of improved wireability, fewer number of wiring layers and strengthened power supply includes a plurality of power pads placed on a semiconductor chip and a plurality of signal pads placed on the semiconductor chip and configured to have a width less than that of the power pads. The signal pads and the power pads are placed in the uppermost wiring layer among a plurality of wiring layers. Signal wiring connecting I/O cells and signal pads is disposed in the uppermost wiring layer. First power wiring electrically connecting the I/O cells and first power pads is disposed in the uppermost wiring layer. Second power wiring connecting internal circuits and second power pads is disposed in the uppermost wiring layer.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Abstract: A semiconductor device includes a mount substrate and a semiconductor chip mounted upon the mount substrate via a metal bump, wherein metal bump includes an inner part joined to the semiconductor chip and an outer part covering the inner part, the outer part having an increased hardness as compared with the inner part.

Abstract: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Abstract: A method of easily manufacturing reliable solder contacts on semiconductor dies are made in the shape of a loop made from metal wires or ribbons that may be coated with other solderable metals. The loops can be in multi loop form, single loop forms or both on the semiconductor die. The loop contacts may be formed on the die using thermosonic or ultrasonic bonding. The die may also be packaged with encapsulating material leaving the die exposed through the encapsulating material as a solder-ready contact for the device.

Abstract: An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular developed on a first layer and a second mark portion associated with and in particular developed on a second layer, wherein the first and second mark portions together constitute, when the mark is properly aligned, at least one pair of test zones, each test zone comprising a first mark section formed as part of the first mark portion and a second mark section formed as part of the second mark portion each comprising a plurality of elongate rectangular mark structures in parallel array adjacently disposed to form the said test zone such that the mark structures in each test zone are in alignment in a first direction within the test zone but are substantially at 90° with respect to the mark structures of at least one other test zone in alignment in a second direction, and wherein the test zones making up the or each pair a

Abstract: Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus.

Abstract: Hot water (12) in a bath (11) is pumped up by a suction pump (9) and introduced into a carbon dioxide gas dissolver (7) through solution flow rate adjusting means (14) and then, poured into the bath (11). Carbon dioxide gas supplied from a carbon dioxide gas cylinder (1) is introduced into the carbon dioxide gas dissolver (7) through gas flow rate adjusting means (5). At this time, the quantity of bubbles existing in artificial carbonated spring in a take-out pipe (15) is measured with a measuring device (13), and the solution flow rate adjusting means (14), gas flow rate adjusting means (5) and the like are controlled by means of a control device (16) using a relational expression between a preliminarily set quantity of bubbles and carbon dioxide concentration to obtain a desired concentration of carbon dioxide gas in carbonated spring.

Abstract: Hot water (12) in a bath (11) is pumped up by a suction pump (9) and introduced into a carbon dioxide gas dissolver (7) through solution flow rate adjusting means (14) and then, poured into the bath (11). Carbon dioxide gas supplied from a carbon dioxide gas cylinder (1) is introduced into the carbon dioxide gas dissolver (7) through gas flow rate adjusting means (5). At this time, the quantity of bubbles existing in artificial carbonated spring in a take-out pipe (15) is measured with a measuring device (13), and the solution flow rate adjusting means (14), gas flow rate adjusting means (5) and the like are controlled by means of a control device (16) using a relational expression between a preliminarily set quantity of bubbles and carbon dioxide concentration to obtain a desired concentration of carbon dioxide gas in carbonated spring.

Abstract: Molds for injection molding a light guide plate in which a plurality of pin gates and/or film gates for injecting a melted resin material for molding into the cavity portion are formed at portions corresponding to the side portions of the product, a room for balancing flow having an ear shaped portion to which the material is supplied is disposed between each gate and a sprue or a runner, and the area of each gate is set so that the temperature of the material introduced into the cavity is higher than that supplied to each room by at least 5° C. due to heat generated from shearing when the material passes through the gate; and a process for producing a light guide plate using the molds. Formation of weld lines, sink marks, flow marks and warp is suppressed, and a product exhibiting excellent quality without the necessity of steps of gate cutting and finishing can be obtained.

Abstract: A production method for an optical transmission element (1), wherein a cylindrical transparent resin is used as a core wire, a monomer becoming a polymer different in refractive index from the core wire after polymerized or a mixture of a monomer and a polymer (2) is bonded to the outer periphery of the core wire and the monomer is diffused from the outer periphery of the core wire to thereby form the monomer inside the core wire at a proper concentration distribution, and then the monomer is further polymerized to the core wire to provide a distribution layer having different refractive indexes from the center toward the outer periphery, whereby it is possible to provide a graded index type optical transmission element at low costs with a simple facility.

Abstract: The present invention relates to aqueous processes for the production of silicone hydrogel contact lenses.

Abstract: The present invention relates to aqueous processes for the production of silicone hydrogel contact lenses.

Abstract: An apparatus for manufacturing pre-formatted linear optical data storage media including an elongated linear polymer layer. The apparatus includes a drum mounted for rotation about a rotation axis, and the drum includes a circumferential outer surface having a predetermined pattern of protrusions for embossing at least one pattern of optically readable embossments in the elongated linear polymer layer as the layer is rolled on the drum. The apparatus also includes a thermal radiation source positioned adjacent the drum for heating the embossments of the elongated linear polymer layer prior to the layer being removed from the protrusions of the outer surface of the drum.

Abstract: A mold clamping apparatus has a mold clamping force transmitting member disposed in a middle part of a mold mounting platen on which a mold is mounted. An abutting member is detachably provided in a spaced area between a peripheral portion of a mold mounting platen and peripheral portion of a mold clamping force transmitting member. If this abutting member is retreated from the spaced area so that it does not touch the mold mounting platen or the mold clamping force transmitting member, the deflection of the mold clamping force transmitting member due to a mold clamping force is not transmitted to the mold mounting platen. On the other hand, if this abutting member is inserted in the spaced area so that it touches the mold mounting platen or the mold clamping force transmitting member, the deflection of the mold clamping force transmitting member is transmitted to the mold mounting platen.

Abstract: A mold 20B for foam molding which allows efficient production of the foam molded product with accurately finished outer surface, and easy release of the molded product from the mold in the foam molding method is formed of an upper mold portion 21B and a lower mold portion 22B. The gas feed means 23 formed of the valve box 25, the valve element 26 and the like is attached to an opening formed in the bottom surface of the lower mold portion 22B. The recess portions 51 are formed in each part of the opposite side surfaces 50a and 50c of the cavity 50. The protruding portions 52 are formed on the lower surface of the upper mold portion 21B so as to be fit to the corresponding recess portion 51. Upon completion of curing, the upper mold portion is separated to open the mold, air is supplied into the valve box 25 such that air is fed to a space between the molded product 31B and the bottom surface of the lower mold portion 22B to push up the molded product 31B so as to be released from the mold.

Abstract: A spunbond system for manufacturing a non-woven web of fibers includes a spin beam assembly configured to process and deliver a plurality of polymer streams for extrusion through spinneret orifices. The spin beam assembly includes a plurality of manifold sections within the spin beam assembly, each manifold section including a distribution pipe configured to transfer a respective polymer component to a plurality of piping sections extending within the manifold section and a heat transfer medium that flows within the manifold section and around the piping sections extending into the manifold section so as to maintain the respective polymer component at a selected temperature.

Abstract: Method and system using near infrared (NIR) spectroscopy for dynamically monitoring and controlling the proportion of resin solids or other additive solids in combination with other ingredients used in continuous production of resin-wood composite articles.

Abstract: Provided are filtration matrixes formed from adsorptive media, such as activated carbon, and polymeric binder for use in water filtration systems. A first aspect of the invention provides methods of making a filtration matrix comprising: mixing an adsorptive media with a polymeric binder to form a mixture; impulse filling a mold with the mixture; and processing the mixture to form the filtration matrix. Filtration matrixes formed from this method are also provided. Another aspect includes methods of making a filtration matrix comprising: mixing adsorptive media with a polymeric binder to form a mixture; filling a mold with the mixture; and applying heat and pressure the mixture to form the filtration matrix, wherein the step of applying pressure to the mixture comprises compressing the mixture until a desired final shape of the filtration matrix is obtained.