Abstract: The present invention provides a method and apparatus for to conduct transgenic and targeted mutagenesis screening of genomic DNA. This invention also provides a system for screening DNA for a designated genetic sequence. The system includes a computer having a processor, memory and web browser, wherein the computer receives instructions concerning the designated genetic sequence and other screening parameter selected from a remote user via a form of electronic communication, and an automatic screening device that analyzes samples of genomic DNA for the designated sequence.

Abstract: A feeding tray for retaining a liquid nutrient liquid is provided for use with a multiwell filter plate. The feeding tray includes a flat support surface surrounded by walls which retain liquid on the support surface. The flat support surface includes protrusions positioned to contact the membrane portion of a multiplicity of wells of the multiwell filter plate when the multiwell filter plate is removed from the feeding tray. These protrusions remove residual liquids from the bottom of each filter well thereby minimizing cross contamination in subsequent processing steps. Additionally, it may contain one or more baffles, in lieu of or in addition to the protrusions for controlling liquid movement during handling.

Abstract: A fertilization and culture container, e.g. for intravaginal use, comprises a container body having an orifice for introducing a culture medium, one or more oocytes and sperm, resealable closure means for selectively opening and closing the container body orifice, the container body having a main chamber for receiving the culture medium, oocytes and sperm and a microchamber for collecting for retrieval of one or more embryos. The container body has elements for restricting access of retrieval catheter or pipette relative to the microchamber. At least a portion of a sidewall of the container body defining said microchamber is transparent and of optical quality for microscopic inspection of embryos prior to and/or during retrieval with a catheter or a pipette.

Abstract: The present invention relates to polynucleotides encoding immunogenic HIV polypeptides. Uses of the polynucleotides in applications including immunization, generation of packaging cell lines, and production of HIV polypeptides are also described. Polynucleotides encoding antigenic HIV polypeptides are described, as are uses of these polynucleotides and polypeptide products therefrom, including formulations of immunogenic compositions and uses thereof.

Abstract: Polynucleotides encoding rhesus monkey HER2/neu have been isolated, cloned and sequenced. The gene encoding the HER2/neu is commonly associated with the development of epithelial-derived human carcinomas. The present invention provides compositions and methods to elicit or enhance immunity to the protein product expressed by the HER2/neu tumor-associated antigen, wherein aberrant HER2/neu expression is associated with a carcinoma or its development. This invention specifically provides adenoviral vector constructs carrying rhHER2/neu and discloses their use in vaccines and pharmaceutical compositions for preventing and treating cancer.

Abstract: It has been discovered that when pluripotent stem cells are cultured in the presence of a hepatocyte differentiation agent, a population of cells is derived that has a remarkably high proportion of cells with phenotypic characteristics of liver cells. In one example, human embryonic stem cells are allowed to form embryoid bodies, and then combined with the differentiation agent n-butyrate, optionally supplemented with maturation factors. In another example, n-butyrate is added to human embryonic stem cells in feeder-free culture. Either way, a remarkably uniform cell population is obtained, which is predominated by cells with morphological features of hepatocytes, expressing surface markers characteristic of hepatocytes, and having enzymatic and biosynthetic activity important for liver function.

Abstract: A verification method of a sample solution amount includes the steps of: detecting at least one of a transmitted light component, a scattered light component and a reflected light component of a light by a photosensor while irradiating a sample solution, which is being injected into a sample cell, with the light; and verifying that a predetermined amount of the sample solution is held in the sample cell based on a change in an output signal from the photosensor.

Abstract: A method for diagnosing and monitoring subjects for hemostatic dysfunction, severe infection and systematic inflammatory response syndrome is provided whereby lipoproteins are examined for abnormalities, particularly for prothrominase enhancement, through quantitative and qualitative analysis.

Abstract: The present invention relates to rapid methods for the detection of ischemic states and to kits for use in such methods. Provided for is a rapid method of testing for and quantifying ischemia based upon methods of detecting and quantifying the existence of an alteration of the serum protein albumin which occurs following an ischemic event; methods for detecting and quantifying this alteration include evaluating and quantifying the cobalt binding capacity of circulating albumin, analysis and measurement of the ability of serum albumin to bind exogenous cobalt, detection and measurement of the presence of endogenous copper in a purified albumin sample and use of an immunological assay specific to the altered form of serum albumin which occurs following an ischemic event.

Abstract: An apparatus and system are provided for simultaneously analyzing a plurality of analytes anchored to microparticles. Microparticles each having a uniform population of a single kind of analyte attached are disposed as a substantially immobilized planar array inside of a flow chamber where steps of an analytical process are carried out by delivering a sequence of processing reagents to the microparticles by a fluidic system under microprocessor control. In response to such process steps, an optical signal is generated at the surface of each microparticle which is characteristic of the interaction between the analyte carried by the microparticle and the delivered processing reagent. The plurality of analytes are simultaneously analyzed by collecting and recording images of the optical signals generated by all the microparticles in the planar array.

Abstract: The present invention relates to a receptacle for receiving samples, containing a nucleic-acid stabilizing solution and a nucleic-acid-binding solid phase. The receptacle is especially suited for the withdrawal of blood to be examined for nucleic acid.

Abstract: A method for measuring the amount of fluid contained in a reaction vessel in a clinical analyzer includes the steps of adding a first aliquot of fluid to the reaction vessel and measuring the quantity of fluid contained therein. A second aliquot of fluid is then added to the reaction vessel and the quantity of fluid contained therein is also measured. Measurement of the two fluid quantities can occur with or without removal of the first aliquot in between measurements. In obtaining the two quantity measurements and comparing them against a standard, the effects of well geometry can be minimized. Preferably, a delta or ratio measurement is obtained between the first and second liquid volume measurements which can be compared against a standard so as to normalize apparent volume losses or gains due to reaction well dimensional variation. This approach enhances the analytical capability to detect true fluid delivery errors.

Abstract: A self-assembled relay probe for detecting a target material is provided including: a first peptide tag bound to the target material; and a first fluorescent conjugate including a first fluorochrome and a first tag binding group; wherein the first fluorescent conjugate selectively associates with the first tag. The probe further includes a second peptide tag bound to the target material; and a second fluorescent conjugate including a second fluorochrome having a longer wavelength and distinct excitation and emission maxima from the first fluorochrome and a second tag binding group. Upon exposure to the target material, the first and second fluorescent conjugates independently associate with the first and second peptide tags, respectively, so as to be a distance apart represented by about 0.

Abstract: The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at least one characteristic parameter associated with at least one device structure on the at least one workpiece. The method also includes comparing the at least one characteristic parameter associated with the at least one non-device structure and the at least one characteristic parameter associated with at least one device structure.

Abstract: A wafer level method of packaging, trimming and testing integrated circuits is described. A wafer having trim pads is bumped before the wafer is trimmed. After the bumping, the dice on the wafer are trimmed and tested using standard trim probing and test probing techniques. After the trimming and testing, an electrically insulative undercoating is applied to the active surface of the wafer. The undercoating directly covers the trim pads while leaving at least portions of the contact bumps exposed. The undercoating may be applied using a variety of different processes, including spin-on coating, molding, screen printing or stencil printing. The undercoating may be formed from a wide variety of material including epoxy, polyimide and silicone-polyimide copolymers. With this approach, the wafer may be trimmed and final tested at substantially the same stage of wafer processing. The trimming and testing operations may be performed either sequentially or substantially simultaneously.

Abstract: Built-in electrical test structures are measured for lead-to-lead shorting during the fabrication of MR elements on a wafer. The test structures are fabricated in the same fashion as the MR elements, however, the active sensor region or track width is omitted from the test structures. Thus, the left and right leads for each test structure are electrically isolated from each other in their “track width” region. If there is lead-to-lead shorting on a test structure, then the left and right leads are electrically connected in the track width region. A simple resistance measurement between the left and right leads determines the extent of any lead shorting by giving a quantitative resistance value.

Abstract: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Abstract: A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a first diameter and communicating the first face with the second face. A contact probe including a tubular body having a second diameter which is smaller than the first diameter, and a plunger retractably projected from one end portion of the tubular body is prepared and disposed in the first through hole. A conductive plate having a second through hole is prepared. Molten resin is injected into the second through hole such that at least a part of inner face of the second through hole is covered with solidified resin, thereby forming a third through hole. The conductive plate is disposed so as to oppose to the second face of the conductive member and to communicate the third through hole with the first through hole.

Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

Abstract: The invention relates to a method for the production of self-supporting substrates comprising element III nitrides. More specifically, the invention relates to a method of producing a self-supporting substrate comprising a III-nitride, in particular, gallium nitride (GaN), which is obtained by means of epitaxy using a starting substrate. The invention is characterised in that it consists in depositing a single-crystal silicon-based intermediary layer by way of a sacrificial layer which is intended to be spontaneously vaporised during the III-nitride epitaxy step. The inventive method can be used, for example, to produce a flat, self-supporting III-nitride layer having a diameter greater than 2?.

Abstract: The invention relates to a method for producing a photodiode contact for a TFA image sensor which includes a photodiode, produced by deposition of a multilayer system and a transparent conductive contact layer on an ASIC circuit that has been coated with an intermediate metal dielectric component and that has vias in a photoactive zone which are arranged on a pixel grid. Said vias extend through the intermediate metal dielectric component and are linked with respective strip conductors of the CMOS-ASIC circuit. A pixel-grid structured barrier layer, and on top thereof a CMOS metallization, are arranged on the intermediate metal dielectric component. The aim of the invention is to improve the characteristic variables of the photodiode by simple technological means.

Abstract: In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thickness of the second insulating film is larger than a total thickness of the first electrode and stopper film. Then, second insulating film is polished. By this polishing, the stopper film is exposed to the outside to the outside, and is planarized. After forming an opening in the stopper film, a sacrifice film is burred in the opening. Surfaces of the sacrifice film and second insulating film are planarized, and a second electrode is formed on the second insulating film as to cross the sacrifice film. A space is formed between the first and second electrodes by removing the sacrifice film.

Abstract: The present invention provides an SiGe-based thin film, a method for manufacturing this thin film, and applications of this thin film.

Abstract: To provide a manufacturing method of an electro-optical device capable of effectively forming self-emitting elements in a large substrate on which a plurality of small substrates are arranged in a plane, without increasing the size of a manufacturing apparatus, the electro-optical device manufactured by the method, and an electronic apparatus equipped with the same. When manufacturing an organic EL display device by bonding a plurality of small substrates, processes required for a laser annealing technique and a photolithography technique, such as a process of forming TFTs and a process of forming pixel electrode, are performed before a process of bonding the small substrates to the large substrate, and organic EL elements are formed by an inkjet method after the bonding process. Further, a protective film is formed on the small substrates while the organic EL display elements are being formed.

Abstract: A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: In a method for manufacturing an FBAR device, the device includes a substrate having a certain size, at least one device functional portion performing a resonance function by responding to electrical signals applied from the outside, the device functional portion being formed along a center portion of the substrate while defining a certain air gap therein, plural external electrodes formed on an upper surface of the substrate substantially coming into contact with both opposite edges of the upper surface, the external electrodes being electrically connected to the device functional portion, and a cap bonded onto the substrate so as to function as a cover for covering a remaining portion of the substrate except for the plural external electrodes.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof, in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; punching through from a surface side having the reinforcing member in the wiring substrate, thereby continuously cutting the reinforcing member from an inboard side thereof to an outboard side along a boundary between the first region and the second region; and punching through from the surface side having the reinforcing member in the wiring substrate, thereby cutting the terminals along the boundary between the first region and the second region.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided. In an embodiment of the methods, a second die is mounted on a first die which is at least partially received within a recess of the second die and an overall height of the dies within the device is less than a combined height of the dies.

Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together.

Abstract: A method of fabricating a printed circuit board (PCB) including embedded chips, composed of forming a hollow portion for chip insertion through a substrate, inserting the chip into the hollow portion, fixing the chip to the substrate by use of a plating process to form a central layer having an embedded chip, and then laminating a non-cured resin layer and a circuit layer having a circuit pattern on the central layer. Also, a PCB including embedded chips fabricated using the above method is provided.

Abstract: A method of making an exposed-pad ball-grid array package (11) includes applying a conductive sheet (16) to an adhesive tape (18). Stamping the conductive sheet (16) to form a die pad (24) and separating the remainder (26) of the sheet from the adhesive tape (18) so that only the die pad (24) remains on the adhesive tape (18). A substrate (28) is applied to the adhesive tape (18) proximate to the die pad (24). A die (30) is attached to the die pad (24) and electrically coupled to the substrate (28). An encapsulant (34) is formed around at least a portion of the die (30), the die pad (24) and the substrate (28) above the adhesive tape (18). The adhesive tape (18) is removed from the die pad (24), substrate (28) and encapsulant (34). Conductive balls (36) are attached to the substrate (28).

Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.

Abstract: A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially planar member and at a location that corresponds to the location of a bond pad of a semiconductor device with which the rerouting element is to be used. The at least one conductive element, which communicates with the at least one contact location, reroutes the bond pad location of the semiconductor device to a corresponding rerouted bond pad location adjacent to a second one peripheral edge of the rerouted substantially planar member which is opposite the first periphered edge. In addition, assemblies including rerouting elements and methods for designing and using rerouting elements are disclosed.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. An amorphous semiconductor thin film is irradiated with ultraviolet light or infrared light, to obtain a crystalline semiconductor thin film (102). Then, the crystalline semiconductor thin film (102) is subjected to a heat treatment at a temperature of 900 to 1200° C. in a reduced atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: In a method for forming a silicon-on-insulator FET providing a contact to be given a fixed potential to a substrate, substrate-biasing between an SOI transistor and the silicon substrate is performed via a plug. As a result, the contact hole for the substrate-biasing does not need to pass through an insulating layer, a silicon layer, and an interlayer insulating layer. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can be implanted to the surface of the substrate via the contact hole for substrate biasing. As a result, contact holes for substrate-biasing can be formed without the contact holes for substrate-biasing causing an opening fault.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode.

Abstract: A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.

Abstract: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.

Abstract: A semiconductor memory device and method of manufacturing a semiconductor memory device that prevents oxidation of the bit lines caused by misalignment which may occur when patterning a storage electrode. An oxidation preventing layer, such as a nitride layer, is formed over the bit lines or in the contact holes to eliminate the diffusion of oxygen into the bit line structure, thereby preventing oxidation of the bit lines.

Abstract: A method for forming a ruthenium metal layer on a dielectric layer comprises forming a silicon dioxide layer, then treating the silicon dioxide with a silicon-containing gas, for example silicon hydrides such as silane, disilane, or methylated silanes. Subsequently, a ruthenium metal layer is formed on the treated dielectric layer. Treating the dielectric layer with a silicon-containing gas enhances adhesion between the dielectric and the ruthenium without requiring the addition of a separate adhesion layer between the dielectric layer and the ruthenium metal layer.

Abstract: The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region.

Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.