Abstract: Using a dry film resist that is a photosensitive resin, a resin mask layer is formed around electrodes on a substrate. A solder precipitating composition is applied on the substrate, and this solder precipitating composition is heated to precipitate solder on the surface of the electrodes. Subsequently, in removing the resin mask layer, at least one selected from glycol ethers and aminoalcohols is used. Thereby, the resin mask layer is removed after heating process. This makes it possible to easily remove the heat-processed resin mask layer in a short period of time without damaging solder resist and solder bumps on the substrate.

Abstract: A photo-sensing device package and the method of packaging such device is provided. The package includes an assembly portion having a substrate formed of a material substantially transparent to light within a predetermined range of wavelengths and a sensing portion having at least one photo-sensing die photo-electronically transducing light within the predetermined range of wavelengths. The assembly portion is formed with at least one metal layer disposed on the substrate about a front surface region thereof, and at least one passivation layer formed to extend over the metal layer. The passivation layer is patterned to define a plurality of first and second access openings respectively about a plurality of first solder wettable pads and at least one second solder wettable pad on the metal layer.

Abstract: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.

Abstract: Provided are a piezoelectric element and a liquid-jet head using the same, in which favorable crystallinity can be obtained with improved uniformity, breakage of a piezoelectric film can be prevented, thereby providing stable displacement properties. The piezoeletric element includes a lower electrode, a piezoelectric film formed on the lower electrode, and an upper electrode formed on the piezoelectric film. The piezoelectric film in turn includes a lower layer portion having column crystals, and an upper layer portion having column crystals which are continuous from those in the lower layer portion and having sizes larger than those in the lower layer portion.

Abstract: A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.

Abstract: In one method of forming a semiconductor device, a first electrode is formed electrically coupled with a semiconductor material. After the first electrode is formed, an insulator is formed over the semiconductor material adjoining the first electrode and extending a selected distance from the first electrode. After the insulator is formed, a second electrode is formed electrically coupled with the semiconductor material adjoining the insulator.

Abstract: After crystallization of a semiconductor film is performed by irradiating first laser light (energy density of 400 to 500 mJ/cm2) in an atmosphere containing oxygen, an oxide film formed by irradiating the first laser light is removed. It is next performed to irradiate second laser light under an atmosphere that does not contain oxygen (at a higher energy density than that of the first laser light irradiation), thus to increase the flatness of the semiconductor film.

Abstract: A method of fabricating a transistor device for regulating the flow of electric current is provided wherein the device has Schottky-barrier metal source-drain contacts. The method, in one embodiment, utilizes an isotropic etch process prior to the formation of the metal source-drain contacts to provide better control of the Schottky-barrier junction location to a channel region. The improvements from the controllability of the placement of the Schottky-barrier junction enables additional drive current and optimizes device performance, thereby significantly improving manufacturability.

Abstract: A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.

Abstract: A dielectric material layer is formed over a workpiece, a metal layer is formed over the dielectric material layer, and a semiconductive material layer is formed over the metal layer. The workpiece is heated, causing a top portion of the metal layer to interact with the semiconductive material layer and causing a bottom portion of the metal layer to diffuse into the dielectric material layer. The metal layer portion that interacts with the semiconductive material layer forms a silicide, and the diffused metal layer portion forms a high dielectric constant gate material having a graded concentration of the metal from the metal layer. At least the semiconductive material layer and the dielectric material layer are patterned to form a gate and a gate dielectric of a transistor device. A source region and a drain region are formed in the workpiece proximate the gate and gate dielectric.

Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract: Processing a semiconductor wafer can include forming a plurality of Light Emitting Devices (LED) on a semiconductor wafer having a first thickness. The plurality of LEDs on the wafer are brought into contact with a surface of a carrier to couple the wafer to the carrier. The first thickness of the wafer is reduced to a second thickness that is less than the first thickness by processing the backside of the wafer. The carrier is separated from the plurality of LEDs on the wafer and the wafer is cut to separate the plurality of LEDs from one another. Related devices are also disclosed.

Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract: In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of the silicon structure. A layer is produced over the surface and the silicon oxide and an opening is produced in the layer, the opening abutting on the silicon oxide. The selectively grown silicon oxide is removed and the opening is filled with electrically conductive material, whereby the electrically conductive material forms the contact.

Abstract: A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory cells are arranged in cell rows offset with respect to one another and are separated from one another by strip-like isolator structures. Buried word lines are embedded in the isolator structures and run along the longitudinal faces of semiconductor fins which are formed along the cell rows and include the active regions of the selection transistors. The internal electrodes of the trench capacitors are each connected with a low impedance via surface straps to first source/drain areas of the respective selection transistors. In one embodiment, one word line is formed for each isolator structure using an open bit line architecture, with only every alternate word line being used for addressing. A reinforced word line/trench isolator is provided between the word lines and the trench capacitors.

Abstract: A method of manufacturing a semiconductor device has the steps of: preparing a semiconductor substrate having a structure in which first and second active regions are isolated by a field oxide; forming a first insulation film and a first film on the semiconductor substrate; exposing the first active region in the first active region; forming a second insulation film and a first conductive film over the first active region, the second insulation film being thicker than the first insulation film; processing the first conductive film and the second insulation film into a first gate electrode and a first gate insulation film; exposing the second active region in the second active region; forming a third insulation film and a second conductive film on the over the second active region, the third insulation film being thinner than the second insulation film; and processing the second conductive film and the third insulation film into a second gate electrode and a second gate insulation film.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating film over the whole surface including the upper surface of the gate electrode; by removing the formed first insulating film through etching from the top surface side, forming first sidewalls, covering the side surfaces of the gate electrode, from the first insulating film; and by implanting first impurity ions of a second conductive type to the semiconductor region by using an ion implantation device capable of processing a plurality of semiconductor wafers collectively, forming first impurity diffusion regions on both sides of the gate electrode in the semiconductor region.

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Abstract: The invention provides a method for producing a solid electrolytic capacitor reliable with good LC value after mounting, wherein a solid electrolytic capacitor element comprises an anode body composed of a material containing at least one selected from a group consisting of an earth-acid metal, an alloy comprising an earth-acid metal as the main component, an electrically conducting oxide of an earth-acid metal and a mixture of two or more thereof, a dielectric layer formed on the anode body by electrolytic oxidation (electrochemical formation) and comprising an oxide as the main component, a semiconductor layer formed on the dielectric layer, and an electrically conducting layer stacked on the semiconductor layer, and the solid electrolytic capacitor element is molded with a resin, cured and then applied voltage (aging) treatment, which method comprises sequentially repeating a step of leaving the resin-molded body to stand at 225 to 305° C.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches.

Abstract: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit light, allowing a photodetector to respond to transmitted light to stimulate a retina, for example. Discrete electronic components may be placed in the three-dimensional street area of the integrated circuit package, yielding a completely integrated hermetic package that is implantable in living tissue.

Abstract: A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.

Abstract: A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a <100> crystal direction notch (32a) and a <110> crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a <110> crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers.

Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: A photodetector (100, 200, 300) comprising a gallium nitride substrate, at least one active layer (104, 302) disposed on the substrate (102, 202, 306), and a conductive contact structure (106, 210, 308) affixed to the active layer (104, 302) and, in some embodiments, the substrate (102, 202, 306). The invention includes photodetectors (100, 200, 300) having metal-semiconductor-metal structures, P-i-N structures, and Schottky-barrier structures. The active layers (104, 302) may comprise Ga1-x-yAlxInyN1-z-w PzAsw, or, preferably, Ga1-xAlxN. The gallium nitride substrate comprises a single crystal gallium nitride wafer and has a dislocation density of less than about 105 cm?2. A method of making the photodetector (100, 200, 300) is also disclosed.

Abstract: A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking voltage to the electrostatic chuck. The method further includes introducing into the chamber a precursor gas including a species to be ion implanted in the workpiece and applying an RF bias to the electrostatic chuck, the RF bias having a bias level corresponding to the ion implantation profile depth.

Abstract: A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

Abstract: A filter device and a method for fabricating filter devices can package filters, especially acoustic wave filters, by bonding a carrier (substrate) wafer carrying manufactured filters to another wafer referred to as a capping wafer. A capping wafer/substrate eliminates the need for a conventional package to protect the sensitive filters, which reduces both product size and product costs significantly. Even though additional packaging is possible (i.e. in plastic molded packages, or in glob-top packages), it is not required for the reliability of the filters.

Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.

Abstract: A example method of forming of a contact hole by removing residue and oxide spacer beside a nitride spacer after a CF containing etch. We provide a gate structure with nitride spacers on the sidewalls of the gate. We provide a dielectric layer (oxide) over the substrate and gate structure. We form a contact photoresist pattern over the oxide dielectric layer. We etch the oxide dielectric layer using fluorocarbons (CxFy) to form contact openings and residual spacer. The photoresist is striped. Preferably, a NF3 and N2 and H2 plasma treatment is performed to deposit a byproducts layer over the residual spacer. The byproducts layer and residual spacer are removed preferably using one of the following processes: (1) heat (2) DI rinse or (3) IR or UV radiation.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an uppermost layer of amorphous carbon substantially conformally over the hardmask layer; forming a trench line opening through at least the thickness of the amorphous carbon layer; forming a dual damascene opening comprising forming the trench line opening overlying a via opening pattern through a thickness of the hardmask layer and partially through a thickness of the dielectric insulating layer; and, filling the dual damascene opening with metal.

Abstract: A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing member by pressing the pressing member against the flowable film; forming a solidified film having the first concave portion by solidifying the flowable film through annealing at a first temperature with the pressing member pressed against the flowable film; forming a burnt film having the first concave portion by burning the solidified film through annealing at a second temperature higher than the first temperature; forming a second concave portion connected at least to the first concave portion in the burnt film by forming, on the burnt film, a mask having an opening for forming the second concave portion and etching the burnt film by using the mask; and forming a plug and a metal interconnect by filing the first concave portion and the second concav

Abstract: A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first material. The first and second materials are of different compositions, and are proximate one another at an interface. The first and second materials as being proximate one another at the interface are capable of reacting with one another at some minimum reaction temperature when in an inert non-plasma atmosphere at a pressure. The interface is provided at a processing temperature which is at least 50° C. below the minimum reaction temperature, and is provided at the pressure. With the interface at the processing temperature and at the pressure, the substrate is exposed to a plasma effective to impart a reaction of the first material with the second material to form a reaction product third material of the first and second materials over the first material. Other aspects and implementations are contemplated.

Abstract: A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug.

Abstract: A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectric layer. A conductive layer is deposited on the barrier layer and filling the opening. Then, a step of planarization is performed to form the interconnection structure, such that a peripheral edge of a top surface of the interconnection structure is no lower than a top surface of the barrier layer.

Abstract: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided.

Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist pattern of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist pattern of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.

Abstract: Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract: In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.

Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

Abstract: A method and system for facilitating etching. Specifically, the method includes incorporating a fluorescent marker in a layer of a grouping of patterned layers. Etching of the group of patterned layers is controlled based upon the fluorescent marker.

Abstract: A method and system is described for treating a substrate with a high pressure fluid, such as carbon dioxide in a supercritical state. A process chemistry is introduced to the high pressure fluid for treating the substrate surface. The process chemistry comprises fluorosilicic acid.

Abstract: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to erosion by the plasma, and a bonding layer that improves the adhesion of the protective layer to the processing element to mitigate possible process contamination by failure of the protective layer.