Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: PROBLEM To provide a high quality solid state image pickup device. SOLUTION Impurities are implanted into a semiconductor substrate to form vertical transfer channels for transferring electric charges in a first direction and to form a drain near each of the vertical transfer channels via a gate which forms a barrier. A first silicon oxide film, a silicon nitride film and a second silicon oxide film are deposited in this order from the bottom, on the surfaces of the vertical transfer channels, gates and drains. A first layer vertical transfer electrode is formed on the second silicon oxide film above the vertical transfer channel, and an insulating film if formed on the surface of the first layer vertical transfer electrode. The second silicon oxide film and silicon nitride film are etched in such a manner that the silicon nitride film covers the vertical transfer channel and extends above the gate excepting a portion near the drain.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: The present invention discloses the semiconductor device having the substrate that reflects the laser beam on a surface; that absorbs the laser beam therein; or that partially reflects the laser beam on the surface and partially absorbs the laser beam in the laser annealing. Moreover, the substrate has a poly-crystalline semiconductor film having a large grain size. The present invention suppresses the effect due to the reflected light from a rear surface of the substrate and therefore the uniform laser annealing can be performed.

Abstract: A programmable structure and device and methods of forming and using the structure and device are disclosed. The structure includes a soluble electrode, an ion conductor, and an inert electrode. Upon application of a sufficient voltage, a conductive region forms within or on the ion conductor and between the electrodes. The presence or absence of the conductive region can be used to store information in memory devices.

Abstract: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

Abstract: Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.

Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: At least either above or below a memory transistor formed on an insulating substrate, a shielding layer which has an area larger than that of the semiconductor layer of the memory transistor and has either an electromagnetic wave shielding effect or a light shielding effect or both of these is provided, and by this shielding layer, electromagnetic waves or light is prevented from entering the semiconductor layer. Or, the regional area of at least one of the gate and the charge accumulation layer of the memory transistor is made larger than the semiconductor layer to prevent electromagnetic waves or light from entering the semiconductor layer by the gate or the charge accumulation layer.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Abstract: A vertical power semiconductor device comprises a substrate including a first layer that is a first conductivity type. A first conductive region is provided proximate an upper surface of the substrate, the first conductive region being a second conductivity type that is different from the first conductivity type. A first electrode is provided proximate the upper surface of the substrate and coupled to the first conductive region. A second electrode is provided proximate a lower surface of the substrate. A passivation structure including first and second dielectric layers provided over the upper surface of the substrate. One or more field plates of first type are provided between the first and second dielectric layers.

Abstract: The invention relates to a field effect controllable semiconductor component, comprising a semiconductor body with a first terminal zone and a second terminal zone, a channel zone formed between the two terminal zones, a control electrode, and also a plurality of compensation zones. The semiconductor component furthermore has additional doping zones which are arranged in spatial proximity to the compensation zones or in a manner merged therewith. The additional doping zones are connected to the first terminal zone, if appropriate via a series diode.

Abstract: Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0<A=t/(t+d)?0.72 where t is the thickness of the first semiconductor layer, and d is the thickness of the second semiconductor layer.

Abstract: TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: A layout capable of placing a circuit constituted by a plurality of transistors in a small-with region is automatically formed. A search section inputs data on a circuit and makes a search for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes in sets of route found by searching. A width determination section determines the layout width from the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes.

Abstract: A multi-transistor layout capable of saving area includes a substrate; a common drain comprising four sides formed over the substrate; four gates formed over the four sides of the common drain; and four sources formed over outer sides of the four gates corresponding to the common drain.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: A micromechanical cap structure and a corresponding manufacturing method are described. The micromechanical cap structure includes a first wafer with a micromechanical functional structure, and a second wafer to form a cap over the micromechanical functional structure. The first and second wafers have in their interior a support structure with a metal-semiconductor contact, and in their edge zone a bonding structure. The edge zone of the second wafer, when in the capped state, is arched in relation to the interior of the second wafer.

Abstract: A capacitive dynamic quantity sensor whose size is small and whose reliability and mass productivity are high is provided. In order to realize signal transmission from a lower electrode to an upper electrode, silicon columns which are electrically isolated from one another but not mechanically isolated from one another are formed to connect both electrodes.

Abstract: A photodetector includes a charge carrier collector and a charge carrier concentrator that redirects onto the collector charge carriers that are not initially headed towards the collector.

Abstract: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

Abstract: A method of manufacturing a nanowire filament includes forming and fusing actions. In a forming action, close proximity conductors are formed. In another forming action, a junction oxide is formed between the close proximity conductors. In a fusing action, a nanowire filament is fused between the close proximity conductors, through the junction oxide. A circuit is also provided, having first and second close proximity conductors, and a nanowire filament fused between the close proximity conductors.

Abstract: A pad electrode of a field effect transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the related art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, in the case of a buried gate electrode structure for enhancing characteristics of the field effect transistor, it is possible to enhance reliability and yields.

Abstract: A p impurity region (3) defines a RESURF isolation region in an n? semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n? semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n? semiconductor layer (2) and a p? semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

Abstract: The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Abstract: A thin film capacitor comprising a lower electrode formed on a predetermined surface, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the end portion of the lower electrode is further covered by an insulator other than the dielectric layer.

Abstract: An apparatus for supplying electrical power to a movable member. The apparatus includes a fixed member, the movable member moving relative to the fixed member, a flexible wiring member having an end connected to the movable member and another end connected to the fixed member, configured to transmit the electrical power from the fixed member to the movable member, and a cooling member configured to cool the fixed member.

Abstract: A solid-state imaging device includes a housing having a resin-molded base and ribs; metal lead pieces embedded in the housing, the metal lead pieces each having an inner terminal portion facing an inner space of the housing, an outer terminal portion exposed at a bottom surface of the housing, and a lateral electrode portion exposed at an outer lateral surface of the housing; an imaging element fixed on the base in the inner space; connecting members connecting electrodes of the imaging element respectively to the inner terminal portions; and a transparent plate fixed to an upper surface of the ribs. The die pad having a through hole is embedded in a center portion of the base so that the die pad's upper and lower surfaces are exposed, and the imaging element is fixed on the die pad. A ventilation hole to the inner space of the housing that is formed in one piece with a resin can be formed easily with a simple configuration.

Abstract: A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: The invention relates to an electronic component having a multilayered rewiring plate, which carries a circuit chip, in particular a magnetic memory chip, and connects contact areas of the chip to external contacts of the electronic component via rewiring lines. The rewiring plate has at least one patterned, magnetic shielding layer made of an amorphous metal or an amorphous metal alloy. Furthermore, the invention encompasses a method for producing this electronic component.

Abstract: A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between terminals on the die and the bond pads to form a package subassembly. The subassembly is encapsulated and then background to remove the leadframe fingers and surrounding frame. The bond pads which remain embedded in the encapsulation material are exposed on the lower surface of the package for connection to further conductors.

Abstract: A semiconductor device is composed of a heat sink, an IC chip mounted and fixed on a specific face of the heat sink, a lead frame electrically connected to the IC chip and a sealing mold resin package. One or more of the faces of the heat sink has a specific surface area.

Abstract: A protective cap for adhesion to a substrate including a substantially flat base sheet, a dome extending outwardly from an obverse side of the base sheet and forming a cavity in the opposite side of the base sheet with the cavity sized for substantially encapsulating a connector. The cap also includes a semi-tubular shield extending outwardly from one side of the base sheet that defines a channel in the opposite side of the base sheet extending from the cavity toward the periphery of the base sheet, and an integrated primer layer comprising a pressure-sensitive adhesive and attached to the reverse side of the base sheet for application to the substrate.

Abstract: An interconnect structure including a substrate, an interconnect device formed on the substrate, and a test device formed on the substrate.

Abstract: An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and a composition disposed between the first substrate and the second substrate including a siloxane-based aromatic diamine.

Abstract: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Abstract: The present invention provides an IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit containing a circuit line having a bypass line and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to a circuit section consisting of the electronic circuit and the IC chip and located at the interface between the substrate sheet and the first adhesive layer, wherein the angle formed by the tangent of the bypass line at the connection between the bypass line and the circuit line and the tangent of the circuit line at the connection is 10 degree or greater. When the IC tag attached to an article is peeled off, the built-in electronic circuit is surely broken.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: A device comprises a first substrate, a second substrate and a compliant element. The compliant element is composed of a first, compliant material between the first substrate and the second substrate and has a side surface coated at least in part with a layer of a second material. The compliant element exhibits deformation consistent with the first substrate and a second side having been pressed together. In some embodiments, the second material is electrically conductive such that the compliant element provides a reliable electrical connection between the substrates. In other embodiments, the second material increases the hermeticity of the compliant element such that the compliant element provides a better hermetic seal between the substrates.