Patents Issued in November 27, 2007
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Patent number: 7300787Abstract: The present invention relates to L-lactic acid producing bacterial strains, including Lactobacilli such as NRRL B-30568 (ADM B64), NRRL B-30569 (ADM DEC2-2B), NRRL B-30570 (ADM RP1A-4E), NRRL B-30571 (ADM RP2-1C), NRRL B-30572 (ADM RP3-1E), NRRL, B-30573 (ADM RP4A-2C), NRRL B-30574 (ADM LC49.25), NRRL B-30575 (ADM LC54.62) and mutations thereof. The present invention also relates to processes of producing L-lactic acid by culturing these strains. The present invention also relates to a method of making a bacterial strain that is capable of producing an increased yield or optical purity of L-lactic acid relative to these strains.Type: GrantFiled: July 5, 2002Date of Patent: November 27, 2007Assignee: Archer-Daniels-Midland CompanyInventors: John M. Eddington, Kevin Brent Johnson, Hungming J. Liaw, Melanie Rowe, Yuegin Yang
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Patent number: 7300788Abstract: The invention provides nucleic acid sequences that are complementary, in one embodiment, to a wide variety of human polymorphisms. The invention provides the sequences in such a way as to make them available for a variety of analyses including genotyping a large number of SNPs in parallel. The invention also provides a collection of human SNPs that is useful for genetic analysis within and across populations. As such, the invention relatesd to diverse fields impacted by the nature of genetics, including biology, medicine, and medical diagnostics.Type: GrantFiled: October 7, 2003Date of Patent: November 27, 2007Assignee: Affymetrix, Inc.Inventors: Hajime Matsuzaki, Rui Mei, Mei-Mei Shen, Giulia C. Kennedy
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Patent number: 7300789Abstract: The invention provides a bioreactor (10) for the culture of animal, vegetable, microbial of algal cells of their co-cultures, of the type including a body (12) which delimits an internal volume (14) capable of holding a culture liquid (16) and a gas volume (17) above the culture liquid (16), and which includes means for introducing (18) and/or extracting (20) elements respectively into and/or out of the internal volume (14) of the body (12), and of the type which includes means (22) for driving the body (12) in an oscillating movement so as to obtain agitation of the culture liquid (16), characterised in that the body (12) is a rigid vessel.Type: GrantFiled: May 21, 2003Date of Patent: November 27, 2007Assignee: L'OrealInventors: Richard Martin, Pascal Hilaire
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Patent number: 7300790Abstract: The present invention relates to non-vaccinal and non-pharmacologic compositions and methods for controlling complex retroviral infections. In particular, the present invention provides transgenic animals expressing a transdominant negative Rex gene product that inhibits retroviral replication.Type: GrantFiled: January 23, 2004Date of Patent: November 27, 2007Assignee: ioGenetics, LLCInventors: Kurt Eakle, Thomas Hope, Eun-A Choi, Jane Homan, Robert D. Bremel
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Patent number: 7300791Abstract: DNA isolates coding for a vascular endothelial cell growth factor may be used to produce the protein via recombinant expression systems. Such protein is useful therapeutically to treat conditions in which a selective action on the vascular endothelial cells, in the absence of excessive connective tissue proliferation, is desirable.Type: GrantFiled: May 17, 2002Date of Patent: November 27, 2007Assignee: Genentech, Inc.Inventors: Napoleone Ferrara, David Wai-Hung Leung
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Patent number: 7300792Abstract: The luxA, B, C, D, and E genes from Photorhabdus luminescens have been introduced into Saccharomyces cerevisiae bioluminescent yeast cells.Type: GrantFiled: April 4, 2003Date of Patent: November 27, 2007Assignee: University of Tennessee Research FoundationInventors: Rakesh K. Gupta, Stacy S. Patterson, Gary S. Sayler, Steven A. Ripp
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Patent number: 7300793Abstract: A method for the prevention of the adhesion of particles, in particular cells and cellular components in solution to surfaces, characterized in that to the solution is added at least one polyalcohol.Type: GrantFiled: July 17, 2002Date of Patent: November 27, 2007Assignee: Evotec Technologies GmbHInventor: Gabriele Gradl
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Patent number: 7300794Abstract: The present invention provides a unique medium for the cultivation of intestinal cell lines. The medium allows for the development of a highly differentiated intestinal epithelial cell monolayer in a much shorter period of time than currently possible without the aid of cell culture substrates.Type: GrantFiled: March 11, 2004Date of Patent: November 27, 2007Assignee: Supernus Pharmaceuticals, Inc.Inventors: Marina Lowen, Ali Keshavarz-Shokri
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Patent number: 7300795Abstract: Optoinjection method for transiently permeabilizing a target cell by (a) illuminating a population of cells contained in a frame; (b) detecting at least one property of light directed from the frame; (c) locating a target cell by the property of light; and (d) irradiating the target cell with a pulse of radiation.Type: GrantFiled: March 30, 2004Date of Patent: November 27, 2007Assignee: Cyntellect, Inc.Inventors: Manfred R. Koller, Elie G. Hanania, Timothy M. Eisfeld, Bernhard Ø. Palsson
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Patent number: 7300796Abstract: A test environment and an associated method of testing and analyzing a semiconductor package material containing a molding compound, for stability in a sustained oxygen environment. Test samples are exposed to a pressurized gas containing oxygen, under elevated temperature below the glass transition temperature of the molding compound. Control samples are exposed to a pressurized inert gas under similar or more severe conditions of gas pressure, temperature, and humidity. At least one characteristic common to the test samples and the control samples is measured. A determination is made as to whether there exists at least one significant difference between the at least one measured characteristic of the test samples and the control samples.Type: GrantFiled: September 9, 2003Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Joseph K. V. Comeau, Adele M. Mahoney, Jason P. Ritter, Gerald J. Scilla, Charles H. Wilson
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Patent number: 7300797Abstract: A multifunctional reagent for erythrocytes containing an amount sufficient to produce the lysis of erythrocytes or the sphering of erythrocytes in such a way that they can be detected by a cytometer or an automatic counting device, of a carbamate or of an agent inducing the formation by the erythrocytes, from carbonate and from a nitrogenated heterocycle or ammonium ions, of a carbamate combined with the absorption of CO2 by said erythrocytes, process for lysing or sphering erythrocytes and preparation process for leucocytes.Type: GrantFiled: September 14, 2001Date of Patent: November 27, 2007Assignee: Immunotech, S.A.Inventors: Andre van Agthoven, Jean-Pierre Daziano, John Allen Maples
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Patent number: 7300798Abstract: A method and apparatus for using arrays of polymers each having a pattern of features over a corresponding array region on a surface of a flexible elongated web. In this method each array region may be exposed to a corresponding continuous volume of a sample fluid. A method and apparatus are also provided for reading arrays disposed along a surface of a flexible elongated web. In one such method the web with the arrays thereon may be transported in a lengthwise direction past a reading location at which a characteristic of the features is read, while restraining the web on both surfaces on either side of the reading location to assist in maintaining the reading location flat.Type: GrantFiled: October 18, 2001Date of Patent: November 27, 2007Assignee: Agilent Technologies, Inc.Inventors: Michel G. M. Perbost, Steven M. Lefkowitz, Roy H. Kanemoto, Carol T. Schembri
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Patent number: 7300799Abstract: A method for determining degree of organoclay delamination and degree of layer alignment in a polymer organoclay nanocomposite comprising one or more infrared light spectral measurements selected from the group consisting of (A) Si—O absorption bandwidth, (B) Si—O absorption band intensity, (C) Si—O absorption band area, and (D) Si—O absorption anisotropy.Type: GrantFiled: June 24, 2005Date of Patent: November 27, 2007Assignee: Elementis Specialties, Inc.Inventors: Wouter Ijdo, Steven Kemnetz, Wilbur Mardis, Daphne Benderly
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Patent number: 7300800Abstract: An analyte detection system utilizing a combination of fluorescent labels for labeling particles and an analyte specific fluorescent analyte detection dye. The particles contain a combination of fluorescent labels for coding the particles and an analyte specific fluorescent dye. The particles can be used to identify and quantify analytes in an analytical sample by reaction of the analytical sample with the particles. An analytical device can identify the particles according to the combination of fluorescent labels. The device can then correlate the identified particle with the analyte specific fluorescent analyte detection dye. Multiple subpopulations of particles can be used to identify and quantify multi-analytes in a single analytical sample. Near infrared (NIR) fluorescent labels useful in the detection system are also provided.Type: GrantFiled: May 13, 2005Date of Patent: November 27, 2007Assignee: Beckman Coulter, Inc.Inventors: Michael L. Bell, Yuan Lin, Josephine M. Michael, Stephen L. Pentoney, Jr., Tsong-Tseh Tsay
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Patent number: 7300801Abstract: Solid phase extraction articles, well-less filtration devices, and methods of manufacturing the articles and devices are disclosed. Methods of extracting analytes from samples using the articles and devices are also disclosed. The articles, devices and methods include a solid phase extraction medium (SPE medium) that incorporates thermoplastic material, e.g., in the form of thermoplastic particles enmeshed within a fibril matrix.Type: GrantFiled: September 12, 2003Date of Patent: November 27, 2007Assignee: 3M Innovative Properties CompanyInventors: Robert A. Pranis, Craig A. Perman
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Patent number: 7300802Abstract: The present invention relates to a biosensor for point-of-care testing (POCT) whose detection sensitivity was remarkably improved by introducing to membrane strip chromatographic assay system a successive cross-flow procedure for immune reaction and enzymatic reaction.Type: GrantFiled: April 20, 2004Date of Patent: November 27, 2007Assignee: Biodigit Laboratories Corp.Inventors: Se Hwan Paek, Jung Hwan Cho, Ser Ka Kim
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Label-free methods for performing assays using a colorimetric resonant reflectance optical biosensor
Patent number: 7300803Abstract: Methods are provided for detecting biomolecular interactions. The use of labels is not required and the methods can be performed in a high-throughput manner. The invention also relates to optical devices.Type: GrantFiled: August 22, 2006Date of Patent: November 27, 2007Assignee: SRU Biosystems, Inc.Inventors: Bo Lin, Jane Pepper, Brian T. Cunningham, John Gerstenmaier, Peter Li, Jean Qiu, Homer Pien -
Patent number: 7300804Abstract: A method and apparatus for controlling the processing of a liquid sample, e.g., a blood sample, based on a measurement related to the sample's ability to coat a surface against which the sample is brought into contact while being routinely transported. Preferably, the sample is advanced through a tube, and the amount of sample residue remaining within the tube is measured and correlated to coating process subsequently carried out on the sample, e.g., a process for producing blood-smears on a microscope slide. In a preferred embodiment, the amount of sample residue in a blood-transport tube is used to control the motion profile (i.e., acceleration and velocity) of a drop-spreading member used to spread a blood drop on a microscope slide in an automated slide-making instrument.Type: GrantFiled: November 15, 2004Date of Patent: November 27, 2007Assignee: Beckman Coulter, Inc.Inventor: Jose Sellek-Prince
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Patent number: 7300805Abstract: Provided is a method of manufacturing a capacitor in a semiconductor device, comprising the steps of: forming a first metal film of noble series for the bottom electrode; forming a ferroelectric film on the first metal film; conducting a first thermal process on the resultant structure where the ferroelectric film is formed; conducting an ion implantation process on the resultant structure passing through the first thermal process; conducting a second thermal process on the resultant structure passing through the ion implantation process; forming a second metal layer of noble series for the top electrode on the ferroelectric film in the resultant structure passing through the first thermal process; and conducting a third thermal process on the resultant structure.Type: GrantFiled: May 10, 2005Date of Patent: November 27, 2007Assignee: Hynix Semiconductor Inc.Inventor: Young Ho Yang
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Patent number: 7300806Abstract: It is an object to provide fine particles of bismuth titanate having excellent dielectric characteristics, high crystallinity and a small particle diameter, and a process for their production. The object is accomplished by a process which comprises a step of obtaining a melt comprising, as represented by mol % based on oxides, from 23 to 72% of Bi2O3, from 4 to 64% of TiO2 and from 6 to 50% of B2O3, a step of quickly quenching this melt to obtain an amorphous material, a step of crystallization of bismuth titanate crystals from the above amorphous material, and a step of separating the bismuth titanate crystals from the obtained crystallized material, in this order.Type: GrantFiled: September 13, 2005Date of Patent: November 27, 2007Assignee: Asahi Glass Company, LimitedInventors: Yoshihisa Beppu, Kazuo Sunahara, Hiroyuki Tomonaga, Kumiko Takahashi
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Patent number: 7300807Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements.Type: GrantFiled: April 14, 2004Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Douglas D Coolbaugh, Hayden C. Cranford, Jr., Terence B. Hook, Anthony K. Stamper
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Optically pumped, surface-emitting semiconductor laser device and method for the manufacture thereof
Patent number: 7300808Abstract: The invention is directed to an optically pumped surface-emitting semiconductor laser device having at least one radiation-generating quantum well structure and at least one pump radiation source for optically pumping the quantum well structure, whereby the pump radiation source comprises an edge-emitting semiconductor structure. The radiation-generating quantum well structure and the edge-emitting semiconductor structure are epitaxially grown on a common substrate. A very efficient and uniform optical pumping of the radiation-generating quantum well structure is advantageously possible with this monolithically produced semiconductor laser device. Methods for manufacturing inventive semiconductor laser devices are also specified.Type: GrantFiled: July 29, 2004Date of Patent: November 27, 2007Assignee: Osram GmbHInventors: Tony Albrecht, Norbert Linder, Johann Luft -
Patent number: 7300809Abstract: A multilayer semiconductor laser includes a substrate on which is formed a semiconductor multilayer heterostructure divided into a plurality of electrically pumped regions and an elongated optically pumped region. The electrically pumped regions generate and deliver optical pump radiation laterally into the elongated optically pumped region. Output radiation is generated and delivered by the optically pumped region.Type: GrantFiled: July 29, 2005Date of Patent: November 27, 2007Assignee: Coherent, Inc.Inventors: Serguei G. Anikitchev, Hailong Zhou, R. Russel Austin
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Patent number: 7300810Abstract: A solid-state imaging device is provided in which noise to an image signal is restrained and miniaturization is facilitated in a peripheral circuit formation region. A solid-state imaging device includes a pixel formation region 4 and a peripheral circuit formation region 20 formed in the same semiconductor substrate; in the peripheral circuit formation region 20 a first element isolation portion is formed of an element isolation layer 21 in which an insulation layer is buried in a semiconductor substrate 10; in the pixel formation region 4 a second element isolation portion made of an element isolation region 11 formed inside the semiconductor substrate 10 and an element isolation layer 12 projecting upward from the semiconductor substrate 10 is formed; and a photoelectric conversion element 16 (14, 15) is formed extending to a position under the element isolation layer 12 of the second element isolation portion.Type: GrantFiled: November 16, 2006Date of Patent: November 27, 2007Assignee: Sony CorporationInventor: Ikuo Yoshihara
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Patent number: 7300811Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.Type: GrantFiled: November 8, 2005Date of Patent: November 27, 2007Assignee: Industrial Technology Research InstituteInventors: Yu-Cheng Chen, Chi-Lin Chen, Chi-Ming Chang
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Patent number: 7300812Abstract: This disclosure relates to lids and methods for forming and using them. One embodiment of these lids enables MEMS protected by the lids to be smaller. Another of these lids enables testing of a group of conjoined, lidded MEMS. Also, processes for forming and using these lids are also disclosed. One of these processes forms lids from a lid precursor residing over an assembly MEMS.Type: GrantFiled: October 29, 2004Date of Patent: November 27, 2007Assignee: Hewlett-Packard Development Coompany, L.P.Inventors: Chien-Hua Chen, David M. Craig, Charles C. Haluzak
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Patent number: 7300813Abstract: The present invention relates to the manufacture of a semiconductor switch for use in a variety of communication systems, and particularly to the manufacture of a RF micro-machined switch of pull-up type, wherein an electrostatic electrode is used so as to cause the contact pad involved in the operation of the switch to be pulled upward from below. The RF micro-machined switch of pull-up type according to the invention has a high isolation characteristic for shorting and opening the circuit and needs a low driving voltage, so that miniaturization of communication system is possible because a circuit for booting driving voltage is not required within the system. Further, the characteristic of switch is little changed after a long use because the metal composing the contact pad experiences little deformation during operation, whereby the semi-permanent use of switch is possible.Type: GrantFiled: September 20, 2005Date of Patent: November 27, 2007Assignee: Dongguk University Indusrty-Academic Cooperation FoundationInventors: Jin-Koo Rhee, Seong-Dae Lee
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Patent number: 7300814Abstract: A method of fabricating micro-mechanical devices. A mesa is etched in a homogeneous wafer. The wafer is bonded to a patterned substrate with the mesa defining device elements suspended above the substrate. A portion of the wafer is removed until a desired device thickness is achieved. Discrete elements of the device are then formed by performing a structural etch on the remaining wafer material.Type: GrantFiled: December 16, 2004Date of Patent: November 27, 2007Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Brian T. Cunningham, Marc S. Weinberg
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Patent number: 7300815Abstract: Described is a process to pattern adhesion and top contact layers in such a way that at least some portion of the top contact layers overlaps the adhesion layer, while another portion of the top contact layer overlaps with the bottom contacts, but does not overlap with the adhesion layer. The overlap between the top contact layer and the adhesion layer helps to hold the top contact layer onto the sacrificial layer. Because there is no overlap between the adhesion layer and the bottom contact, the removal of adhesion layer is no longer necessary, leading to better contacts and simplifying the fabrication process.Type: GrantFiled: April 25, 2005Date of Patent: November 27, 2007Assignee: Schneider Electric Industries SASInventors: Gordon Tam, Jun Shen
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Patent number: 7300816Abstract: The present invention is directed to a method of making flexible interconnect packaging, in particular, packaging for fingerprint sensor chips. The chip is mounted on a flexible substrate having conductive traces leading to a connector at an end of the substrate. Wires are used to connect contact pads with the conductive traces, and a rigid frame is mounted below the substrate and chip. The conductive traces are preferably internal within the substrate and are exposed by forming a cavity in the substrate adjacent to the chip. Also disclosed are electronic devices which incorporate the foregoing fingerprint sensing apparatus.Type: GrantFiled: May 20, 2005Date of Patent: November 27, 2007Assignee: Fujitsu LimitedInventor: Michael Manansala
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Patent number: 7300817Abstract: A semiconductor device includes a plurality of photoelectric conversion photodiodes provided on a silicon substrate, and a refractive index matching film provided on each of the photodiodes. The refractive index matching film is composed of an insulating compound layer represented by SiOxNy (0?x and y) assuming that the molar ratio of silicon, oxygen and nitrogen of the compound layer is 1:x:y. The oxygen content of the compound layer is the lowest at the silicon interface with each photodiode and the highest in an upper portion of the compound layer, and the nitrogen content is the highest at the silicon interface with each photodiode and the lowest in the upper portion of the compound layer. Therefore, multiple reflection can be decreased to improve light receiving sensitivity, as compared with a case in which a SiN single layer and a SiO2 single layer are laminated.Type: GrantFiled: October 27, 2004Date of Patent: November 27, 2007Assignee: Sony CorporationInventor: Ichiro Murakami
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Patent number: 7300818Abstract: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at least two adhering areas in the direction in which the adhesive tape is peeled. The porous member adheres to the semiconductor wafer by suction and fixes the wafer in place.Type: GrantFiled: September 23, 2005Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kurosawa, Shinya Takyu
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Patent number: 7300819Abstract: A method for mounting a semiconductor device, which can decrease the occurrence rate of failures, a method for repairing a semiconductor device, which can easily repair defective solder joints, and a semiconductor device which makes those methods feasible. A substrate 1 has formed therein through-holes 7 lined on the internal walls with a wiring layer 9, and solder balls 6 are fusion-bonded to the substrate 1 in such a manner as to cover the through-holes 7. In the mounting process or in the repair process, heating probes 41 are passed through the through-holes 7 and thrust into the solder balls 6 to thereby melt the solder balls, and the heating probes are pulled out of the solder balls to let the solder balls cool down. In those processes, only the solder balls 6 can be heated, thereby averting adverse effects on the IC chip 3. In the repair process, the solder balls 6 can be restored to an initial condition free of intermetallic compounds.Type: GrantFiled: June 29, 2005Date of Patent: November 27, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Takashi Noguchi
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Patent number: 7300820Abstract: An apparatus and method for an adhesive assembly for securing a printed circuit board to a substrate. The assembly provides a printing tool with a plurality of apertures defined therethrough. Preferably, the apertures have a top opening with a larger area than a bottom opening. The printing tool is placed upon one of the printed circuit board and/or substrate, and a liquid adhesive is printed onto the printing tool. The liquid adhesive forms islands of adhesive within each aperture. Removing the printing tool deforms each island to form a raised edge at a periphery of each island. A temporary liner can be placed on the raised edges to protect the adhesive until the printed circuit board can be assembled with the substrate.Type: GrantFiled: March 16, 2004Date of Patent: November 27, 2007Assignee: Temic Automotive of North America, Inc.Inventors: Jinbao Jiao, Kevin D. Moore, Thomas P. Gall, William C. Weigler
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Patent number: 7300821Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.Type: GrantFiled: August 31, 2004Date of Patent: November 27, 2007Assignee: Micron Technology, Inc.Inventors: Paul A. Farrar, Leonard Forbes, Kie Y. Ahn, Joseph E. Geusic, Arup Bhattacharyya, Alan R. Reinberg
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Patent number: 7300822Abstract: A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 22 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A heat spreader having parallel channels on opposite sides is attached to the chip carrier along the channels. The heat spreader has a second coefficient of thermal expansion that is smaller than or equal to the coefficient of thermal expansion of the chip carrier. The interplay between the heat spreader and the chip carrier can effectively reduce package warpage and maintain coplanarity within the specification.Type: GrantFiled: April 28, 2005Date of Patent: November 27, 2007Assignee: Altera CorporationInventor: Yuan Li
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Patent number: 7300823Abstract: Apparatus for housing a micromechanical structure, and a method for producing the housing. The apparatus has a substrate having a main side on which the micromechanical structure is formed, a photo-resist material structure surrounding the micromechanical structure to form a cavity together with the substrate between the substrate and the photo-resist material structure, wherein the cavity separates the micromechanical structure and the photo-resist material structure and has an opening, and a closure for closing the opening to close the cavity.Type: GrantFiled: November 17, 2004Date of Patent: November 27, 2007Assignee: Infineon Technologies AGInventors: Martin Franosch, Andreas Meckes, Winfried Nessler, Klaus-Gunter Oppermann
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Patent number: 7300824Abstract: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary substrate. With the surface of the chips coplanar with the surface of the complete structure without any gaps, interconnect metal lines can be easily placed on the uninterrupted surface, connecting the chips and other components.Type: GrantFiled: August 18, 2005Date of Patent: November 27, 2007Inventor: James Sheats
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Patent number: 7300825Abstract: Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.Type: GrantFiled: April 30, 2004Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Nancy Anne Greco, Stephen Edward Greco, Erik L. Hedberg
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Patent number: 7300826Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.Type: GrantFiled: September 29, 2004Date of Patent: November 27, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hisashi Ohtani
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Patent number: 7300827Abstract: A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a photoresist pattern to remove the conductive layer using a stripping composition and dissolving the conductive layer. The method of manufacturing a thin film transistor substrate is capable of improving an efficiency of manufacturing process of the thin film transistor substrate. In addition, the stripping composition is recycled.Type: GrantFiled: August 30, 2005Date of Patent: November 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sick Park, Shi-Yul Kim, Jong-Hyun Choung, Won-Suk Shin
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Patent number: 7300828Abstract: Disclosed is a photoresist film which is formed in a manner of covering at least a source electrode, a source line, a pixel electrode, a drain electrode, a drain line, a semiconductor film and a protective film, and further covering a gate insulting film in their vicinities. Moreover, wet and dry etchings are sequentially performed by using the photoresist film as a mask. Due to this etching, a residual pattern existing on the gate insulating film is etched.Type: GrantFiled: April 26, 2006Date of Patent: November 27, 2007Assignee: NEC LCD Technologies. Ltd.Inventors: Hideto Motoshima, Hisanobu Shimodozono, Junji Nishimoto, Makoto Horinouchi, Shouichi Sonohata
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Patent number: 7300829Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.Type: GrantFiled: June 2, 2003Date of Patent: November 27, 2007Assignee: Applied Materials, Inc.Inventors: Mark Hsiao, Dong-Kil Yim, Takako Takehara, Quanyuan Shang, William R. Harshbarger, Woong-Kwon Kim, Duk-Chul Yun, Youn-Gyung Chang
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Patent number: 7300830Abstract: A method of fabricating a liquid crystal display panel includes forming a first conductive layer on a substrate and patterning the first conductive layer using a first resist pattern printed on the first conductive layer to form a gate pattern. A semiconductor layer and a second conductive layer are stacked on a gate insulating film formed on the gate pattern. A second resist pattern having a stepped part printed on the second conductive layer forms a source/drain pattern of a transistor. A third resist pattern printed on a passivation film formed on the substrate patterns the film. A third conductive layer is formed on the patterned film and the third resist pattern and the third resist pattern is stripped to form a transparent electrode pattern including a pixel electrode connected to the drain electrode of the transistor.Type: GrantFiled: October 13, 2004Date of Patent: November 27, 2007Assignee: LG. Philips LCD Co., Ltd.Inventors: Soon Sung Yoo, Seung Hee Nam
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Patent number: 7300831Abstract: A polycrystalline silicon thin film transistor of a bottom gate structure is used as a switching element and a mask having transmissive, half-transmissive and blocking areas is used so that an array substrate for a liquid crystal display device having a monolithic driving circuit can be fabricated through a six-mask process.Type: GrantFiled: April 6, 2005Date of Patent: November 27, 2007Assignee: LG.Philips LCD Co., Ltd.Inventors: Kum-Mi Oh, Kwang-Sik Hwang
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Patent number: 7300832Abstract: A method of semiconductor device manufacture provided includes forming a gate insulating layer upon a single crystal semiconductor substrate, forming a gate electrode made from a polycrystal conductive film upon the gate insulating layer, implanting impurity in the gate electrode and in the surface layer of the semiconductor substrate adjacent to or separate from the gate electrode, performing a first heat treatment, and performing a second heat treatment. The first heat treatment performs heat treatment at a temperature that diffuses the impurity implanted mainly in the gate electrode and controls the diffusion of the impurity implanted in the surface layer of the semiconductor substrate. The second heat treatment performs heat treatment at a higher temperature and for a shorter time than the first heat treatment, and at a temperature that activates the impurity implanted in the semiconductor substrate.Type: GrantFiled: June 16, 2004Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Kyoichi Suguro
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Patent number: 7300833Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: October 27, 2006Date of Patent: November 27, 2007Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 7300834Abstract: Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed method includes forming a trench in a surface of a substrate to define a field area, forming a first conductive type well in a first active area of the substrate, forming a second conductive type well in a second active area of the substrate, and filling up the trench with a dielectric.Type: GrantFiled: December 28, 2004Date of Patent: November 27, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Dae Kyeun Kim
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Patent number: 7300835Abstract: A method of manufacturing a semiconductor device including forming a gate oxide layer, a first conductive layer, a capacitor dielectric layer, and a second conductive layer on a semiconductor substrate. The method also includes patterning the first and second conductive layers, the gate oxide layer, and the field oxide layer so as to form a gate pattern and a capacitor pattern; selectively wet-etching the first and second conductive layer so as to project out an outward part of the capacitor dielectric layer; implanting ions into the semiconductor substrate using the gate pattern and the protruding portion of the capacitor dielectric layer as an implantation mask; and removing the protruding portion of the capacitor dielectric layer so that the patterned capacitor dielectric layer has the same width as the gate electrode and the first capacitor electrode.Type: GrantFiled: December 23, 2005Date of Patent: November 27, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong-Wook Shin
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Patent number: 7300836Abstract: This invention is directed to a manufacturing method of a semiconductor device having a MOS transistor and a diffusion resistance layer formed on a same semiconductor substrate, where current leakage from the diffusion resistance layer is minimized. The manufacturing method of the semiconductor device of the invention has following features. That is, a CVD insulation film is formed on a whole surface of an n-type well including on a gate electrode and a p+-type diffusion resistance layer formed thereon. Then, a second photoresist layer is formed having an opening above a part of the diffusion resistance layer. By using this second photoresist layer as a mask, an anisotropic etching is performed to the CVD insulation film to form a sidewall spacer on a sidewall of the gate electrode.Type: GrantFiled: December 15, 2004Date of Patent: November 27, 2007Assignee: Sanyo Electric Co., Ltd.Inventor: Yoshihiko Miyawaki