Abstract: A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. The SiN mask is removed and then a breakthrough etch is applied to remove an underlying pad oxide layer. A PSG layer defining a width of each of the fins on a sidewall of each of the support structures is deposited on each of the support structures. At least two fins each having a narrow fin pitch of about 0.25 ?m. are formed. The fins provide a seed layer for at least two selective epitaxially raised source and drain regions, wherein each raised source-drain associated with each fin are interconnected thus forming a source pad and a drain pad.

Abstract: Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an electrode formed above the insulating film.

Abstract: A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

Abstract: A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the first dielectric layer, and a second dielectric layer with a capacitor opening is formed on the first dielectric layer, in which the capacitor opening is situated directly above the first damascene conductor. Next, an MIM capacitor having a top plate and a bottom plate is created within the capacitor opening, in which the bottom plate of the MIM capacitor is electrically connected to the first damascene conductor. Next, a third dielectric layer is deposited on the second dielectric layer and the MIM capacitor, and at least one second damascene conductor is formed within part of the third dielectric layer, in which the second damascene conductor is electrically connected to the top plate of the MIM capacitor.

Abstract: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction where the adjacent storage electrode is arranged. A dielectric layer is formed on the storage electrode. A plate electrode is formed on the dielectric layer.

Abstract: A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced.

Abstract: A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a stringer of a control gate, which is formed by the negative slope of the self-aligned floating gates, can be prevented. Furthermore, because an isotropic etch process is used to remove element isolation films between the floating gates, the element isolation films do not remain on the sides of the floating gates. It is thus possible to prevent loss of the coupling ratio. Accordingly, failure of devices can be reduced and decreasing the program speed can be prevented.

Abstract: A method of forming a gate of a flash memory device, including the steps of forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate, an isolation film in the field region, a dielectric layer, a second polysilicon layer, a metal silicide film, and a hard mask film on the structure, etching the hard mask film, the metal silicide film, and a given region of the second polysilicon layer to expose the dielectric layer, stripping a top surface of the exposed dielectric layer of the active region and the field region, a part of the first polysilicon layer of the active region to form dielectric layer horns, the first polysilicon layer and a part of the dielectric layer horns of the active region, and the first polysilicon layer and the dielectric layer horns of the active region.

Abstract: The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region including doping the cap layer with a pre-determined percentage of at least one element associated with the compound base region; and forming an emitter region over the cap layer.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: A method of producing a semiconductor component, e.g., a multilayer semiconductor component, and a semiconductor component produced by this method, where the semiconductor component has, e.g., a mobile mass, i.e., an oscillator structure. A method easily and inexpensively produce a micromechanical component having monocrystalline oscillator structures, such as an acceleration sensor or a rotational rate sensor for example, by surface micromechanics, a first porous layer is formed in the semiconductor component in a first step and a cavity, i.e., a cavern, is formed beneath or out of the first porous layer in the semiconductor component in a second step.

Abstract: In a method for the reversible oxidation protection of microcomponents, a substrate is provided, a silicon nitride layer is provided on the substrate in order to protect it against oxidation, an insulation layer is applied to the silicon nitride layer, and a reoxidation process is carried out. In the reoxidation process are generated oxygen radicals which are passed through the insulation layer to the silicon nitride layer in order to convert silicon nitride of the nitride layer into silicon dioxide.

Abstract: A process for detaching two layers of material according to a weakened zone defined between the layers. This process includes the thermal annealing of a structure that incorporates the layers, with the annealing bringing the temperature from a starting temperature to a final annealing temperature while evolving according to a first phase up to a transition temperature, then according to a second phase during which the rise in temperature per unit of time is greater than that of the first phase. The invention also concerns an application for using this process in a particular semiconductor fabrication technique.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A process and system for processing a thin film sample, as well as the thin film structure are provided. In particular, a beam generator can be controlled to emit successive irradiation beam pulses at a predetermined repetition rate. Each irradiation beam pulse may be masked to define a first plurality of beamlets and a second plurality of beamlets. The first and second plurality of beamlets of each of the irradiation pulses being provided for impinging the film sample and having an intensity which is sufficient to at least partially melt irradiated portions of the section of the film sample. A particular portion of the section of the film sample is irradiated with the first beamlets of a first pulse of the irradiated beam pulses to melt first areas of the particular portion, the first areas being at least partially melted, leaving first unirradiated regions between respective adjacent ones of the first areas, and being allowed to resolidify and crystallize.

Abstract: A plasma is produced in a treatment space (58) by diffusing a plasma gas at atmospheric pressure and subjecting it to an electric field created by two metallic electrodes (54,56) separated by a dielectric material (64), a precursor material is introduced into the treatment space to coat a substrate film or web (14) by vapor deposition or atomized spraying at atmospheric pressure. The deposited precursor is cured by electron-beam, infrared-light, visible-light, or ultraviolet-light radiation, as most appropriate for the particular material being deposited. Additional plasma post-treatment may be used to enhance the properties of the resulting coated products.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended material leads to formation of a conductor overlayed by an insulator such that after formation, the conductor is capable of carrying current from the first electronic device to the second electronic device and the insulator forms a protective layer over the conductor.

Abstract: High quality dielectric layers may be achieved without introducing excessive impurities when a semiconductor device is manufactured by a method that includes forming a lower wire layer on a structure above a semiconductor substrate, forming a silicon rich oxide layer having a refractive index of 0.45-1.55 on the lower wire layer and the structure, implanting carbon and oxygen (e.g., CO2) into the silicon rich oxide (SRO) layer, and forming an organosilicate glass layer by heat-treating the implanted SRO layer.

Abstract: An interposer and a method of manufacturing a flexible radio frequency (RF) type device having an IC and thin film circuits, such as an antenna. The device is made by using an easy-to-insert interposer subassembly with pre-positioned ICs to mechanically and electrically attach an IC to the thin film circuit. A method of mass producing radio frequency devices comprising antennas and ICs on interposers that are physically and electrically connected to the antennas using a pressure sensitive adhesive.

Abstract: A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

Abstract: An IC chip/substrate assembly bonded together by a non-conductive adhesive and a method for forming the assembly. The assembly consists of an IC chip that has bumps formed on an active surface, a substrate that has bond pads formed on a top surface, wherein at least one of the IC chip and the substrate has dummy bumps formed in-between the bumps or the bond pads, and a non-conductive adhesive disposed in between and bonding the IC chip and the substrate together in a face-to-face relationship with the bumps in electrical communication with the bond pads.

Abstract: A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively having a trench and a via contact hole; forming a barrier metal layer and a line metal layer on the interlayer insulating layer and in the dual damascene patterns; forming an anti-oxidation layer on above the line metal layer; and forming a metal line in the dual damascene patterns by planarizing an entire surface of the anti-oxidation layer.

Abstract: Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening. The capping layer and the dielectric layer are etched through the resist pattern to form the first interconnect opening. The resist pattern is removed and a barrier layer is applied over the capping layer and in the first interconnect opening. An interconnection is formed by filling the first interconnect opening with conductive material. The interconnection is planarized to remove excess material and a portion of the first dielectric layer damaged by the planarizing step is selectively etched. A second dielectric layer is applied to replace the damaged portion of the first dielectric.

Abstract: An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.

Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on a substrate by using an atomic layer deposition process (a vapor deposition process that includes a plurality of deposition cycles) with a refractory metal precursor compound, an organic amine, and an optional silicon precursor compound.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract: A method for manufacturing a semiconductor device using a dual-damascene pattern, where a photosensitive film is coated instead of a dielectric material, the photosensitive film is cured, and the photosensitive film is entirely etched. The method includes forming a first conductor on a first insulation film deposited on a semiconductor substrate, and depositing second, third, and fourth insulation films on the first insulation. The method also includes forming holes by selectively removing the fourth and third films, forming a fifth insulation film where the holes are filled with the fifth film, and forming a sixth insulation film on the fifth and fourth films. The method further includes forming a trench mask pattern on the sixth film, forming trench line holes and trench via holes using the pattern and forming a barrier metal film and a second conductor, where the line and via holes are filled with the second conductor.

Abstract: A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heteroleptic precursor compounds that include, for example, guanidinate, phosphoguanidinate, isoureate, thioisoureate, and/or selenoisoureate ligands using a vapor deposition process is provided.

Abstract: A method for chemical mechanical polishing of semiconductor substrates containing a metal layer requiring removal and metal interconnects utilizing a composition containing engineered copolymer molecules comprising hydrophilic functional groups and relatively less hydrophilic functional groups; the engineered copolymer molecules enabling contact-mediated reactions between the polishing pad surface and the substrate surface during CMP resulting in minimal dishing of the metal interconnects in the substrate.

Abstract: Metal residue on a semiconductor surface resulting from metal chemical mechanical polishing (“CMP”) process are eradicated using a dry clean process. The dry cleaning uniformly removes or substantially eliminates metal residue from the surface of the semiconductor. An unintended metal short that may be present due to the residue may thereby be eliminated by adjusting the dry cleaning process based on a type of dry cleaning material, and type and a thickness of the residue.

Abstract: A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.

Abstract: A method of manufacturing a semiconductor device that prevents formation of scratches and occurrence of dishing in a CMP process. The method includes forming a first film on a part of a semiconductor substrate, forming a second film all over the semiconductor substrate, and a CMP process utilizing a ceria slurry to planarize the second film using the first film as a mask, the CMP process including performing a first CMP until a portion of the first film is exposed and performing a second CMP. A first ceria slurry of a predetermined abrasive grain concentration is employed in the first CMP, and a second ceria slurry of lower abrasive grain concentration is employed in the the second CMP. The number of scratches is reduced by reducing the abrasive grain concentration of the ceria slurry, and dishing is prevented by reducing a polishing rate ratio between the first and second films.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: Manufacturing costs may be reduced and yield may be improved when metal wiring in a semiconductor device is fabricated by a disclosed method including: sequentially forming an etch stop layer, an intermetal insulation layer, an anti-reflection coating layer, and a mask pattern on a semiconductor substrate formed with a lower structure; etching the anti-reflection coating layer using the mask pattern; forming a trench by removing the intermetal insulation layer to a predetermined depth by performing wet etching using the mask pattern; forming a via hole by removing the remaining intermetal insulation layer and the etch stop layer by dry etching them using the mask pattern; and removing the mask pattern.

Abstract: A method of forming a fine pattern by a tri-layer resist process to overcome a bi-layer resist process is disclosed. When a fine pattern is formed using a silicon photoresist, a gas protection film is coated on a photoresist to prevent exhaustion of silicon gas generated from the photoresist in light examination of high energy. As a result, lens of exposure equipment may be prevented from being contaminated.

Abstract: A plasma etching is performed on a substrate having a pattern wherein an interval between neighboring openings formed on a resist mask is equal to or less than 200 nm, wherein the etching is performed by converting a processing gas comprising an active species generating gas which includes a compound having carbon and fluorine, and a nonreactive gas which includes xenon gas into a plasma. The nonreactive gas further includes argon gas.

Abstract: An etching method for plasma-etching a low-k film, wherein the plasma etching is conducted under an etching gas atmosphere including a fluorocarbon gas, O2 gas and Ar gas, and under the conditions of a pressure of 60 mTorr (7999.32 mPa) or higher and a high-frequency output (RF power) of 600 W or less.

Abstract: A method of forming a gate electrode (24?) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24?) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24?), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask.

Abstract: According to an aspect of the invention, there is provided a pattern forming method comprising forming an underlayer film on a film to be worked which has been formed on a semiconductor substrate, subjecting the underlayer film to an oxidizing treatment, forming an intermediate film which becomes a mask of the underlayer film, forming a resist film on the intermediate film, exposing the resist film to light to form a resist pattern, transferring the resist pattern onto the intermediate film to form an intermediate film pattern, and transferring the intermediate film pattern onto the underlayer film to form an underlayer film pattern.

Abstract: A film formation method for a semiconductor process is arranged to form a thin film on a target substrate by CVD, while supplying a first process gas for film formation and a second process gas for reacting with the first process gas to a process field accommodating the target substrate. The method alternately includes first to fourth steps. The first step performs supply of the first and second process gases to the process field. The second step stops supply of the first and second process gases to the process field. The third step performs supply of the second process gas to the process field while stopping supply of the first process gas to the process field. The fourth step stops supply of the first and second process gases to the process field.

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.