Abstract: An N-type epitaxial layer 115, which is formed above an N-type semiconductor substrate 114 in each of a pixel region and a peripheral circuit region; a first P-type well 1 formed above the N-type epitaxial layer 115 in the pixel region; and light receiving regions 117, which are formed within the first P-type well land each of which is a component of a photodiode, are included. The peripheral circuit region includes: second P-type wells 2, which are formed from a surface 200 of the peripheral circuit region to a desired depth and each of which is a component of an N-Channel MOS transistor; an N-type well 3 which is formed from the surface 200 of the peripheral circuit region to a desired depth and which is a component of a P-Channel MOS transistor; and a third P-type well 4 which is formed so as to have such a shape as to isolate the N-type well 3 from the N-type epitaxial layer 115 and which has a higher impurity concentration than that of the first P-type well 1.

Abstract: A method for manufacturing a semiconductor device, includes: forming a protrusive portion on a surface of a semiconductor substrate, forming a thin film on the surfaces of the semiconductor substrate and the protrusive portion, applying a resist on a surface of the thin film so that at least an apex of the protrusive portion on which the thin film is formed is exposed, etching the thin film formed on the apex of the protrusive portion which is exposed from the resist to separate a pattern of the thin film into a plurality of patterns of the thin film and removing the resist.

Abstract: A microelectromechanical system (MEMS) assembly includes a MEMS substrate having a plurality of MEMS devices, a plurality of bond pads, and a wafer cap. The wafer cap includes a unitary structure having a plurality of pockets and a plurality of apertures. The wafer cap is fixed to the MEMS substrate such that at least some of the MEMS devices are enclosed within respective enclosed cavities formed by the pockets and the MEMS substrate, and such that at least come of the apertures provide access to the bond pads from an exterior of the wafer cap.

Abstract: A MEMS device, for example a capacitive microphone, comprises a flexible membrane 11 that is free to move in response to pressure differences generated by sound waves. A first electrode 13 is mechanically coupled to the flexible membrane 11, and together form a first capacitive plate of the capacitive microphone device. A second electrode 23 is mechanically coupled to a generally rigid structural layer or back-plate 14, which together form a second capacitive plate of the capacitive microphone device. The capacitive microphone is formed on a substrate 1, for example a silicon wafer. A back-volume 33 is provided below the membrane 11, and is formed using a “back-etch” through the substrate 1. A first cavity 9 is located directly below the membrane 11, and is formed using a first sacrificial layer during the fabrication process. Interposed between the first and second electrodes 13 and 23 is a second cavity 17, which is formed using a second sacrificial layer during the fabrication process.

Abstract: Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456).

Abstract: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the electrode portion on the surface of the semiconductor chip. The electrode portion is placed in a position which does not overlap with the sensor element in the thickness direction of the semiconductor chip.

Abstract: The present invention relates to a semiconductor photodetector and the like that can be made adequately compact while maintaining mechanical strength. The semiconductor photodetector includes a structural body of layers and a glass substrate. The structural body of layers is arranged from an antireflection film, a high-concentration carrier layer of an n-type (first conductive type), a light absorbing layer of the n-type, and a cap layer of the n-type that are laminated successively. The glass substrate is adhered via a silicon oxide film onto the antireflection film side of the structural body of layers. The glass substrate is optically transparent to incident light.

Abstract: Elevated crystal silicon photosensors for imagers pixels, each photosensor formed of crystal silicon above the surface of a substrate that has pixel circuitry formed thereon. The imager has a high fill factor and good imaging properties due to the crystal silicon photosensor.

Abstract: A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap filling polymer layer opposite to the photo-diodes and a second polymer arranged on the interconnect layers covers and planarizes and passivates the color filter layers. On top of the planarizing polymer there is a plurality of micro-lenses opposite to the color filters, and a third polymer layer is deposited on the micro-lenses for passivating the micro-lenses. According to the invention the polymer materials are comprised of a siloxane polymer which gives thermally and mechanically stable, high index of refraction, dense dielectric films exhibiting high-cracking threshold, low pore volume and pore size.

Abstract: The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between a layer of n-type silicon and a layer of p-type silicon.

Abstract: A drive circuit has a level shift circuit which outputs level-shifted on and off signals each for controlling a power semiconductor element in an on or off state, a first RS flip flop which is supplied with the on signal through a setting input terminal and supplied with the off signal through a resetting input terminal, and which outputs a drive signal to the power semiconductor element, and a logic filter circuit which is provided between the level shift circuit and the first RS flip flop, and which blocks transmission of the on and off signals during the time period from a time at which both the on and off signals become a first logic to a time at which both the on and off signal become a second logic.

Abstract: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

Abstract: A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending from a storage node contact junction region to a channel region Line type gate patterns, each filling a predetermined portion of the trench of the individual recess pattern, is formed in a direction crossing a major axis of the active region in an upper portion of the individual channel region.

Abstract: The structure of the present invention comprises a semiconductor substrate and a trench region formed on the semiconductor substrate. The trench region includes an extended funnel portion in the vicinity of the semiconductor substrate surface. A device isolation layer is formed at the trench region. The device isolation layer includes a void formed at a lower level than the funnel portion. The sidewalls of the hard mask pattern and the internal walls of the trench region are etched to form a funnel portion with an extended trench region at the vicinity of the semiconductor substrate surface. Accordingly, the void in the trench region does not extend above a surface of the semiconductor substrate.

Abstract: An electrically programmable fuse is provided which includes a cathode, an anode, and a fuse link conductively connecting the cathode to the anode. The cathode, the anode and the fuse link each have a length in a direction of current between the anode and cathode. Each of the cathode, the anode and the fuse link also has a width in a direction transverse to the respective length. At a cathode junction where the cathode meets the fuse link, the width of the fuse link decreases substantially and abruptly relative to the width of the cathode. The width of the fuse link increases only gradually in a direction towards an anode junction where the fuse link meets the anode.

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract: A chamber for exposing a workpiece to charged particles includes a charged particle source for generating a stream of charged particles, a collimator configured to collimate and direct the stream of charged particles from the charged particle source along an axis, a beam digitizer downstream of the collimator configured to create a digital beam including groups of at least one charged particle by adjusting longitudinal spacing between the charged particles along the axis, a deflector downstream of the beam digitizer including a series of deflection stages disposed longitudinally along the axis to deflect the digital beams, and a workpiece stage downstream of the deflector configured to hold the workpiece.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.

Abstract: A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.

Abstract: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode material layer located over the piezoelectric material layer. The devices also include a layer of isolation material located over the second electrode material layer that at least one of chemically or electrically isolates a portion of the second electrode material layer from a fluid. Some devices include a layer of conductive material located over the layer of isolation material.

Abstract: An electrical component includes a conductive substrate, a tin layer formed on the substrate, and a conformal coating formed on the tin layer to impede tin whisker growth. The conformal coating comprises a polymer matrix having gas-filled voids dispersed therethrough. In a method for impeding tin whisker growth from a tin plating or finish formed over an electrical component, a gas is infused into a liquid polymer. The tin plating or finish is then covered with a conformal coating comprising the liquid polymer. Then, one or more of the temperature and pressure of the conformal coating are adjusted to thereby create a dispersion of gas-filled voids comprising the gas in the conformal coating.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a component having dielectric sub-layers are described.

Abstract: A semiconductor device, including an interlayer dielectric layer having a bonding pad and a fuse on a semiconductor substrate, the interlayer dielectric layer having a pad opening and a fuse opening exposing the bonding pad and the fuse, an organic passivation layer on the interlayer dielectric layer, and a fuse passivation layer covering the organic passivation layer, a side surface of the pad opening, a side surface of the fuse opening, and a bottom surface of the fuse opening.

Abstract: A semiconductor package structure includes a substrate, a chip module, a lead frame, and a bridging element. The chip module is electrically connected to the substrate. The lead frame is disposed beside one side of the substrate, and the lead frame has a projecting block unit. The bridging element has one side electrically connected with the chip module, and a first positioning unit formed on the other side thereof for electrically retaining with the projecting block unit. Moreover, the semiconductor package structure of the present invention is applied to a design of multi-chip package, and ensures that a bridging element is connected with a chip via the bridging element being retained by a lead frame. In addition, the junction between the bridging element and the lead frame do not cause displacement between the lead frame and the bridging element during the packaging process.

Abstract: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe) 204 has two planar surfaces and a cavity formed therein. The adhesive material 209 is configured to couple the semiconductor die 208 within the cavity of the conductive leadframe 204 such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Abstract: A package structure and a lead frame using the same are provided. The package structure includes a lead frame, a chip and an adhesive. The lead frame has a first surface and a second surface opposite to the first surface. The first surface has a chip adherent area. The lead frame includes a plurality of through holes and grooves. The through holes penetrate through the first surface and the second surface to be disposed around the chip adherent area. The grooves are disposed on the first surface. The grooves connect the neighboring through holes to form an annular trace disposed around the chip adherent area. The chip is disposed on the chip adherent area. The adhesive is disposed between the chip and the lead frame, and is diffused in the annular trace.

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices. The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general. For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with. For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract: A semiconductor device includes a semiconductor chip, an insulating base film and first projecting electrodes. The first projecting electrodes are formed in a single row on one face of the semiconductor chip along the edge of the semiconductor chip. This face of the semiconductor chip faces a semiconductor chip mounting face of the base film. The semiconductor device also includes second projecting electrodes formed in a single row outside the row of first projecting electrodes. The height of the second projecting electrodes is smaller than the first projecting electrodes. The semiconductor device also includes first inner leads formed on the semiconductor chip mounting face of the base film. The first inner lead extend to the first projecting electrodes. The semiconductor device also includes an insulating film formed between the first inner leads and the semiconductor chip. The semiconductor device also includes second inner leads formed on the insulating film.

Abstract: The disclosed subject matter includes a semiconductor optical device with a stable optical characteristic, an excellent radiant efficiency, and a high mounting reliability. A casing can be configured with a concaved-shaped cavity that includes an opening and a bottom portion. Each of one end portions of first/second lead frame electrodes 3a, 3b can be exposed on the bottom portion. The first one end portion can include an optical chip mounted thereon, and the second one end portion can be connected to another electrode of the optical chip via a bonding wire. The first lead frame electrode extends from an outside surface substantially perpendicular to the bottom portion and is bent in a direction towards the opening. The second lead frame electrode extends from an outside surface of the casing that is opposite to the outside surface from which the first electrode extends. Various physical configurations of the electrodes are disclosed.

Abstract: A semiconductor device comprises a die having a first surface and a second surface, a first leadframe connected to the first surface and the second surface, and a second leadframe connected to the first surface.

Abstract: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

Abstract: A multi-layer structure (102) includes a first build-up layer structure (202) configured to connect to a heat-generating module (120), a second build-up layer structure (206) configured to connect to a substrate, and a middle layer (204) provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component (110) and a heat spreader (130). A first set of thermal vias (210) extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias (2100 extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

Abstract: Disclosed are a semiconductor integrated circuit device, and a design and manufacturing method of the device, in which various semiconductor integrated circuit devices can be effectively designed and manufactured at low cost using a master slice method. A fixed layer used in common between Wire-Bonding (WB) chips and Flip-Chip (FC) chips is previously designed. When it is determined whether to form a WB chip or a FC chip, a variable layer for the WB chip or for the FC chip is designed. Based on this design, the WB chip or FC chip including the fixed layer and the variable layer added thereto is formed. Since the WB chip and the FC chip are differentially formed by the variable layer, the designing and manufacturing man-hour can be concentrated on the variable layer. Thus, reduction in TAT and in cost can be realized in design and manufacture of the device.

Abstract: A sensor device includes a board, a sensor element and a resin member made of resin. The sensor element has a displace part to be displaced in a predetermined detection direction, and detects a displace amount of the displace part in the detection direction. The sensor element is mounted and connected to the board through the resin member. The resin member is arranged between the sensor element and the board in part such that a warp of the sensor element in the detection direction due to a temperature variation is smaller than a warp of the sensor element in a direction except for the detection direction.

Abstract: An electronic component is provided with a base member 1 having a through hole 41 (43) extending from a bottom surface of a recess 15 to a back surface 11back, an electronic element 4 mounted in the recess 15, a lid member 2 closing an aperture of the recess 15, and an adhesive 3 (42) interposed between the lid member 2 and an opening end face of the recess 15, and obstructing the through hole 41 (43) to keep an interior space of the recess in a hermetically-sealed state; the adhesive 3 (42) obstructs a space between the lid member 2 and the base member 1, and the adhesive 3 (42) finally also obstructs the through hole 41 (43) extending from the bottom surface of the recess 15 to the back surface 11back so as to allow air, which could inhibit the obstruction, to escape during production.

Abstract: A system-in-package (SIP) device includes a substrate, a first chip and a chip package. The first chip is mounted and electrically connected to the substrate. The chip package is disposed above the first chip, and includes a leadframe, a second chip and a first encapsulant. The leadframe includes a die pad and a plurality of leads, wherein each lead is divided into an inner lead and an outer lead, and the outer lead is mounted and electrically connected to the substrate. The second chip is mounted on the die pad and electrically connected to the inner leads. The first encapsulant seals the second chip and a part of the leadframe, and exposes out the outer leads. The SIP device further includes a second encapsulant seals a part of the chip package, the first chip and the upper surface of the substrate, and exposes out the lower surface of the substrate.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: A circuit board stack structure embedded with semiconductor components includes two circuit boards, each of which having an opening; circuit layers formed on top and bottom surfaces of the circuit boards, each of the circuit layers having a plurality of conductive structures and electrical connecting pads; two semiconductor components embedded in the openings respectively, each of the semiconductor components having a plurality of electrode pads electrically connected to a portion of the conductive structures; a plurality of conductive bumps implanted on the electrical connecting pads of at least one of the circuit boards; and a plurality of solder balls formed on the electrical connecting pads on the other of the circuit boards that is free of the conductive bumps, allowing the conductive bumps of the one of the circuit boards to be engaged with the solder balls of the other of the circuit boards.

Abstract: A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically connected over the top substrate. Mounting the top package by the top substrate over the bottom substrate and electrically connecting the bottom and top substrates. Mounting system electrical connectors under the bottom substrate adjacent the bottom die.

Abstract: A semiconductor device includes an insulator substrate mounted on a base plate, the insulator substrate having an upper electrode, semiconductor chips mounted on the insulator substrate, external terminals for establishing external electrical connections of the semiconductor device, wires for establishing electrical connections among the external terminals, the upper electrode and the semiconductor chips, a case accommodating the insulator substrate, the semiconductor chips, the external terminals and the wires which are sealed by a sealing material filled in the case, a lid for protecting an upper part of the sealing material, and an insulative low electrification covering fitted on each wire, the low electrification covering having a lesser tendency to produce an electric charge buildup than the sealing material.

Abstract: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.

Abstract: A semiconductor device of the present invention is includes a semiconductor device comprising: a semiconductor chip having a passivation film on an electrode forming surface thereof on which a plurality of electrodes are formed; a protective film which is provided on an upper surface of the passivation film and patterned into a predetermined form; rewiring which is provided on an upper surface of each portion of the protective film divided by patterning and is connected to the electrode; a post connected to the rewiring; and a sealing resin layer which covers the rewiring.

Abstract: A semiconductor package which includes a conductive can, a semiconductor die received in the interior of the can and connected to an interior portion thereof at one of its sides, at least one interconnect structure formed on the other side of the semiconductor die, and a passivation layer disposed on the other side of the semiconductor die around the interconnect structure and extending at least to the can.

Abstract: A packaged integrated circuit device is disclosed, in which there are provided at least one pad formed at an active surface and a conductive line which is connected with a non-active surface along a lateral surface, so that a connection between the pad and the non-active surface is performed through a redistribution substrate. In the packaged integrated circuit device, an assembling work using a whole semiconductor substrate and productivity are enhanced. A foreign substance is prevented from being inputted into a sensor part formed on an active surface of a semiconductor substrate, and a small size package product can be possible. It is well applicable to the semiconductor products, which are designed to operate in accordance with external physical signals.

Abstract: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line, creating two small termination current loops conducting in opposite directions; using separate terminating impedances, which may be unequal, to control current in each of the loops; and arranging major axes of the termination current loops for a signal to be perpendicular to those of the isolation-target signal. Capacitive coupling adjustments include routing ground potential termination current return connections nearby the signal connection to shield it from the isolated signal line, using dual overlapping connections to shield each return path, and adjusting dielectric material proximity to the signal paths.

Abstract: An integrated circuit (IC) carrier assembly includes a printed circuit board (PCB). A carrier is soldered to the PCB. The carrier includes a grid of electrical contact islands surrounding a receiving zone for receiving an IC. Pairs of adjacent islands are interconnected by respective resilient suspension means. Each resilient suspension means includes a serpentine member. The IC received in the receiving zone is electrically coupled to some of the plurality of islands adjacent to the receiving zone.

Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: An MCM-D substrate in accordance with the present invention includes a silicon substrate provided with a Si-bump and a ground bump formed thereon, an insulating layer formed on the silicon substrate, a metal layer patterned on the insulating layer, a dielectric layer, a transmission line, a flip-chip bonding bump and a mounted component. The mount component is installed on a top of the Si-bump by a flip-chip bonding bump and the Si-bump prevents a dielectric layer from placing below the flip-chip bonding bump unlike a conventional technology. A ground bump makes an electric contact between a metal formed on a ground and a metal on the dielectric layer through a deep-via free process.