Abstract: An array substrate including a signal line, a test line to inspect the open of the signal line and fault of the pixels, and a fuse electrically connecting the signal line with the test line. The fuse is opened when a current higher than a reference current is applied thereto. Accordingly, a laser trimming process to insulate the signal line from the test line is not needed after the signal line and pixels have been tested, so that the processing time may be shortened.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

Abstract: A method of fabricating a p-type thin film transistor (TFT) includes: performing a first annealing process on a substrate to diffuse a metal catalyst through a capping layer into a surface of an amorphous silicon layer, and to crystallize the amorphous silicon layer to a polycrystalline silicon layer due to the diffused metal catalyst; removing the capping layer; patterning the polycrystalline silicon layer to form a semiconductor layer; forming a gate insulating layer and a gate electrode on the substrate; implanting p-type impurity ions into the semiconductor layer; and implanting a gettering material into the semiconductor layer and performing a second annealing process to remove the metal catalyst. Herein, the p-type impurity ions are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the gettering material is implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

Abstract: A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a <100> direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

Abstract: A method of manufacturing a semiconductor device, including forming a gate electrode or dummy gate on a fin-type silicon layer, introducing an impurity into the fin-type silicon layer with the gate electrode or dummy gate used as mask so as to form first impurity regions, etching the gate electrode or dummy gate so as to form a gate electrode or dummy gate having a reduced size, and introducing an impurity into the fin-type silicon layer with the gate electrode or dummy gate of the reduced size used as a mask so as to form second impurity regions positioned adjacent to the first impurity diffusion regions.

Abstract: The invention discloses a system for displaying images comprising an organic electroluminescent device. The organic electroluminescent device comprises a pixel area including a plurality of sub-pixels, a switching TFT having a first silicon layer with a first thickness and a driving TFT having a second silicon layer with a second thickness. Each sub-pixel includes a switching region with a switching TFT thereon and a driving region with a driving TFT thereon. Specifically, a difference between the first thickness and the second thickness at least exceeds 10%. Fabrication methods of the system are also provided.

Abstract: A thin film transistor array panel and a method of manufacturing the same include: a substrate; a data line formed on the substrate; a gate line intersecting the data line and including a gate electrode; a source electrode connected to the data line; a drain electrode opposite the source electrode; an organic semiconductor partly in contact with the source electrode and the drain electrode; a gate insulating member positioned between the gate electrode and the organic semiconductor; and an insulating bank having an opening where the organic semiconductor and the gate insulating member are positioned and is formed in a cross shape in which a horizontal part and a vertical part intersect.

Abstract: A TFT array substrate includes a gate line, a gate electrode, and a gate pad on a substrate, each of which including stacked layers of a first metal and a transparent conductive material, respectively, a pixel electrode formed of the transparent conductive material, a gate insulation layer on the substrate including the gate line and the gate electrode, the gate insulation layer having first and second open areas exposing the pixel electrode and the gate pad, a semiconductor layer formed on the gate insulation layer, a data line crossing the gate line to define a sub-pixel region, a source electrode diverging from the data line, a drain electrode spaced apart from the source electrode and connected to the pixel electrode, a data pad at an end of the data line; a masking layer covering the data line, the source electrode and the drain electrode, and an oxidation-prevention layer covering the gate pad and the data pad.

Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.

Abstract: A plurality of semiconductor layers including a light-emitting layer (14) are formed on the main surface of a substrate (10) which is composed of a group III-V nitride semiconductor. A first n-type semiconductor layer (12) containing indium is formed between the light-emitting layer (14) and the substrate (10), thereby reducing the affect of damage in the substrate surface. By having such a structure, there is realized a semiconductor light-emitting device having uniform characteristics.

Abstract: The light intensity emitted from a package is increased by adjusting a portion of the package encapsulant so that light impacting the side walls of the adjusted encapsulant portion will encounter total internal reflection (TIR) with the reflected light directed toward the top surface of the package. The adjusted portion of the package is positioned so that air can be used as the second (exterior) medium with the critical TIR angle being such that light emitted from a light source (such as from an LED die) will be directed primarily so as to escape the package from the top surface as opposed to being scattered internal to the package. In one embodiment, a lower portion of the encapsulant is surrounded by a casing to inwardly direct light from the light source that impacts the side of the encapsulant with an angle less than the critical TIR angle.

Abstract: A light emitting device having little variation in the intensity of light emitted from the light emitting surface is provided. The light emitting device of exemplary embodiments of the present invention 2 includes a laminated body with a first conductivity type layer and a second conductivity type layer, with a light emitting portion therebetween. The light emitting device also includes a metal thin film layer on the second conductivity type layer of the laminated body, and a transparent conductor on the metal thin film layer. The transparent conductor includes a single layer of transparent conductive film. The grain size in the light emitting surface of the transparent conductive film is not less than 30 nm and not greater than 300 nm.

Abstract: Briefly, the present disclosure provides a device comprising: a) an LED capable of emitting light at a first wavelength; b) a re-emitting semiconductor construction which comprises a potential well not located within a pn junction; and c) a reflector positioned to reflect light emitted from the LED onto the re-emitting semiconductor construction. Alternately, the device comprises: a) an LED capable of emitting light at a first wavelength; b) a re-emitting semiconductor construction capable of emitting light at a second wavelength which comprises at least one potential well not located within a pn junction; and c) a reflector which transmits light at said first wavelength and reflects at least a portion of light at said second wavelength.

Abstract: A nitride-based semiconductor LED comprises a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer formed on a predetermined region of the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the active layer; a p-electrode formed on the p-type nitride semiconductor layer, the p-electrode having a p-type branch electrode; a p-type ESD pad formed at the end of the p-type branch electrode, the p-type ESD pad having a larger width than the end of the p-type branch electrode; an n-electrode formed on the n-type nitride semiconductor layer, on which the active layer is not formed, the n-electrode having an n-type branch electrode; and an n-type ESD pad formed at the end of the n-type branch electrode, the n-type ESD pad having a larger width than the end of the n-type branch electrode.

Abstract: A light emitting diode (LED) chip including: a substrate; and a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, sequentially deposited on the substrate, in which when a length of the substrate is L and a width of the substrate is W, L/W>10.

Abstract: An organic light emitting device includes a first electrode disposed on a first substrate and comprising an emission area and an non-emission area, a plurality of barrier ribs located on a portion of the non-emission area of the first electrode, each barrier rib having an overhang structure, auxiliary electrodes disposed on a portion of a lower part of the barrier ribs and electically contacting the first electrode, an emission layer disposed on the emission area of the first electrode and a second electrode disposed on the emission layer.

Abstract: Provided is a novel structure of an active matrix TFT backplane. In order to form an auxiliary capacitor by a pixel electrode or a drain electrode of a TFT connected therewith, a base metal layer is formed on a glass substrate and a substrate insulating layer is formed on an entire surface thereof. By the structure, position alignment of the drain electrode with a counter electrode is unnecessary. An area for electrical capacitor formation is determined by size precision of the drain electrode, so a variation in electrical capacitance is suppressed to a small value.

Abstract: A light emitting device has a mount with a protruding portion that has an element mounting surface on which a light emitting element is mounted and a first lead and a second lead are exposed. The light emitting element has a first electrode and a second electrode that are electrically connected to the first lead and the second lead, respectively.

Abstract: There is provided a highly reliable semiconductor light emitting device in which disconnection of wires does not occur in case that a semiconductor light emitting device capable of being used in place of incandescent lamps or fluorescent lamps is formed in a monolithic type by forming a plurality of light emitting units on one substrate. A plurality of light emitting units (1) are formed by electrically separating a semiconductor lamination portion (17) which is so formed on a substrate (11) as to form a light emitting layer, and the light emitting units (1) are respectively connected in series and/or parallel by wiring films (3). For obtaining the light emitting units (1) from the semiconductor lamination portion a separation groove (17a) and an insulation film (21) deposited in the separation groove (17a) are formed in the semiconductor lamination portion (17).

Abstract: An object of the present invention is to provide a method of producing a Group III nitride semiconductor stacked structure which is useful for the production of reliable and excellent Group III nitride semiconductor light emitting devices having low forward voltage and small temporal changes in the forward voltage without lowering the light emitting output by keeping an excellent crystallinity of the light emitting layer and improving the crystallinity of the p-type layer. In the inventive method of producing a Group III nitride semiconductor stacked structure, the stacked structure has an n-type underlying layer, an active layer, a p-type cladding layer and a p-type contact layer, each comprising a Group III nitride semiconductor, in this order on a substrate, wherein the p-type contact layer is grown at two or more temperature ranges of substrate temperature, and the temperature range at the later growth is higher than that at the first growth.

Abstract: Low profile, side-emitting LEDs are described, where all light is efficiently emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED is a flip chip with the n and p electrodes on the same side of the LED, and the LED is mounted electrode-side down on a submount. A reflector is provided on the top surface of the LED so that light impinging on the reflector is reflected back toward the active layer and eventually exits through a side surface of the LED. A waveguide layer and/or one or more phosphors layers are deposed between the semiconductor layers and the reflector for increasing the side emission area for increased efficiency. Side-emitting LEDs with a thickness of between 0.2-0.4 mm can be created.

Abstract: A light emitting device including a multi-layer stack and an encapsulant layer having a patterned encapsulant region in optical proximity to a luminous stack surface of the multi-layer stack is disclosed. A method of making that encapsulant layer and of affixing that encapsulant layer to a luminous stack surface is also disclosed.

Abstract: A method for fabricating semiconductor and electronic devices at the wafer level is described. In this method, dielectric material is used to wafer bond a device wafer to a submount wafer, after which vias can be structured into the submount wafer and dielectric bonding material to access contact pads on the bonded surface of the device wafer. The vias may subsequently be filled with electrically and thermally conducting material to provide electrical contacts to the device and improve the thermal properties of the finished device, respectively. The post-bonding process described provides a simple, cost-effective, non-alignment method for fabricating a variety of electronic and semiconductor devices, particularly light emitting diodes with electrical contacts at the bottom of the chip.

Abstract: A light source is provided comprising an LED component having an emitting surface, which may comprise: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which comprises a second potential well not located within a pn junction having an emitting surface; or which may alternately comprise a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally comprises a converging optical element.

Abstract: Light emitting diodes include a substrate having first and second opposing faces and that is transparent to optical radiation in a predetermined wavelength range and that is patterned to define, in cross-section, a plurality of pedestals that extend into the substrate from the first face towards the second face. A diode region on the second face is configured to emit light in the predetermined wavelength range, into the substrate upon application of voltage across the diode region. A mounting support on the diode region, opposite the substrate is configured to support the diode region, such that the light that is emitted from the diode region into the substrate, is emitted from the first face upon application of voltage across the diode region.

Abstract: A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.

Abstract: An LED comprises a multilayered light-generating semiconductor region grown on one of a pair of opposite major surfaces of a semiconducting silicon substrate, a bonding pad overlying the light-generating semiconductor region and received in part in a cavity formed centrally therein, and a substrate electrode on the other major surface of the substrate. For protecting the LED from voltage spikes or like transients, an overvoltage protector such as a Schottky barrier diode is interposed between the bonding pad and the substrate. Further, for a uniform current distribution throughout the light-generating semiconductor region, a current-spreading film of electrically conducting, optically transparent material overlies the light-generating semiconductor region and itself covered by a transparent overlay of electrically insulating material. The bonding pad is electrically coupled to the current-spreading film via a plurality of connector strips extending radially from the pad over the transparent overlay.

Abstract: A light emitting device includes a semiconductor structure having a light emitting layer disposed between an n-type region and a p-type region. A porous region is disposed between the light emitting layer and a contact electrically connected to one of the n-type region and the p-type region. The porous region scatters light away from the absorbing contact, which may improve light extraction from the device. In some embodiments the porous region is an n-type semiconductor material such as GaN or GaP.

Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

Abstract: A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof. In addition, highly efficient operation of the drain pump (200) can be achieved by enabling and disabling the drain pump (200) in response to the high voltage level to provide an output signal at a relatively constant high voltage level. The drain pump (200) is enabled in response to a high voltage detector (202, 402, 502) detecting a high voltage level lower than a first predetermined voltage level and is disabled in response to detecting a voltage level higher than a second predetermined voltage level, the second predetermined voltage level being higher than the first predetermined voltage level.

Abstract: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap away from ion conducting part 4. Second electrode 2 supplies metal ions to the ion conductor, or receives the metal ions from the ion conductor to precipitate metal corresponding to the metal ions.

Abstract: Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.

Abstract: Structures and methods for forming the same. A semiconductor fabrication method comprises a step of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a capacitor electrode on the semiconductor substrate. The capacitor electrode comprises dopants, and is electrically insulated from the semiconductor substrate by a capacitor dielectric layer. The semiconductor structure further includes a semiconductor layer on the semiconductor substrate. The semiconductor layer comprises a trench which partially but not completely overlaps the capacitor electrode. The method further comprises the step of causing some of the dopants of the capacitor electrode to diffuse into the semiconductor layer, resulting in a doped source/drain region. The doped source/drain region overlaps the capacitor electrode and abuts a sidewall of the trench.

Abstract: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

Abstract: A method for making a high electron mobility field-effect transistor device, including the following steps: providing a layered semiconductor structure that includes an InGaAs channel layer and at least two layers over the channel layer, the at least two layers including a layer of InAlAs, a portion of which has an InGaAs cap layer deposited thereon; depositing spaced apart source and drain ohmic contacts on the InGaAs cap layer, the source and drain contacts comprising Ge/Ag/Ni contacts; and depositing a gate contact, between the source and drain contacts, on the InAlAs layer.

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

Abstract: A light emitting transistor comprises a first conductivity-type collector layer formed on a substrate; a second conductivity-type base layer formed on a predetermine region of the collector layer; a collector electrode formed on the collector layer where the base layer is not formed; a first conductivity-type emitter layer formed on a predetermine region of the base layer; a base electrode formed on the base layer where the emitter layer is not formed; an emitter electrode formed on the emitter layer; a first activation layer formed between the collector layer and the base layer; and a second activation layer formed between the base layer and the emitter layer.

Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In a first embodiment, a BE-SONOS sub-gate-AND array architecture is constructed multiple columns of SONONOS devices with sub-gate lines and diffusion bitlines. In a second embodiment, a BE-SONOS sub-gate-inversion-bitline-AND architecture is constructed multiple columns of SONONOS devices with sub-gate inversion bitlines and with no diffusion bitlines.

Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface.

Abstract: Disclosed is a phase-change memory device including a phase-change material pattern, a diffusion barrier layer, a bottom electrode and a top electrode. The phase-change material pattern is placed on the bottom electrode, and the diffusion barrier layer containing tellurium is placed on the phase-change material pattern. The top electrode containing titanium is placed on the diffusion barrier layer. The diffusion barrier layer acts to inhibit diffusion of titanium from the top electrode into the phase-change material pattern.

Abstract: A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

Abstract: An optical semiconductor device containing a photodiode, includes a first semiconductor layer of a first conductive type; and a channel layer of a second conductive type formed from a surface portion of the first semiconductor layer in a light receiving region. The channel layer and the first semiconductor layer in the light receiving region form a p-n junction region.

Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0<y?1) which have different respective Germanium contents, comprising the steps of: a) formation on a substrate covered with a plurality of Si1-yGey based semi-conducting zones (where 0<x<1 and x<y) and identical compositions, of at least one mask comprising a set of masking blocks, wherein the masking blocks respectively cover at least one semi-conducting zone of the said plurality of semi-conducting zones, wherein several of said masking blocks have different thicknesses and/or are based on different materials, b) oxidation of the semi-conducting zones of the said plurality of semi-conducting zones through said mask.

Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.

Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.