Abstract: Enhancement of the power conversion efficiency and reduction of switching noise of a power supply circuit are achieved. The power supply circuit includes, on the primary side, a composite resonance type converter formed from a current resonance type converter and a partial voltage resonance circuit in combination, and is configured so as to produce a plurality of secondary side DC output voltages. A particular one of the plural secondary side DC output voltages is controlled to a constant voltage by variably controlling the switching frequency of a primary side switching converter. Each of the remaining secondary side DC output voltages is controlled to a constant voltage by adjusting the level of control current to be supplied to a controlling winding of a control transformer in response to the level of the secondary side DC output voltage to adjust the inductance of a controlling winding of the control transformer inserted in a rectification current path.

Abstract: An output voltage circuit for power supply aims to arrange output DC power according to component voltage and equalizing current. The power supply has a voltage transformation circuit which consists of transformers each has at least one high voltage power and one low voltage power. The high voltage power output from each transformer is coupled in parallel and integrated on the same line to be output to a load at the rear end. Each low voltage power is output through a single line to another load at the rear end. Thus the load of the transformers is reduced and a desired electricity condition can be maintained.

Abstract: The invention presents a switching power control circuit including two levels of under voltage lockout to improve the protection of the power supply. An input terminal of control circuit is connected to a supplied capacitor to supply the power of the control circuit. The supplied capacitor is charged through a start resistor for the start-up. Once the input voltage reaches a start-up voltage, the control circuit will start the operation. After that, the power is further supplied from a transformer of the power supply. If a fault condition is occurred, the switching of the control circuit will be stop and the supplied capacitor will be discharged. When the input voltage is discharged lower than a first under-voltage lockout threshold, the circuits of control circuit are shut down to consume lower power. Furthermore, once the input voltage is discharged lower than a second under-voltage lockout threshold, the control circuit will enable the start-up again.

Abstract: A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and are used to adjust the slew rate of the boosting circuit. The closed-loop control and adjustable slew rate improve the accuracy and predictability of the boosting circuit's final boosted output voltage.

Abstract: This invention provides a power conversion circuit control apparatus which rapidly detects the voltage amplitude and phase of each phase, corrects the output of a current controller by the mean voltage amplitude and mean phase, and corrects, on the basis of the voltage amplitude and phase of each phase, a voltage amplitude command and voltage phase command to be applied to pulse width modulation. The apparatus can suppress an overcurrent even when the AC voltage is unbalanced, and restart the operation without generating any overcurrent when the circuit is to be reactivated.

Abstract: AC-to-AC power conversion systems and methods are presented, in which a small number of asymmetrical power switching devices are used to convert input AC power to output AC power of constant or variable frequency.

Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Abstract: A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

Abstract: A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.

Abstract: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request.

Abstract: A nitride read-only memory (NROM) device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system util

Abstract: Disclosed is a semiconductor device including a memory cell array, word lines, bit lines, and a signal difference determination circuit. In the memory cell array, memory cells each formed by connecting a MOS transistor and resistor in series are arranged in a matrix. The word lines are connected to the gates of the MOS transistors of the memory cells in the same row of the memory cell array. The bit lines are provided so as to correspond to the columns of the memory cell array. Each bit line is connected to one terminal of a corresponding one of the resistors of the memory cells in the same column. The signal difference determination circuit compares two output signals read to two bit lines from a pair of memory cells, thereby determining stored information in the pair of memory cells.

Abstract: A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as a read only memory (ROM).

Abstract: A memory cell (310) for a magnetic memory device (300) includes a free layer (311), a cap layer, an antiferromagnetic layer, and a synthetic antiferromagnetic layer which comprises two or more than two ferromagnetic layers that are antiferromagnetically coupled through non-magnetic space layers. The synthetic antiferromagnetic layer is pinned by antiferromagnetic layer. The antiferromagnetic layer and the synthetic antiferromagnetic layer form a synthetic antiferromagnetic pinned (SAFP) recording layer. The magnetization of the SAFP recording layer can be changed by combining a heating process and an external field induced from currents flowing along the bit line (320) and the word line (330). Therefore, a MRAM with high density, high thermal stability, low power dissipation and high heat tolerance can be achieved after introducing the SAFP recording layer due to the high volume and anisotropy energy of the SAFP recording layer.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

Abstract: A NAND flash memory device, and more particularly, to NAND flash memory device and method of manufacturing operating the same as described. A dielectric film and a conduction layer are formed between cell gates so that between-cell gates are buried. Therefore, an interference effect between floating gates, which becomes profound with the level of integration increasing, and program threshold voltage distributions between cells can be improved.

Abstract: A float gate memory device comprises a bottom word line, a float channel layer formed on the bottom word line and kept at a floating state, a float gate, and a top word line formed on the float gate in parallel with the bottom word line. In the float gate formed on the float channel, data are stored. Here, data are written in the float gate depending on levels of the bottom word line and the top word line, and different channel resistances are induced to the float channel depending on polarity states of charges stored in the float gate, so that data are read. As a result, in the float gate memory device, a retention characteristic is improved, and cell integrated capacity is also increased due to a plurality of float gate cell arrays deposited vertically using a plurality of cell oxide layers.

Abstract: A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.

Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Abstract: A method for programming a non-volatile memory device includes applying a first program-verify voltage to a first word line to determine whether or not memory cells associated with the first word line have been programmed successfully. A second program-verify voltage is applied to a second word line to determine whether or not memory cells associated with the second word line have been programmed successfully. The second program-verify voltage is different from the first program-verify voltage. The first and second word lines are associated with the same word line switching unit.

Abstract: Errors can occur when reading the threshold voltage of a programmed non-volatile storage element due to at least two mechanisms: (1) capacitive coupling between neighboring floating gates and (2) changing conductivity of the channel area after programming (referred to as back pattern effect). To account for coupling between neighboring floating gates, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. To account for the back pattern effect, a first voltage is used during a verify operation for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. The combination of these two techniques provides for more accurate storage and retrieval of data.

Abstract: A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making timing of generation of a signal for controlling the normal operation and a signal for controlling the refresh operation different from each other.

Abstract: A semiconductor device includes a first memory block having a first address space, a second memory block having a second address space which is smaller than the first address space, and a test circuit which supplies a test address and a test control signal to the first memory block and the second memory block, and tests the first memory block and the second memory block simultaneously. The second memory block has a storage circuit which stores an address corresponding to the second address space, and a control circuit which inactivates the test control signal when the test address falls outside the second address space.

Abstract: A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.

Abstract: A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.

Abstract: The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing data stored in the array of storage cells are either true or inverted, a plurality of read-toggle drivers coupled on a plurality of data output paths for inverting the data outputs only when the mode bit indicates that the array of storage cells are storing inverted data, and a plurality of write-toggle drivers coupled on a plurality of data input paths for inverting the data inputs only when the mode bit indicates that the array of storage cells are storing inverted data and for writing back inverted data into the array of storage cells during a refreshing cycle.

Abstract: A method and circuit for preventing the overprogramming of a memory cell. A fuse circuit is operable to be blown. A combinational logic circuit receives a signal from the fuse circuit, indicating whether or not the fuse has been blown, and controls the programming of the memory cell. The programming of the memory cell is prevented if the fuse circuit has been blown.

Abstract: An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external clock to output an internal clock; a unit delaying set for sequentially delaying the internal clock to output a plurality of delayed clocks; a phase detecting block for detecting logic levels of the delayed clocks at a rising edge of the internal clock to output phase detecting signals; a sampling pulse generator for outputting a sampling signal generated at a predetermined point of the internal clock; a latching block for outputting a phase detection latch signal by sampling and latching the phase detection signal at a point of the sampling signal being inputted; and a frequency detection block for outputting the frequency detection signal by logically combining the phase detection latch signal.

Abstract: A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit configured to control the page address control signal depending on transition of a sense detecting signal for notifying end of operation of a bit line sense amplifier, and a column control unit configured to generate a column selecting signal in response to the page address control signal when the page address detecting signal is activated.

Abstract: A method of characterizing shear wave anisotropy in a formation includes obtaining crossed-dipole waveforms from a borehole penetrating the formation over a range of depths and frequencies, determining far-field slowness in a fast-shear and slow-shear direction using a low-frequency portion of the crossed-dipole waveforms, and determining near-wellbore slowness in the fast-shear and slow-shear directions using a high-frequency portion of the crossed-dipole waveforms. The method also includes marking a selected depth of the formation as having intrinsic anisotropy if at the selected depth the far-field slowness in the fast-shear direction is less than the far-field slowness in the slow-shear direction and the near-wellbore slowness in the fast-shear direction is less than the near-wellbore slowness in the slow-shear direction.

Abstract: An undersea communications system in which a message is converted to a redundant fixed-length data packet and transmitted acoustically as a quadrature phase-keyed signal in a frequency band with a continuous pilot signal at a frequency closely adjacent to the frequency band. A receiver uses the received continuous pilot signal to Doppler compensate the incoming quadrature phase keyed signal by estimating any Doppler distortion in the received pilot signal. The resultant redundant signals are then robustly processed coherently and jointly by the adaptive decision feedback equalizer and decoder to provide the original transmitted data.

Abstract: A marine seismic exploration method and system comprised of continuous recording, self-contained ocean bottom pods characterized by low profile casings. An external bumper is provided to promote ocean bottom coupling and prevent fishing net entrapment. Pods are tethered together with flexible, non-rigid, non-conducting cable used to control pod deployment. Pods are deployed and retrieved from a boat deck configured to have a storage system and a handling system to attach pods to cable on-the-fly. The storage system is a juke box configuration of slots wherein individual pods are randomly stored in the slots to permit data extraction, charging, testing and synchronizing without opening the pods. A pod may include an inertial navigation system to determine ocean floor location and a rubidium clock for timing. The system includes mathematical gimballing. The cable may include shear couplings designed to automatically shear apart if a certain level of cable tension is reached.

Abstract: A mechanical-type watch movement is disclosed. In one implementation, the movement may include a frame. The frame may support a work train that is periodically driven in rotation by a driving element. The frame may also support an animation part. The animation part may be configured to be visible, and may be arranged to be animated by an oscillating movement that is capable of simulating, for example, a pendulum movement. The movement may also include, supported by the frame, an animation train that meshes with a mobile of the work train, and is kinematically connected to the animation part.

Abstract: An actuator and a method of operating an optical pickup of an optical disk drive comprises a blade on which an object lens is mounted, a plurality of magnets for generating a magnetic field, a plurality of focusing coils for interacting with the magnetic field generated at the magnets to move the blade in a first direction, a tracking coil for interacting with the magnetic field generated at the magnets to move the blade in a second direction, a first supporting member for supporting the blade so that the blade is tilted by the difference in electromagnetic forces which are generated between the magnets and the focusing coils, and a second supporting member connected to the first supporting member, for movably supporting the blade in the first and the second directions. Accordingly, the blade tilts in the tangential direction by adjusting the electric current supplied to the focusing coil.

Abstract: Even in an optical disk which includes, within a single disk, plural record areas whose track-pitches differ from each other, a tracking parameter is adjusted in a short time and with a high accuracy. At first, an optical pickup for reading information recorded in the optical disk is displaced into a reference track-pitch area which is one of the plural record areas of the optical disk. Moreover, the tracking gain is adjusted so that the tracking servo gain in this area may exhibit a predetermined characteristic. Also, the value thus acquired is recorded into, e.g., a non-volatile memory. After that, based on the tracking parameter learned/adjusted in the reference track-pitch area, the tracking parameter in another track-pitch area is calculated using the track-pitch ratio therebetween. Thereby it becomes possible to adjust the tracking parameter in a short time and with a high accuracy.

Abstract: A method and apparatus for tracking error detection in an optical disk reproduction system. The tracking error detecting apparatus generates a tracking error signal as a difference signal of optical detection signals generated by more than two optical detectors positioned along a diagonal line from a track center and includes binarizers which binarize each output of the optical detectors, phase locked loops (PLLs) which generate respective clock signals synchronized with the outputs of each of the binarizers, a phase difference detector which detects a phase difference between the synchronized signals output from the PLLs, and low-pass filters which filter the output of the phase difference detector to output the result as the tracking error signal. The tracking error detecting apparatus generates a tracking error signal which is not dependent on the lengths of pits or marks recorded on an optical disk, enhancing the reliability of the tracking error signal.

Abstract: A data demodulation process rate is varied according to a reproduction state, thereby reducing power consumption while maintaining a reading performance in a favorable state. A channel rate process data demodulation device performs a data demodulation process by employing channel bit frequency. Further, a half rate process data demodulation device performs a data demodulation process by employing frequency half as high as the channel bit frequency. These devices demodulate digital data from an optical recording medium. A process rate switching device switches a process rate at data demodulation, whereby demodulation is performed by switching between the data demodulation devices according to a quality of a reproduction signal, so as to reproduce the digital data recorded on the optical recording medium.

Abstract: Method for controlling a laser power used in recording on an optical disk includes: causing the laser to emit a test light emission pattern including a multipulse light emission interval and an at-bottom value continuous light emission interval; receiving the test light emission pattern of the laser to convert the pattern to an electric signal and to thereby obtain a light detection signal; calculating a detection value of a multipulse average value from the average value of the light detection signal, and calculating a bottom detection value from the light detection signal to obtain a light emission power characteristic of the laser on a supplied current based on the detection value of the multipulse average value and the bottom detection value; and controlling the current supplied to the laser based on the light emission power characteristic on the current supplied to the laser.

Abstract: A CD-R/RW drive (optical storage carrier player) includes an access device for writing data on a CD (optical storage carrier). The CD includes a central portion, an inner power calibration area which can provide the optical power calibration 100 times, a data storage area for data writing by a user and a last possible lead-out area, in order from CD center to CD outer edge. The method is to define an outer power calibration area in the last possible lead-out area to perform optical power calibration in this outer power calibration area such that the total number of optical power calibrations for the CD can exceed 100.

Abstract: A tilt sensor 23 is provided on a CD optical pickup 11, and a sub-chassis 24 and a height adjustment mechanism 25 and the like are provided for adjusting the tilt of a DVD optical pickup 12. A recording or reproduction position is read in by the DVD optical pickup 12 while moving the CD optical pickup 11 and the DVD optical pickup 12 along guide shafts 18 and 26 respectively, the amount of tilt of the optical disk 16 at this position is detected by the tilt sensor 23 of the CD optical pickup 11, the tilt of the laser light axis from the DVD optical pickup 12 is adjusted in accordance with the amount of tilt that is detected, and the amount of tilt of the optical disk 16 is corrected.

Abstract: A method for optical drive decoding of address in pre-groove (ADIP) data is provided to decode an input wobble signal to an ADIP unit signal. The method includes generating a wobble carrier frequency signal having the same phase with the wobble signal, multiplying the wobble carrier frequency signal by the input wobble signal to generate a product signal, accumulating the value of the product signal in each clock to generate a quotient summation signal, determining the phase change of the input wobble signal according to the value of the quotient summation to generate a phase change signal, and generating the ADIP unit signal by comparing the phase change signal with a plurality of ADIP patterns.

Abstract: This invention provides an optical disk device comprising an optical pick-up being structured to irradiate light beams onto an optical disk through an objective lens unit, receive the light beams reflected from the optical disk by a two-divided light-receiving element, convert amounts of light received by each segment of the light-receiving element into electrical outputs, and detect differential signals between the electrical outputs, a spherical aberration adjustment device for changing spherical aberration of light emitted from the objective lens, a detection device for detecting control signals for the adjustment device to minimize asymmetry of the deterioration degree of the differential signal amplitude detected when a light beam is defocused at any desired position on the radius of the optical disk, and a memory device for storing the control signals corresponding to the positions on the radius.

Abstract: A storage device includes a probe and a storage medium having a plurality of storage cells. The probe is able to form a first structure and a second structure in the storage medium, where a first storage cell containing a transition between the first structure and a second structure contains a data bit having a first state, and where a second storage cell not including a transition between the first structure and the second structure contains a data bit having a second state.