Abstract: A trap vector containing a loxP sequence composed of inverted repeat sequence 1, a spacer sequence and inverted repeat sequence 2 in this order, the loxP sequence being a mutant loxP wherein a part of the inverted repeat sequence 1 or 2 is mutated.

Abstract: The present invention relates to Lactobacillus species recombinantly altered to express a biologically active protein. The invention also related to methods of providing the bacteria to the vagina.

Abstract: The present invention provides a cell line which can be substituted for ? cells in human mature pancreatic islets and express insulin in a glucose-concentration dependent manner, and enables the easy obtainment of the number of cells which meets the demand. The present invention also provides a therapeutical cell preparation for treating diabetes. The cell lines of the present invention can be obtained by integrating both a nucleotide sequence encoding tamoxifen-induced Cre recombinase and a nucleotide sequence encoding insulin regulated by glucose-sensitive promoter into the chromosome in a human immortalized hepatic cell line FERM BP-7498 containing the TERT gene inserted in between a pair of LoxP sequences.

Abstract: A method of ex-vivo expanding a population of stem cells, while at the same time inhibiting differentiation of the stem cells. The method comprises ex-vivo providing the stem cells with conditions for cell proliferation and with at least one copper chelator in an amount and for a time period for permitting the stem cells to proliferate and, at the same time, for reducing a capacity of the stem cells to differentiate.

Abstract: Polynucleotide and polypeptide sequences that encode novel variant FAM3C proteins are disclosed that can be used in therapeutic, diagnostic, and pharmacogenomic applications.

Abstract: The invention involves combining a peptide toxin effective against insects, including but not limited to thrips, leaf hoppers, and beetles, with a transport peptide capable of facilitating transfer of the peptide toxin from the gut of an insect to the hemocoel. The combination can be effected by a fusion of genetic material encoding the peptide toxin and the transport peptide, such that expression of the genetic material fusion results in synthesis of a fusion protein combining the functions of both the toxin and the transport protein. Ingestion of the fusion protein by the sucking insect transfers the fusion protein into the insect's gut from which it is transferred into the hemocoel due to the functional activity of the transport peptide where the toxin exerts its toxic effect upon the insect. In a preferred embodiment, the invention is effective in control of such sucking insects as aphids, whiteflies and the like, and other vectors that transmit viruses in a circulative manner.

Abstract: This invention provides a method of converting a stem cell into a ventral neuron which comprises introducing into the stem cell a nucleic acid which expresses homeodomain transcription factor Nkx6.1 or Nkx6.2 protein in the stem cell so as to thereby convert the stem cell into the ventral neuron. Provided are methods of diagnosing a motor neuron degenerative disease in a subject. Also provides is a method of treating neuronal degeneration in a subject which comprises implanting in diseased neural tissue of the subject a neural stem cell which is capable of expressing homeodomain Nkx6.1 or Nkx6.2 protein under conditions such that the stem cell is converted into a motor neuron after implantation, thereby treating neuronal degeneration in the subject.

Abstract: The present invention relates to a crystal structure of G-quadruplexes and its use. The invention provides a crystal of an intramolecular G-quadruplex structure having a hexagonal space group P6, and unit cell dimensions a=b=56.7 and c=42.1; ?=?=90°, ?=120° and a crystal of G-quadruplex having the three dimensional atomic coordinates of Table 1 or Table 2. These structures may be used in a computer-based method for the analysis of the interaction of a molecular structure with a G-quadruplex.

Abstract: A method of assigning expected recovery values to control substances used in analytical testing is disclosed.

Abstract: An incubator includes an incubator ring assembly having at least two concentric rings supported for rotation about a common axle defining an axis of rotation. Each concentric ring includes a plurality of circumferentially defined load positions, each load position being sized for accommodating a test sample. At least one test station is arranged in relation to the plurality of load positions to selectively test a test sample, the test samples being are sequentially shuttled into and out of load positions of at least one of the concentric rings to increase the overall throughput of the analyzer.

Abstract: The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or detection of particles, such as cells and/or beads. The invention provides systems, including apparatus, methods, and kits, for the microfluidic manipulation and/or analysis of particles, such as cells, viruses, organelles, beads, and/or vesicles. The invention also provides microfluidic mechanisms for carrying out these manipulations and analyses. These mechanisms may enable controlled input, movement/positioning, retention/localization, treatment, measurement, release, and/or output of particles. Furthermore, these mechanisms may be combined in any suitable order and/or employed for any suitable number of times within a system.

Abstract: The present invention provides novel polynucleotides encoding HGPRBMY23 polypeptides, fragments and homologues thereof. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying these novel HGPRBMY23 polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides, particularly renal diseases and/or disorders, colon cancer, breast cancer, and diseases and disorders related to aberrant NFKB modulation. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention.

Abstract: The invention is directed to devices and methods that allow for simultaneous multiple biochip analysis. The method of analyzing the plurality of biochips includes inserting a first biochp into a first station of an analysis device, inserting a second biochip into a second station of the analysis device, wherein each of the first and second biochips include a substrate, the substrates including an array of detection electrodes, each electrode including a different capture binding ligand, a different target analyte, and a label, and a plurality of electrical contracts, detecting current as an indication of the presence of the labels on the first biochip, and detecting current as an indication of the presence of the labels on the first second biochip. The devices and method may be used with multiple cartridges comprising biochips comprising arrays, such as nucleic acid arrays, and allow for high throughput analysis of samples.

Abstract: Apparatus for use in effecting surface-enhanced Raman spectroscopy comprises first and second containment means, the first containment means containing a known quantity of a reference chemical having an effective surface-enhanced Raman factor, and the second containment means containing a surface-enhanced Raman-active medium and being sufficiently transparent, at least at one optical access location, to permit both the excitation irradiation of, and also the collection of surface-enhanced Raman scattered radiation from, a common field of view of the surface-enhanced Raman-active medium. The apparatus is constructed for carrying out the method of the invention; i.e., for effecting intimate mixing, substantially prior to introduction to the surface-enhanced Raman-active medium contained in the second containment means, of the reference chemical with an analyte chemical-containing solution introduced through an entrance into the first containment means.

Abstract: The invention is based on the development of several sensitive and simple methods for detecting erythropoietin and the erythropoietin receptor and associated antibodies. The methods and reagents are useful for differential diagnosis in Epo and EpoR related clinical problems. Methods and kits for simultaneous measurement of erythropoietin and erythropoietin receptor in a biological sample are described.

Abstract: Methods are provided for detecting biomolecular interactions. The use of labels is not required and the methods can be performed in a high-throughput manner. The invention also relates to optical devices.

Abstract: Metal organic chemical vapor deposition (MOCVD) may be utilized in methods of forming an (111) oriented PZT ferroelectric layer at a lower temperature, a ferroelectric capacitor and methods of fabricating, and a ferroelectric memory device using the same may be provided. Using the metal organic chemical vapor deposition, ferroelectric layers, capacitors, and memory devices, which may be fabricated and may have (111) preferred oriented crystal growth.

Abstract: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into the single crystal substrate to modify the chemical and/or structural properties of subsurface layers at predetermined depths underneath super layers of material. These subsurface layers are removed by selective etching. The removal of the subsurface layers leaves the super layers of material intact as membrane structures on top of openings or channels corresponding to the space of the removed subsurface layers. At least one portion or end of a membrane structure remains attached to the single crystal substrate.

Abstract: An image sensor and a fabrication method thereof are provided. The image sensor includes: a first photodiode formed in a substrate and receiving a first color; a second photodiode formed in the substrate apart from the first photodiode and receiving a second color with a wavelength longer than that of the first color; a third photodiode formed in the substrate apart from the first photodiode and the second photodiode and receiving a third color with a wavelength longer than that of the second color; and a passivation layer formed on the substrate and having different regional thicknesses whose magnitude increases in order of a first region of the passivation layer corresponding to a first color region, a second region of the passivation layer corresponding to a second color region and a third region of the passivation layer corresponding to a third color region.

Abstract: A printing system for printing a pattern onto a liquid crystal display device includes a cliché having a plurality of grooves defining a pattern, a blade for filling a material into each of the plurality of grooves of the cliché, a clean chamber for cleaning the cliché, and an actuator disposed within an interior of the clean chamber upon which the cliché is placed.

Abstract: An electronic system for selectively detecting and identifying a plurality of chemical species, which comprises an array of nanostructure sensing devices, is disclosed. Within the array, there are at least two different selectivities for sensing among the nanostructure sensing devices. Methods for fabricating the electronic system are also disclosed. The methods involve modifying nanostructures within the devices to have different selectivity for sensing chemical species. Modification can involve chemical, electrochemical, and self-limiting point defect reactions. Reactants for these reactions can be supplied using a bath method or a chemical jet method. Methods for using the arrays of nanostructure sensing devices to detect and identify a plurality of chemical species are also provided.

Abstract: There is disclosed a nanotube sensor which essentially employs a straight or twisted nanotube deposited on a supporting surface, such as silicon, silicon dioxide and some other semiconductor or metal material. The nanotube is basically a graphite device which is now subjected to stress causing the electrical characteristics of the nanotube to change according to stress. The nanotube is then provided in a circuit, such as a Wheatstone Bridge or other circuit, and the circuit will produce an output signal proportional to the change in electrical characteristics of the nanotube according to the applied force.

Abstract: A method of fabricating a photovoltaic solar cell is provided. A plurality of generally spherical semiconductor elements are provided. Each of the semiconductor elements has a core and an outer surface surface forming a p-n junction. An anti-reflection coating is deposited on the outer surface of each of the semiconductor elements and each of the semiconductor elements is bonded into a perforated aluminum foil array thereby providing ohmic contact to a first side of the p-n junction. The anti-reflection coating is removed from a portion of each of the semiconductor elements and then the core is exposed, thereby allowing ohmic contact to be made to a second side of the p-n junction.

Abstract: There is provided a CMOS image sensor comprises a LOCOS isolation film 6 formed on the surface of a semiconductor substrate 100 containing a peripheral circuit 31 and a photodiode region 15, a gate electrode 1 formed on the surface of the peripheral circuit 31, a surface-protecting film 8 deposited on at least a portion of the photodiode region 15, and a sidewall 19 of the gate electrode formed without damaging the portion of photodiode region 15 on which a surface-protecting film 8 is deposited, thereby eliminating etching damage on the surface of the substrate to be expected for a photodiode during blanket etch-back, and suppressing fixed pattern noise (FPN).

Abstract: An organic electroluminescent device includes a substrate, a plurality of gate lines on the substrate, a plurality of data lines on the substrate, each of the plurality of data lines crossing the gate lines, a plurality of switching elements and driving elements interconnected on the substrate, and a power line disposed in parallel to the data lines on the substrate, wherein the power line is electrically connected to at least two of the plurality of driving elements.

Abstract: This invention pertains to methods assembly of organic molecules and electrolytes in hybrid electronic. In one embodiment, a method is provided that involves contacting a surface/electrode with a compound of formula: R-L2-M-L1-Z1 where Z1 is a surface attachment group; L1 and L2 are independently linker or covalent bonds; M is an information storage molecule; and R is a protected or unprotected reactive site or group; where the contacting results in attachment of the redox-active moiety to the surface via the surface attachment group; and ii) contacting the surface-attached information storage molecule with an electrolyte having the formula: J-Q where J is a charged moiety (e.g., an electrolyte); and Q is a reactive group that is reactive with the reactive group (R) and attaches J to the information storage molecule thereby patterning the electrolyte on the surface.

Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Abstract: A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.

Abstract: A method for making an integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The metal layer can provide one or more power planes within the substrate. A laser is used to ablate channels on the surfaces of the outer dielectric layer for the conductive patterns. The conductive patterns are electroplated or paste screen-printed and an etchant-resistive material is applied. Finally, a plating material can be added to exposed surfaces of the conductive patterns. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

Abstract: A resin composition usable for encapsulating a semiconductor, comprising (A) an epoxy resin having two or more epoxy groups in one molecule; (B) a curing agent; and (C) inorganic composite oxide particles constituted by silicon dioxide and at least one metal oxide selected from the group consisting of oxides of metal atoms belonging to Group III and Group IV of the Periodic Table excluding silicon; a semiconductor device comprising a wiring circuit board, a semiconductor element, and the above resin composition; and a method for manufacturing a semiconductor device comprising the steps of adhering a resin sheet comprising the resin composition of claim 1 and a stripping sheet to a semiconductor circuit side of a bump-mounting wafer, removing the stripping sheet leaving only the resin composition to the wafer, and cutting the wafer into individual chips.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: Method for encapsulating a chip having a sensitive surface exposed in a sealed highly clean cavity package, includes bonding a chip's contact pads to lead frame contact pads, positioning the chip and lead frame into one part of a two part mould, taking measures to keep the space above the sensitive surface of the chip free during the encapsulation process, closing the mould with a second mould part, introducing the package material into the closed mould and providing the circumstances to let the package cure. The method also including applying a closed dam of heat resistant material around the sensitive chip area and placing a lid on the dam such that space above the sensitive area enclosed by the dam and the lid is sealed.

Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.

Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.

Abstract: A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements. The said method further comprised of: providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

Abstract: An LCD panel includes a plurality of gate lines and gate electrodes formed on a substrate and a gate insulating film formed on the substrate including the gate lines and the gate electrodes. A semiconductor film is formed in a region on the gate insulating film and an ohmic contact film formed on the semiconductor film. A plurality of data lines cross the gate lines; a source electrode is formed on the ohmic contact film; and a pixel electrode is formed in a pixel region defined by the gate and data lines. A drain electrode is formed on the ohmic contact film, and has an uneven width. Since a portion of drain electrode that overlaps with the gate electrode has a smaller width than a width of other portions of the drain electrode, variation in an area of the drain electrode overlapped with the gate electrode is small, so that variation of the parasitic capacitance can be reduced, thereby improving picture quality.

Abstract: A fabrication process for transistor array substrates of different sizes on a common substrate provides quality control, yield, and space efficiency advantages. In particular, a four-mask process, including a mask with diffraction slits, may be employed to fabricate transistors that share common channel characteristics for each of the transistor array substrates.

Abstract: A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant process is performed to form PMOS pocket regions in a PMOS region of the semiconductor substrate. Spacers are formed on sidewalls of a PMOS gate electrode pattern and sidewalls of an NMOS gate electrode pattern, and an ion implant process is performed to form PMOS source/drain regions in the semiconductor substrate in which the PMOS pocket regions are formed. An ion implant process is performed to form NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed.

Abstract: The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact. More specifically, the present invention relates to manufacturing method for a trench capacitor having an isolation collar with a metal conductive fill in the collar region connected to a metal fill in the capacitor region.

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1?, 60, 1?) having a front side (VS) and a rear side (RS); providing trenches (5) in the semiconductor substrate (1; 1?, 60, 1?) proceeding from the front side (VS) of the semiconductor substrate (1; 1?, 60, 1?); providing a respective inner capacitor electrode (6) in the trenches (5); uncovering the inner capacitor electrodes (6) proceeding from the rear side (RS) of the semiconductor substrate (1; 1?, 60, 1?); providing a capacitor dielectric (40) on the uncovered inner capacitor electrodes (6); and providing outer capacitor electrodes (50) on the capacitor dielectric (40) on the inner capacitor electrodes (6).

Abstract: In a method of forming a metal-insulator-metal (MIM) capacitor in a semiconductor device, after forming a capacitor insulation layer on a lower metal layer of the MIM capacitor, an upper electrode is formed by ion implantation into the capacitor insulation layer and silicidation, without a typical reactive ion etching process. Consequently, damage to the capacitor insulation layer can be minimized, and the area of the capacitor need not increase.

Abstract: A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second electrode, and a second dielectric film provided between the second electrode and the third electrode, an insulating film covering the capacitor structure and having a first hole reaching the first electrode, a second hole reaching the second electrode, and a third hole reaching the third electrode, a first conductive connection electrically connecting the first electrode and the third electrode and having portions buried in the first and third holes, and a second conductive connection formed separately from the first conductive connection and having a portion buried in the second hole.

Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

Abstract: A method of manufacturing a semiconductor device includes forming first and second active regions and a field region in a surface of a substrate; forming a first gate insulating film in the first and second active regions; covering the surface of the substrate with a first polycrystalline silicon film; exposing the first gate insulating film on the second active region by forming an aperture in the first polycrystalline silicon film over the second active region; removing the first gate insulating film in the second active region; forming a second gate insulating film which is thicker than the first gate insulating film in the second active region; covering the surface of the substrate with a second polycrystalline silicon film; removing the second polycrystalline silicon film on the first active region until it becomes a predetermined film thickness; and forming gate electrodes on the first and second active regions.