Abstract: An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

Abstract: The invention relates to a process for producing a layer arrangement, in which, a porous silicon layer is formed as sacrificial layer on an auxiliary substrate, a first semiconductor layer is formed on the sacrificial layer, a first electrically insulating layer is formed on the first semiconductor layer, an electrically conductive layer is formed on the first electrically insulating layer, which electrically conductive layer is laterally patterned, the first electrically insulating layer, the sacrificial layer and the first semiconductor layer are jointly laterally patterned using the laterally patterned electrically conductive layer as a mask, a semiconductor structure is formed adjacent to side walls of the patterned sacrificial layer and of the patterned first semiconductor layer, a substrate is secured over the patterned electrically conductive layer, material of the auxiliary substrate is removed, so that the sacrificial layer is uncovered, the sacrificial layer is selectively removed, so as to form a t

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

Abstract: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.

Abstract: A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide.

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

Abstract: The present invention provides a laser processing apparatus having a laser oscillator for outputting a pulsed laser beam; deflection unit for deflecting the pulsed laser beam to irradiate a object to be processed with the deflected pulsed laser beam; a mounting base on which the object is placed and which is movable in an axial direction or two-axial directions perpendicular to each other; and local shielding unit for controlling an atmosphere around the surface of the object to be processed which is irradiated with the laser beam. When a thin semiconductor film with a thickness of 1 ?m or less is formed over the surface, minute convex portions are formed, which causes a problem that characteristics of TFTs vary among elements. Minute particles generated and adhered to a main surface of a substrate through a laser processing, which is difficult to remove in general surface cleaning, become preventable by the invention.

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

Abstract: A transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).

Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

Abstract: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.

Abstract: A technique is provided that is capable of employing raw materials having no halogen, which has a high possibility of exerting a bad influence upon semiconductor elements, thereby to easily form molybdenum films (molybdenum silicide films or molybdenum nitride films) of which purity is high at a low temperature. A film forming material for forming molybdenum films, molybdenum silicide films, or tungasten nitride films is provided, wherein a Mo source of said film is one or more chemical compounds selected from the group consisting of a hexadimethylaminodimolybdenum, a hexaethylmethylaminodimolybdenum, and a hexadiethylaminodimolybdenum.

Abstract: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.

Abstract: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When connecting the cable to a task object such as an LCD glass substrate or PCB, only a usual non-conductive paste is applied to join the cable and the task object, without use of expensive anisotropic-conductive paste or film.

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Abstract: An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.

Abstract: The present invention provides an electronic device having high insulating reliability, in which metal portions of a circuit are not electrically conductive with each other via an adhesive layer even when the electronic device is used in high-temperature low-humidity conditions or high-temperature high-humidity conditions, and provides a production method for the electronic device, and a semiconductor device comprising the electronic device. In the electronic device in which a circuit formed by pattern formation of metal portions is attached via an adhesive layer to an insulating base, the adhesive layer, which contacts adjacent metal portions, is divided. Typically, the electronic device is one of a lead frame having a lead frame fixing tape, a TAB tape, and a flexible printed circuit board.

Abstract: The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed.

Abstract: A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.

Abstract: A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.

Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Abstract: A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C?C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10?9-10?3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.

Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

Abstract: The corrosion of aluminum-based metal films may be minimized by applying a lactate-containing solution to the aluminum-based metal films before the aluminum-based metal films are etched. The lactate-containing solution is applied to the aluminum-based metal film before the film is etched with a corrosive etchant. Minimizing the corrosion of the aluminum-based film may increase the yield and performance of the highly reflective pixel arrays that are formed from the aluminum-based metal for use in liquid crystal on silicon (LCOS) microprocessors for digital televisions.

Abstract: A method is described for treating a wafer having at least a surface layer of semiconductor material, with the surface of this surface layer having undergone a chemical-mechanical polishing step followed by an RCA cleaning step. After the polishing step and prior to the RCA cleaning step, the method includes an intermediate step of cleaning the surface of the surface layer of semiconductor material using an SC1 solution under concentration and temperature conditions that allow the emergence of defects in the surface layer (curve B) to be reduced compared with a similar surface layer which has not undergone such an intermediate cleaning step (curve A).

Abstract: A method of polishing a semiconductor layer formed on a transparent substrate is described, the method including measuring the thickness of the semiconductor from the substrate side of the semiconductor layer simultaneously with the polishing, and using the thickness measurement to modify the polishing.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: Methods and apparatus for cleaning a semiconductor device are disclosed. A disclosed method comprises forming a capping layer on top of a substrate including a bottom interconnect layer; depositing and patterning an insulating layer on the capping layer to form a damascene structure; etching a portion of the capping layer exposed by the damascene structure; and (d) removing polymers and copper impurities due to the etching by using a HF vapor gas.

Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.

Abstract: The variability of immersion processes for treatment of semiconductor devices can be significantly lowered by initiating the termination of a treatment process according to a predetermined treatment termination protocol in a manner that takes into account the contribution of, in particular, the treatment that is carried out during the period of time in the treatment process in which the treatment process is being terminated. In a preferred embodiment, conditions that indicate the progress of the treatment on a real time basis are monitored, and the timing of the initiation of the termination process is additionally based on the calculated amount of treatment and treatment rate of the process in progress.

Abstract: A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and coupling RF plasma bias power or bias voltage to the workpiece.

Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.

Abstract: A method for applying a passivation layer selectively on an exposed silicon surface includes use of a liquid phase solution supersaturated in silicon dioxide. The application is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by applying the supersaturated solution prior to plugging the holes with conductive material.

Abstract: Methods of film deposition using metals and metal oxides. A thin film of germanium oxide and an oxide of a non-germanium metal is deposited by ALD by alternating deposition of first and second precursor compounds, wherein the first precursor compound includes a metal other than germanium, and the second precursor compound includes germanium.

Abstract: The invention concerns a textile surface having at least a high-visibility face. It is obtained from yarns or fibres of at least three types, of blanketing yarns or fibres, heat-stable yarns or fibres and high-visibility yarns or fibres. The surfaces provide excellent protection against fire and flames.

Abstract: A multilayer, breathable film that contains a base layer and at least one skin layer is provided. The skin layer is incorporated with a filler that is capable of reducing odor. The base layer may be substantially free of the odor-reducing filler to maintain the integrity of the resulting film. As a result, it has been discovered that the multilayer film of the present invention can be used to reduce odor in a variety of applications, while still maintaining the desired breathability.

Abstract: In one aspect, the invention provides glass beads and optical devices comprising the glass beads. In other aspects, the invention provides methods of making said glass beads and rapid glass screening methods that use glass beads. Glass beads of the invention comprise greater than 80 weight percent silica, active rare earth dopant, and modifying dopant. In another embodiment the glass beads comprise greater than 80 weight percent silica and at least 5 weight percent germania. In another embodiment, glass beads comprise and from about 20 to about 90 anion mole percent of non-oxide anion.

Abstract: The present invention provides a high refractive index, high dispersion optical glass for precision molding, being free from harmful materials causing environmental problems, such as lead oxide, etc., and having a low yield temperature, a refractive index (nd) of at least 1.83 and an Abbe number (?d) of at most 26.0 and further providing a low softening property as well as an improved mass production property with less coloration, which is represented in terms of for making up the glass, by the following chemical composition (wt %): P2O5 15 to 29% B2O3 ?0 to 2% GeO2 ?0 to 14% Sum of P2O5 + B2O3 + GeO2 20 to 35% Li2O ?0 to 5% Na2O ?3 to 14% K2O ?0 to 9% Sum of Li2O + Na2O + K2O ?5 to 15% Nb2O5 ?2 to less than 22% Bi2O3 34 to 60% WO3 ?0 to 5% BaO ?0 to 5% In2O3 ??0 to 7%.

Abstract: The present invention provides an optical synthetic quartz glass material which substantially does not cause changes in transmitted wave surface (TWS) by solarization, compaction (TWS delayed), rarefaction (TWS progressed) and photorefractive effect when ArF excimer laser irradiation is applied at a low energy density, e.g. at energy density per pulse of 0.3 mJ/cm2 or less. The present invention further provides a method for manufacturing the same. In order to solve the above-mentioned problems, the optical synthetic quartz glass material of the present invention is characterized in that, in a synthetic quartz glass prepared by a flame hydrolysis method using a silicon compound as a material, the followings are satisfied that the amount of SiOH is within a range of more than 10 ppm by weight to 400 ppm by weight, content of fluorine is 30 to 1000 ppm by weight, content of hydrogen is 0.

Abstract: A structural material of a polystyrene base and the reaction product of the polystyrene base and a solid phosphate ceramic. The ceramic is applied as a slurry which includes one or more of a metal oxide or a metal hydroxide with a source of phosphate to produce a phosphate ceramic and a poly (acrylic acid or acrylate) or combinations or salts thereof and polystyrene or MgO applied to the polystyrene base and allowed to cure so that the dried aqueous slurry chemically bonds to the polystyrene base. A method is also disclosed of applying the slurry to the polystyrene base.

Abstract: A dielectric ceramic composition, comprising a main component including at least a dielectric oxide having a composition expressed by [(CaxSr1-x)O]m[(TiyZr1-y-zHfz)O2], a first subcomponent including a Mn oxide and/or an Al oxide and a glass component, wherein “m”, “x”, “y” and “z” indicating composition mole ratios in the formula included in the main component are in relationships of 0.90?m?1.04, preferably 1.005?m?1.025, 0.5?x<1, preferably 0.6?x?0.9, 0.01?y?0.10, preferably 0.02?y?0.07 and 0<z?0.20, preferably 0<z?0.10.

Abstract: This invention relates to regeneration of coked catalyst by combustion so that the catalyst can be reused in a hydrocarbon conversion reaction. The completion of coke burn is generally measured with a combination of temperature or change in oxygen concentration. Dropping outlet temperatures require time to wait for increases in inlet temperature to correspondingly move down the regenerator. Faster response times might be expected from increasing oxygen concentration, but a small increase in concentration can lead to a significant increase in peak burn temperature which negatively impacts catalyst life. Controlled peak burning is difficult over the entire bed by merely controlling inlet and outlet oxygen concentrations. The invention accordingly combines a measured lag time for temperature travel with an inlet temperature ramping step to ensure complete coke combustion with high oxygen efficiency, thus providing a rapid regeneration that permits more time for operation at desired reaction conditions.

Abstract: The invention is directed to a simple method for preparing highly dispersed, highly loaded platinum metal elements on various carbon substrates, including conductive carbon black, which is utilized in fuel cell electrodes. Utilizing carbon with a controlled point of zero charge (PZC) and maintaining a desired pH value throughout the adsorption of metal onto the carbon substrate, a high metal loading is achieved for a given surface area of the carbon substrate.