Abstract: A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract: Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.

Abstract: A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layer structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 ?, and preferably around 500 ?.

Abstract: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A method (and structure) of coupling a qubit includes locating the qubit near a transmission line approximately at a location corresponding to a node at a predetermined frequency.

Abstract: An n-channel or ambipolar field-effect transistor including an organic semiconductive layer having an electron affinity EAsemicond; and an organic gate dielectric layer forming an interface with the semiconductive layer; characterised in that the bulk concentration of trapping groups in the gate dielectric layer is less than 1018cm?3, where a trapping group is a group having (i) an electron affinity EAX greater than or equal to EAsemicondand/or (ii) a reactive electron affinity EArxngreater than or equal to (EAsemicond. ?2eV).

Abstract: The present invention provides an optoelectronic device comprising a light emitting semiconductor and an encapsulant. The encapsulant is made from an encapsulant formulation comprising an epoxy hydantoin, an epoxy isocyanurate, and a curing agent. The present invention also provides a method of preparing such optoelectronic device.

Abstract: Disclosed herein are a novel oligomeric compound with improved dispersion performance and a method for preparing the same. The oligomeric compound comprises a tail structure consisting of hydrophilic and hydrophobic blocks and an amine or imidazole head structure. The dye containing the compound can be used to prepare a paste composition for a semiconductor electrode of a solar cell. A semiconductor electrode produced using the paste composition and a solar cell fabricated using the semiconductor electrode exhibit greatly improved power conversion efficiency and superior processability.

Abstract: The present invention relates to a semiconductor structure having a low hot-carrier effect characteristic, and, more particularly, to a semiconductor structure capable of reducing the detrimental influence of the happening of the hot-carrier effect on the performance of the transistor having the semiconductor structure, even after the transistor has been operated under an operation environment with high channel electric field. The semiconductor structure comprises: a substrate; a metal layer formed on parts of the surface of the substrate; an insulation layer formed on the surface of the substrate and covering the surface of the metal layer; a first semiconductor layer covering parts of the surface of the insulation layer; and a second semiconductor layer covering parts of the surface of the first semiconductor layer. Besides, the second resistance of the second semiconductor layer is larger than the first resistance of the first semiconductor layer.

Abstract: An organic light-emitting display device wherein an IR drop across a first electrode can be prevented. The organic light-emitting display device includes a substrate; a plurality of stripe-shaped first electrodes disposed on the substrate and extending in a first direction; a plurality of stripe-shaped first insulators extending in a second direction to cross the stripe-shaped first electrodes; a plurality of stripe-shaped second electrodes disposed between the stripe-shaped first insulators to extend in the same direction as the stripe-shaped first insulators and cross the stripe-shaped first electrodes; an intermediate layer disposed at positions where the stripe-shaped first electrodes and the stripe-shaped second electrodes cross and including an emission layer; and first conductors disposed at positions where the stripe-shaped first electrodes and the stripe-shaped first insulators intersect and between the stripe-shaped first electrodes and the stripe-shaped first insulators.

Abstract: A semiconductor device includes an organic semiconductor transistor provided on a substrate; a data line connected to a source electrode or a drain electrode of the organic semiconductor transistor; and a gate line that is disposed so as to intersect the data line and that is connected to a gate electrode of the organic semiconductor transistor. In the semiconductor device, the gate line includes the gate electrode, a first gate line that transmits signals to the gate electrode, and a second gate line intersecting the data line, with an interlayer insulation layer therebetween; the gate electrode, the first gate line, and the second gate line are connected in series; and the electric conductivity of the first gate line is higher than the electric conductivity of the gate electrode and the electric conductivity of the second gate line.

Abstract: An organic light emitting display is disclosed. One embodiment of the organic light emitting display includes a substrate member and a plurality of pixels that are formed on the substrate member. At least one of the pixels includes a thin film transistor, a light emitting element that is electrically connected to the thin film transistor, and a reflective layer that is disposed between the thin film transistor and the light emitting element and that is insulated from each of the thin film transistor and the light emitting element.

Abstract: An organic light emitting diode (“OLED”) display includes a substrate, a gate line, a data line, a driving voltage line, a light blocking member, a switching thin film transistor (“TFT”), a driving TFT, and an OLED, wherein the driving voltage line includes a portion parallel to at least one of the gate line and the data line, the light blocking member is formed under at least one of the gate line, the data line, and the driving voltage line, the switching TFT is connected to the gate line and the data line and includes an amorphous semiconductor, the driving TFT is connected to the switching TFT and includes a polycrystalline semiconductor, and the OLED is connected to the driving TFT.

Abstract: A TFT array substrate includes a TFT having an ohmic contact film and a source electrode and a drain electrode formed on the ohmic contact film. It also includes a pixel electrode electrically connected with the drain electrode. The source electrode and the drain electrode are made of an Al alloy containing Ni as an additive.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: A thin film transistor includes a gate electrode, a gate insulation layer on the gate electrode, source and drain electrodes formed on the gate insulation layer, a polysilicon channel layer overlapping the ohmic contact layers and on the gate insulation layer between the source and drain electrodes, ohmic contact regions over the source and drain electrodes for contacting the polysilicon channel to the source and drain electrodes, and doping layers over the source and drain electrodes.

Abstract: A conversion apparatus comprises a pixel region, on a substrate, including a plurality of pixels arranged in a matrix, each pixel having a conversion element that converts radiation into electric signals and a switching element, wherein the switching element has a structure comprising a gate electrode, a first insulating layer, a second insulating layer and a semiconductor layer from the substrate side in this order, and the conversion element has a structure comprising a bottom electrode, the second insulating layer and a semiconductor layer on the first insulating layer from the substrate side in this order.

Abstract: An active matrix TFT array substrate includes a gate electrode and a gate line formed from a first metal film over a transparent insulating substrate, a gate insulating film to cover the gate electrode and gate line, a semiconductor layer formed over the gate insulating film, a source electrode and a drain electrode formed over the semiconductor layer and a pixel electrode formed from a transparent conductive film. Either of the source or the drain electrode is formed from the transparent conductive film and the active matrix TFT array substrate further comprises a second metal film thereover mainly including one of Al, Cu and Ag.

Abstract: An encapsulant containing nanoparticles that improve the heat and UV resistance properties of electroluminescent devices. The nanoparticles that are suspended in the encapsulant may be either oxides or non-oxides and may include SiO2, TiO2, Al2O3, ZrO2, Ti, TiB2, TiC, and TiN. The nanoparticles may range in size from 5 to 165 nm in diameter. The encapsulant containing nanoparticles may be used in an electroluminescent device by being deposited in a concave base cavity to cover a light source, such as a light-emitting diode (“LED”), positioned in the concave base cavity, and may also be applied in the form of a conformal coating that covers the light source. An electroluminescent device utilizing the encapsulant containing nanoparticles and a method of producing such a device is also provided.

Abstract: An LED Device Having a Top Surface Heat Dissipator is provided. The LED Device Having a Top Surface Heat Dissipator includes a substrate body, and a light emitting diode over the substrate body. The LED Device Having a Top Surface Heat Dissipator also has an electrically and thermally conductive heat dissipator over the substrate body. A method of dissipating heat from an LED device is also provided.

Abstract: A base apparatus includes a base and two finger devices. The base has a first surface and two opposite sides. The finger devices are respectively mounted on the sides of the base, are made of conductive material, and each of the finger devices has multiple fingers. The fingers are extended on the first surface of the base, wherein the fingers of a first finger device are arranged respectively corresponding to the fingers of a second finger device whereby each pair of corresponding fingers supports an illuminating device. The base has a height, each of the fingers has a width and the width is smaller than the height. When the LED is mounted onto a substrate, the LED can be mounted on the substrate by its side so that an entire assembly height of the LED is reduced and is equal to the width of the LED.

Abstract: Disclosed are a light emitting device and a method for fabricating the same. The light emitting device can include a substrate, a buffer layer having a pattern on the substrate, a first conductive-type semiconductor layer on the buffer layer, an active layer on the first conductive-type semiconductor layer, and a second conductive-type semiconductor layer on the active layer.

Abstract: A light emitting diode module is disclosed. The light emitting diode module includes a substrate, a plurality of light emitting diodes, and a plurality of lenses. The light emitting diodes are disposed on the substrate, and the lenses are disposed on the substrate and covering the light emitting diodes, in which each of the lenses includes a curved surface corresponding to each of the light emitting diodes.

Abstract: The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can be conducted with a good state in which a shape and property of an element before peeling are kept. Further, the present invention provides a manufacturing technique of more highly reliable semiconductor devices and display devices with high yield without complicating the apparatus and the process for manufacturing. According to the present invention, an organic compound layer including a photocatalyst substance is formed over a first substrate having a light-transmitting property, an element layer is formed over the organic compound layer including a photocatalyst substance, the organic compound layer including a photocatalyst substance is irradiated with light which has passed through the first substrate, and the element layer is peeled from the first substrate.

Abstract: A method of combining beams from a plurality of laser resonators includes frequency modulating the output of each of the lasers with one or more of the lasers frequency modulated out-of-phase with the others. The frequency modulated beams are directed along parallel spaced-apart paths and overlap in a plane along the paths to form a combined beam having a flat-topped intensity distribution.

Abstract: A light-emitting device (1) is composed by integrating light-emitting diodes (2R, 2G, 2B) and a drive IC (3) for driving these light-emitting diodes (2R, 2G, 2B). The light-emitting device (1) is characterized in that the drive IC (3) has a built-in circuit for controlling the current value of each light-emitting diode (2) or the current proportions of the light-emitting diodes at constant values. The adjustment of the intensities of the light beams emitted from the light-emitting diodes can be simplified, and no outside circuits for adjustment are needed. The structure is excellent in assemblability. When a desired emission color is produced by mixing the emission colors, the adjustment for the mixing is easy, and a structure suited for enhancing the color rendering properties when a while light is emitted is provided.

Abstract: The semiconductor device of the present invention is a semiconductor device including P-type and N-type thin film transistors, at least one of the N-type thin film transistors having an off-set gate structure, at least one of the P-type thin film transistors having a LDD structure, wherein a P-type high concentration impurity layer for forming the at least one P-type thin film transistor is formed on the semiconductor layer in a region other than a region below a gate electrode and a sidewall spacer and contains a higher concentration of a P-type impurity together with an impurity contained in an N-type low concentration impurity layer and an N-type high concentration impurity layer for forming the N type thin film transistor.

Abstract: Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.

Abstract: An LED and light guide assembly has an LED with an output surface; a first power input lead electrically coupled to a first pole and having a first surface and a second surface; and a second power input lead electrically coupled to a second pole and having a first surface and a second surface. A unitary, molded light guide has an axially extending, light transmissive body with a light output window. An input window is formed with the unitary, molded light guide being aligned in a zero-gap relationship to capture substantially all the light emitted by the LED. A support is formed integral with the light guide and envelopes a portion of the first surface and the second surface of the first power input lead and the first surface and the second surface of the second power input lead to anchor the guide with respect to the power inputs.

Abstract: A structure of light emitting diode (LED) effectively reduces its spectral width. The LED structure is applied in a three color mixing of a backlight module to broaden a color space and to improve a saturation of a color display. A grating structure is used as a waveguide layer to coordinate with the LED structure. The present invention does not affect the original thermo and electrical characteristics of the LED structure and has a simple fabrication method.

Abstract: A semiconductor light emitting device 100 comprises: a mount member 130 and a semiconductor light emitting element 110 arranged on the mount member 130, the mount member 130 including: a substrate 131; an electrode assembly (a positive electrode 134, a negative electrode 135, and bumps 140 to 144) that is arranged on a top surface of the substrate 131 and contacts the semiconductor light emitting element 110; and a reflecting member 132 that is out of contact with the semiconductor light emitting element 110 and the electrode assembly. According to this structure, a semiconductor light emitting device can be provided, which efficiently outputs output light using a material having a high reflectance regardless of whether the material is appropriate for an electrode.

Abstract: Light-emitting devices (e.g., LEDs) and methods associated with such devices are provided. The devices may include a first pattern and a second pattern which are formed at one or more interfaces of the device (e.g., the emission surface). The patterns may be positioned such that light generated by the device passes through the interfaces of the patterns when being emitted. The patterns can be defined by a series of features (e.g., vias, posts) having certain characteristics (e.g., feature size, depth, periodicity, nearest neighbor distance, etc.) which may be controlled to influence properties of the light emitted from the device, including improving extraction and/or collimation of the emitted light.

Abstract: The present invention relates to a micro USB memory package and a method for manufacturing the same. The object of the present invention is to provide a micro USB memory package and a method for manufacturing the same, which can meet the USB standard specification, can have light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof.

Abstract: The present invention provides an optoelectronic device comprising a light emitting semiconductor and an encapsulant. The encapsulant is made from an encapsulant formulation comprising an epoxy isocyanurate such as formula (I-1) compound, and a curing agent. The present invention also provides a method of preparing such optoelectronic device.

Abstract: A compound semiconductor luminescent device characterized by comprising: an electroconductive substrate; a compound semiconductor function layer including a GaN layer; an electrode; an adhesiveness-enhancing layer; and a bonding layer, which are stacked in this order, wherein the above-described electroconductive substrate includes a metal material that indicates a thermal expansion coefficient different by 1.5×10?6/° C. or less from GaN.

Abstract: The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED's, lasers), light detecting devices (such as detectors and sensors), power rectifier diodes and FETs (e.g., HFETs), amongst others.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Abstract: A semiconductor device includes: a bulk semiconductor substrate; a thyristor formed in the bulk semiconductor substrate; a gate electrode formed at the third region; and a well region. The thyristor included a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, junctioned in order. The well region of the second conduction type is formed in the bulk semiconductor substrate, the third region is formed in the well region. A first voltage is impressed on the first region side of the thyristor, a second voltage higher than the first voltage is impressed on the fourth region side of the thyristor, and a voltage higher than or equal to the first voltage is impressed on the well region.

Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.

Abstract: A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material.

Abstract: A GaN-based heterostructure field effect transistor capable of accomplishing higher output, higher breakdown voltage, higher speed, higher frequency, and the like. A heterostructure field effect transistor including a channel layer (4) of GaN and a barrier layer (6) of AlGaN, wherein the surface of a transistor element has an insulating film (10).

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Abstract: A hetero-junction bipolar transistor is provided including emitter contact region, an emitter region made of a first semiconductor material, a base region made of a second semiconductor material having a smaller energy band gap than the first semiconductor material, a collector region made of the first semiconductor material, and a collector contact area, the regions being serially formed on a surface of a substrate in a direction parallel to the surface thereof. A buffer layer made of a third semiconductor material with an energy band gap larger than the first semiconductor material is provided between the emitter region, the base region, the collector region and the substrate surface. Emitter, base and collector electrodes are also provided, in contact with the emitter contact region, the base region, and the collector region, respectively.

Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

Abstract: ABSTRACT The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherein the integrated circuit anti-interference outline structure surrounds a periphery of a partial circuit within the integrated circuit and comprises a plurality of PNP structures. At a surface of the integrated circuits are two metal strips for producing a parasitic capacitance at poly layers in order to control noises within acceptable ranges. On a P-substrate therein is disposed with a deep N-well layer for connecting to an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area, and thus having noise currents overflow from a ground terminal as well as preventing the integrated circuit from invasions and leaks of electromagnetic waves.