Abstract: A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (140,940) is at a first side (131, 931) of the fin and a second gate dielectric (150, 950) is at a second side (132, 932) of the fin. A first metal region (160, 960) is adjacent to the first gate dielectric and has a first surface (161, 961), and a second metal region (170, 970) is adjacent to the second gate dielectric and has a second surface (171, 971). The first electrically insulating layer has a third surface (111, 911), the second electrically insulating layer has a fourth surface (121, 921), and the first surface and the second surface lie between the third and fourth surfaces.

Abstract: A system includes a photo beam detector. The photobeam detector senses a presence of an obstruction. The system also includes an apparatus to attach the photo beam detector to the moveable barrier. At least a portion of the photo beam detector is positioned at the moveable barrier such that a movement of the moveable barrier causes a simultaneous rotation of the portion of the photo beam detector. The system also includes a coupler and a controller. The controller is coupled to the photo beam detector via the coupler. The controller is programmed to determine whether the obstruction exists in a pathway of the moveable barrier from input received from the photo beam detector.

Abstract: An electro-optical device includes peripheral circuit wiring arranged in the peripheral area on the element substrate, and which has overlapping portions that overlap vertical conduction terminals on the element substrate in plan view. The overlapping portions are arranged on a lower layer side relative to the vertical conduction terminals.

Abstract: A charge-coupled device includes a photosensitive region for collecting charge in response to incident light; a first and third gate electrode made of a transmissive material spanning at least a portion of the photosensitive region; and a second gate electrode made of a transmissive material that is less transmissive than the first and third gates and spans at least a portion of the photosensitive region; wherein the first, second and third gates are arranged symmetrically within an area that spans the photosensitive region.

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract: A method of forming a semiconductor device is provided. A device isolation region is formed in a semiconductor substrate, thereby defining a device region in the semiconductor substrate. The device region has a flat main surface. The flat main surface is deformed into a round surface, thereby forming a surface-rounded device region. The surface-rounded device region includes a side portion that is adjacent to a boundary with the device isolation region. The surface-rounded device region has a convex shape in vertical cross section. An epitaxial layer is selectively formed on the round surface of the surface-rounded device region. A first ion-implantation process is carried out for introducing an impurity into at least one of the epitaxial layer and the surface-rounded device region.

Abstract: A fuse is formed by a borderless contact process that removes the silicon nitride layer above the cutting region of the fuse. The fuse is formed on a semiconductor substrate, and comprises an insulation layer such as an oxide layer formed on the substrate, a fuse layer formed on the insulation layer, where the fuse layer includes at least a first region and a second region, and a silicon nitride layer formed only above the first region of the fuse layer. The first region of the fuse layer is where contact holes are formed for applying electrical stress to the fuse, and the second region of the fuse layer is where the fuse is cut in response to electrical stress applied to the fuse. Because the silicon nitride layer is removed above the second region of the fuse layer, the silicon nitride layer does not inhibit the cutting of the fuse in response to electrical stress applied to the fuse.

Abstract: A radio frequency (RF) integrated circuit with electrostatic discharge (ESD) protection and an ESD protection apparatus thereof are provided. The ESD protection apparatus includes a substrate, an RF bonding pad, and an ESD protection unit. The RF bonding pad for transmitting RF signal is disposed upon the substrate. The ESD protection unit is disposed under the RF bonding pad. Wherein, The ESD protection unit includes an inductor electrically connected between the RF bonding pad and the power rail.

Abstract: An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance of the wire; the inductance is selected to fine-tune the high frequency characteristics of the circuit.

Abstract: An interconnect path configured for use in RFICs and configured to reduce inductance at the input of an array of cells, and also at the output of the array of cells. According to one preferred embodiment of the present invention, a multi-layered interconnect formed by at least two metal layers separated by dielectric medium is provided. The metal layers are closely spaced and separated by a desirable dielectric to achieve an interconnect having a characteristic inductance (Zo) that is much lower than typical microstrip transmission lines formed by a metal trace over the semiconductor substrate or a dielectric stack that includes the semiconductor substrate. The low Zo line provides much less inductance per unit length, and also provides an increase in the parasitic capacitance per unit length.

Abstract: A semiconductor structure of a high side driver and method for manufacturing the same is disclosed. The semiconductor of a high side driver includes an ion-doped junction and an isolation layer formed on the ion-doped junction. The ion-doped junction has a number of ion-doped deep wells, and the ion-doped deep wells are separated but partially linked with each other.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: A substrate 103 is set in a film-forming apparatus, such as a metal organic vapor phase epitaxy system 101, and a GaN buffer film 105, an undoped GaN film 107, and a GaN film 109 containing a p-type dopant are successively grown on the substrate 103 to form an epitaxial substrate E1. The semiconductor film 109 also contains hydrogen, which was included in a source gas, in addition to the p-type dopant. Then the epitaxial substrate E1 is placed in a short pulsed laser beam emitter 111. A laser beam LB1 is applied to a part or the whole of a surface of the epitaxial substrate E1 to activate the p-type dopant by making use of a multiphoton absorption process. When the substrate is irradiated with the pulsed laser beam LB1 which can induce multiphoton absorption, a p-type GaN film 109a is formed. There is thus provided a method of optically activating the p-type dopant in the semiconductor film to form the p-type semiconductor region, without use of thermal annealing.

Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.

Abstract: A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask. The core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the top surface; herein the interconnection portion includes a surface dielectric layer and a surface circuit layer disposed on the surface dielectric layer. The surface circuit layer is electrically connected to the circuit pattern. The solder mask is disposed on the interconnection portion; herein the solder mask includes a hole to identify the substrate structure. Besides, a method for manufacturing the substrate structure is disclosed.

Abstract: A spin coating apparatus includes a cleaning liquid ejection device that supplies a cleaning liquid primarily containing water to a surface of a lens base material, an antireflection-layer composition ejection device that supplies a composition for an antireflection layer to form an antireflection layer on the surface of the lens base material, a holding portion that rotatably holds the lens base material, a liquid storage portion that stores the liquids supplied from the cleaning liquid ejection device and the antireflection-layer composition ejection device to the lens base material and flowing down, an apparatus main body in which the lens base material is accommodated, an air supply device that supplies cleaning air to the apparatus main body, and an exhaust unit that exhausts contaminated air in the apparatus main body to the outside.

Abstract: A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.

Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.

Abstract: In an electrical connector, cross talk between signal contacts in adjacent linear columns and rows may be reduced by changing the size of the lead portions of the contacts extending within a leadframe housing. For example, the height of the ground contact lead portions may be increased to further isolate signal contacts in adjacent columns from interfering electrical fields. The height of the signal contact lead portions may be decreased in order to accommodate the larger ground contact lead portions without increasing the overall size of the connector. Smaller signal contact lead portions may reduce the overall length differential between signal contacts in a differential pair, thereby minimizing signal skew.

Abstract: A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a semiconductor chip and a circuit board. The semiconductor chip has a bond pad. The circuit board has a base substrate with a throughole, and a conductive film pattern placed on a sidewall of the throughole. The throughole is aligned with the bond pad to expose the bond pad. A connector located within the throughole electrically connects the conductive film pattern to the bond pad. A sealing layer covers the connector.

Abstract: A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.

Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.

Abstract: A semiconductor package and a process for fabricating such a package are presented. The package has a substantially parallelepipedal block, made of an encapsulation material. Embedded within the block is at least one integrated-circuit chip and a leadframe having functional leads for electrical connection to said chip. These functional leads emerge on the outside of said block via at least one side and are intended to be connected to a printed-circuit board. The leadframe does not have functional leads on at least one of the other sides of said block. For that other side, the leadframe includes auxiliary leads for electrical connection to said chip which emerge on the outside of said block via at least one of the sides of this block which do not have functional leads. These auxiliary lead are not intended to be connected to said printed-circuit board.

Abstract: A microelectronic package, a method of forming the package and a system incorporating the package. The package includes a substrate; a die bonded to the substrate; and a thermal sensor connected to the substrate.

Abstract: An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression.

Abstract: A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond and a non-metal-to-non-metal bond.

Abstract: An embedded metal heat sink for a semiconductor device and a method for manufacturing the same are described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit.

Abstract: A package using selectively anodized metal and a manufacturing method thereof are provided. The method includes a patterning step, an anodized metal film forming step, a via hole forming step, and a bump forming step. The pattering step is performed by attaching a masking material to a surface of a metal substrate for integrating semiconductor elements and patterning regions that will not be anodized. The anodized metal film forming step is performed by selectively anodizing the patterned metal substrate and forming a metal oxidation layer having a predetermined thickness. The via hole forming step is performed by forming the via holes in the metal oxidation layer. The bump forming step is performed by forming the bumps for surface-mounting.

Abstract: The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any of the substrate and the semiconductor chip, and has an opening.

Abstract: In various embodiments, semiconductor components and methods to manufacture semiconductor components are disclosed. In one embodiment, a method to manufacture semiconductor components includes attaching multiple heat spreaders to a semiconductor wafer. Other embodiments are described and claimed.

Abstract: At least one bearing body in a power semiconductor module has a surface section on which a first semiconductor component and at least one additional semiconductor component are arranged adjacent to each other. The semiconductor components have contact surfaces, oriented away from the surface section of the bearing body, that are in a contact in a planar manner to provide a flat connection line between the contact surfaces of the semiconductor components. The flat connection line has a lower inductivity and a lower instance dependency of inductivity compared to a bonding wire. A distance between the semiconductor components along the surface section is greater than a lateral measurement of at least one of the semiconductor components and can be, selectively, relatively large, allowing for thermal and/or temperature expansion and a lower thermal load of the semiconductor module than previously obtained.

Abstract: A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package.

Abstract: In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the first conductive pads. A package substrate may include a plurality of second conductive pads. A conductive adhesive layer may connect the first conductive pads and the second conductive pads.

Abstract: A system for low dielectric constant insulators is provided. One aspect of this disclosure relates to a method for forming an insulator. According to an embodiment of the method, a first structural material is applied as one or more layers of insulation to an integrated circuit surface, a damascene pattern is etched into the first structural material, a first barrier layer and a seed layer are deposited upon the insulation layer, a conductor layer is deposited upon the seed layer, at least a portion of the conductor layer is planarized and at least a portion of the first structural material is removed, a top barrier layer is deposited upon the conductor layer, and a final structural material is applied to replace at least a portion of the first structural material, the final structural material having a lower dielectric constant than the first structural material. Other aspects and embodiments are provided.

Abstract: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.

Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.

Abstract: A semiconductor device includes a first semiconductor chip face-down mounted on a substrate, a second semiconductor chip face-up mounted on the first semiconductor chip, and an electromagnetic shielding plate interposed between the first semiconductor chip and the second semiconductor chip.

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract: The Directive 2002/95/EC of the European Parliament and of the Council promulgated that from 1 Jul. 2006 new electrical and electronic equipment must no longer contain lead. Accordingly, lead-free solder alloys for various electrical and electronic applications have been developed. But at present, lead in high melting temperature type solders, e.g. used for die-attach applications, are exempted from the directive due to lack of lead-free alternatives for these alloys. The present invention provides a lead-free die-attach composition for attaching high power semiconductor devices to printed circuit boards. The die-attach composition comprises a metal filled epoxy resin, wherein the metal is selected from a powder comprising copper and having spheroidal particles with less than half of the copper atoms in a surface layer being oxidized as measured by XPS.

Abstract: A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one or more peripheral edges where the conductor ends are disposed at a side surface of the dielectric material. Stacks of such semiconductor dice, wherein one of the dice is configured with discrete conductive elements projecting from the active surface, and the exposed ends of the dice in the stack are connected with vertical interconnects. A probe card is disclosed having bond wires extending from more central contacts between more peripheral contacts to the edge of the probe card. A probe card having an upper layer bearing contacts and at least one window therethrough, a lower layer bearing conductive traces with ends exposed through the at least one window, and conductors extending from at least some of the contacts to conductive trace ends is also provided. Methods of making the foregoing structures are disclosed.

Abstract: A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.

Abstract: A pixel circuit includes a LED, first switch, second switch, first transistor, second transistor and capacitor. The LED has a first end receiving a first supply voltage. The first switch has a first terminal receiving a data signal and a control terminal receiving a scan signal. The second switch has a first terminal coupled to a second terminal of the first switch and a control terminal receiving the scan signal. The first transistor has a drain coupled to a second terminal of the second switch, a source receiving a second supply voltage and a gate coupled to the second terminal of the first switch. The second transistor has a drain coupled to the LED, a source receiving the second supply voltage, and a gate coupled to the first transistor. The capacitor has a first end coupled to the second transistor and a second end receiving the second supply voltage.

Abstract: A method of operating an evaporative cooling tower includes contacting water with air in a cooling zone to cool the water and heat the air and cooling the heated air to condense water therefrom, thereby to reduce water loss from the cooling tower. Typically, the cooling of the heated air is by means of evaporative cooling employing a refrigerant.

Abstract: The invention concerns a process for making a coated optical lens blank free of visible fining lines which comprises: (ix) providing an optical article having at least one fined but unpolished geometrically defined main face; (x) providing a mold part having an internal and external surface; (xi) depositing on said main face of said optical article or on the internal surface of the mold part a requisit amount of a liquid curable coating composition; (xii) moving relatively to each other the optical article and the mold part to either bring the coating composition into contact with the main face of the optical article or into contact with the internal face of the mold part; (xiii) applying pressure to the mold part to spread the liquid curable coating composition on said main face and form a uniform liquid coating composition layer onto the main face; (xiv) curing the liquid coating composition layer; (xv) withdrawing the mold part; and recovering the free of visible fining lines coated optical article.

Abstract: An adjustable mold includes a distortable boundary, a flexible membrane, and a pressurizer, and method of use thereof. Pressure is applied to the flexible membrane, which causes the membrane to distort over the boundary. The shape of the boundary and the distortion of the flexible membrane control the optical characteristics of a lens resulting from the application and curing of a molding composition placed on the flexible membrane or to cast other items having variable shapes determined in part by the flexible membrane. In addition, a mold edge is used to allow casting in predetermined shapes, reducing need for grinding or edging. Visual and emission device calibration features used in conjunction with calibration reference images allow uniform selective distortion of the flexible membrane.

Abstract: Methods and systems are provided for making an ophthalmic lens. The present methods and systems are effecting in coupling two mold sections together at two or more discrete regions. Embodiments of the methods and systems form a bore that extends completely through one of the mold sections and only partially through the other mold section. During formation of the bore, the mold material in proximity to the bore being formed becomes molten and diffuses from the bore. A portion of the molten mold material is provided at a contact point between the two mold sections and when the molten material cools, the material forms a spot weld between the mold sections. By forming multiple hollow spot welds in a mold assembly, the two mold sections can be securely coupled to each other during the manufacture of an ophthalmic lens, such as a silicone hydrogel contact lens.

Abstract: A method for manufacturing ophthalmic lenses, e.g. contact lenses, in particular soft contact lenses, comprises the steps of molding in a high volume manufacturing process a plurality of lenses (CL) having different properties, and transferring the respective molded lenses (CL) that have the same properties to a respective intermediate buffer (1;1a) so as to store therein a bulk of lenses (CL) having the same properties.