Abstract: A memory array includes a buried diffusion region, a first source line that supplies electrical power to the buried diffusion region, a second source line that supplies electrical power to the buried diffusion region, a first bitline transistor having a first channel width and a second bitline transistor having a second channel width. The first bitline transistor is proximate to the first source line and is electrically coupled to a first memory cell. The first bitline transistor is disposed between the first and second source lines. The second bitline transistor is proximate to the first bitline transistor and is electrically coupled to a second memory cell. The second bitline transistor is disposed between the first and second source lines and is farther from the first source line than the first bitline transistor. The second channel width is greater than the first channel width.

Abstract: In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from the plurality of read operations in a volatile array of the memory. In some embodiments, the nonvolatile array may be a flash-based array and the volatile array may be a random access memory.

Abstract: A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides multiple modes of operation including a DRAM mode using the capacitor and a non-volatile random access memory mode using the NROM transistor. The device is comprised of two source/drain regions between which a gate insulator layer is formed. A control gate, coupled to a word line, is formed on top of the gate insulator. The DRAM capacitor is coupled to one of the source/drain regions while the second source/drain region is coupled to a bit line that is eventually coupled to a sense amplifier for reading the state or states of the memory device.

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the thresheld voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks.

Abstract: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

Abstract: In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected wordline. The memory array may be a flash memory incorporating multi-level cell architecture, in one embodiment.

Abstract: To control the problem of program and erase disturb in flash memory arrays having multiple sectors of cells grouped in each isolation wells of the flash memory array, a refresh procedure is used that involves two readings of each of the cells in a “refresh area” of a group under different read timing conditions, with other read conditions being constant or varied as desired. Cells that yield the same result in both reads are not excessively disturbed and need not be reprogrammed. However, cells that read differently may be excessively disturbed and should be reprogrammed. The refresh procedure is particularly suitable for memory arrays with small sector size and many sectors per group. The memory arrays preferably incorporate memory cells that use hot electron programming and Fowler-Nordheim erase.

Abstract: A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable logic that is configured by a user. Depending on the type of user logic that is implemented by the user, the programmable logic device integrated circuit may have different timing needs for its memory blocks. The adjustable register and memory address decoder circuitry has associated programmable elements that are loaded with configuration data. The configuration data adjusts the timing characteristics of the adjustable register and memory address decoder circuitry to accommodate the user logic. The adjustable register and memory address decoder circuitry may be used to make setup and clock-to-output timing adjustments to optimize a logic design.

Abstract: A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical topology. Each of the combined differential amplifiers includes a pair of transistors coupled to each other as a current mirror. The current mirror transistors are coupled in series with a respective one of a pair of differential input transistors. A current source transistor is coupled to the differential input transistors, and it is self-biased by one of the current mirror transistors.

Abstract: A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired.

Abstract: Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.

Abstract: According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.

Abstract: A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.

Abstract: A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

Abstract: A first pump circuit is coupled to a first pump signal line and is configured to generate a first voltage greater than a power supply voltage at an output thereof responsive to transition of the first pump signal line from a ground voltage to the power supply voltage. A second pump circuit includes a first switching circuit configured to couple a first capacitor between the output of the first pump circuit and a ground voltage node responsive to the transition of a first pump signal line from the ground voltage to the power supply voltage to charge the first capacitor to the first voltage, and to couple a second capacitor between the first capacitor and a second pump signal line responsive to a transition of the second pump signal line from the ground voltage to the power supply voltage to generate a second voltage greater than the first voltage.

Abstract: A sense amplifier circuit for a non-volatile semiconductor memory device is used to output data written in a selected non-volatile memory cell and is constructed as a current mirror circuit including a first mirror transistor and a second mirror transistor of a mirror circuit. A selection gate transistor and a detection transistor of the selected non-volatile memory cell are included as part of a load circuit connected to a drain electrode of the second mirror transistor. The detection transistor has a drain electrode linked to a source electrode of the selection gate transistor. An operating current of the selection gate transistor is smaller than an operating current of the detection transistor, and an electric current output from the second mirror transistor is determined by the operating current of the selection gate transistor. This arrangement enables determination of the stable operating current of the memory cell irrespective of the state of a floating gate of the detection transistor.

Abstract: A semiconductor memory includes a plurality of memory portions; and a plurality of spare memory portions. The memory portion includes: a main cell array which includes memory cells, a first reference cell which stores a first reference data in a nonvolatile state, and a first sense amplifier which reads a first state of the memory cell based on the first state and a second state of the first reference cell. The memory cell stores data in a nonvolatile state. The spare memory portion includes: a spare cell array which includes spare cells as spares of the memory cells, a second reference cell which stores a second reference data in a nonvolatile state, and a second sense amplifier which reads a third state of the spare cell based on the third state and a fourth state of the second reference cell. The memory portion having a defect on the first reference cell is replaced with the spare memory portion.

Abstract: A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory cell and the complementary logic state of the stored bit is rewritten to a second storage node of the memory cell. One of the acts of rewriting is achievable faster than the other and the rewriting of the true and complementary logic states is completed upon achieving the one act of rewriting that is faster than the other.

Abstract: A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.

Abstract: A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.

Abstract: A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

Abstract: A semiconductor device in which a current consumption when a word line being selected is suppressed and accurate data reading is carried out. The semiconductor device of a semiconductor device of the invention comprises a data storage means and a power source control means. The data storage means has a plurality of memory cells. The power source control means has at least one power source line and a plurality of switches. In addition, the invention further comprises an address selection means having a selector circuit including a plurality of switches and an output bus, a first decoder circuit for selecting the switch in the selector circuit, and a second decoder circuit.

Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

Abstract: A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.

Abstract: A method for computing a pressure signal gradient. The method includes recording a plurality of pressure signals at least one of a first receiver and a second receiver. The first receiver and the second receiver are disposed within a cluster. The method further includes recording a plurality of pressure signals at the second receiver; computing a calibration filter for removing the difference in distortions between the pressure signals recorded at the first receiver and the pressure signals recorded at the second receiver; and computing the pressure signal gradient between the pressure signals recorded at the first receiver and the pressure signals recorded at the second receiver using the calibration filter.

Abstract: A system and methods for enhancing an image of post-stack seismic data, with pre-stack seismic data features, and displaying the enhanced image with the image of the post-stack seismic data are disclosed.

Abstract: An oscillating valve driven by the pressure in a mud pulser develops a pressure variation in the mud pulse signal that is at a frequency that is different than the frequencies of the mud system. The oscillating valve is coupled to or integral with the pulse drive cylinder, whether the drive means for operation of the pulser is upstream or downstream from the orifice. A bistable valve improves performance of the transmitting element at low flow rates by providing a toggle mechanism which assures positive seating of the bistable valve.

Abstract: The present invention is directed towards an acoustic concealed item detector and related methods for detection using acoustics. In an illustrative embodiment, a multi-frequency ultrasonic wave generator generates in a gaseous medium at least first and second ultrasonic waves. The multi-frequency ultrasonic wave generator is arranged such that in operation, the first ultrasonic wave and the second ultrasonic wave mix in a prescribed mixing zone to produce a difference-frequency acoustic wave. A receiver sensor detects the difference-frequency acoustic wave and produces corresponding electromagnetic signals. The electromagnetic signals are processed by a system processor and signals indicative of concealed items are identified. Preferably the ultrasonic waves are focused to a small prescribed mixing zone. Parametric and multi-transducer embodiments are disclosed.

Abstract: A method and apparatus is provided for suppressing noise which includes receiving a plurality of signals from an array of sensors and transforming each of these signals to the frequency domain. The transformed signals are beamformed so that noise sources can be identified by bearing and frequency range. A planewave-fit noise-suppression routine is then used to remove identified noise sources from the transformed signals and to provide a noise-suppressed transformed signal having signals from said identified noise sources suppressed.

Abstract: The invention provides transducer arrays which are capable of outputting sound beams having a relatively constant width, and with minimal sidelobes, across a range of frequencies. This is achieved by utilising one or more digital signal modifiers within the signal path between the input sound signal and the array of transducers. Variable window functions are also disclosed.

Abstract: Disclosed is a method for adjusting focus bias in an optical disk device. When a focus bias adjustment operation for an optical disk such as a DVD-RAM is performed, a focus bias offset value at which the smallest jitter value of a high frequency signal is detected is set as an optimum focus bias offset value. A physical information data area, which has an embossed form and is recorded in a data area of the disk in a dispersed manner, is detected so that the jitter value of the high frequency signal is measured only for areas other than the detected physical information data area. This achieves a focus bias adjustment operation optimal for an optical disk such as a DVD-RAM, thereby enabling a secure focusing servo operation thereof.

Abstract: An apparatus for recording data on and reproducing data from the disk in which a recording area is divided into sectors, includes a reproducing signal generator for generating a reproducing signal including sum signals V1 and V2 of radial pairs, a sum signal RF_sum, and a push-pull signal RF_pp from an optical signal reflected from the disk, a header area detector for generating a header area signal including a header area from the reproducing signal, a first synchronous signal level detector for detecting a magnitude Ivfo1 of a first synchronous signal in the first header by being synchronized with the header area signal, a second synchronous signal level detector for detecting a magnitude Ivfo3 of a second synchronous signal in the second header by being synchronized with the header area signal, and a balance calculator for calculating the balance of the magnitude Ivfo1 and the magnitude Ivfo3.

Abstract: An optical head in which focusing error is detected by a spot size method used for recording and/or reproducing information signals on or from an optical disc. The optical head includes a unit for correcting the spot shape between the objective lens and a photodetector device. The spot shape correcting unit corrects part or all of light spots formed on the photodetector by a light beam reflected back by the optical disc so that the spot diameter in a direction traversing a track on the optical disc will be larger than the spot diameter along the track.

Abstract: A recording apparatus for recording modulated data on a rewritable recording medium includes a data modulation section for modulating data in accordance with a prescribed modulation rule; a parameter value changing section for changing at least one parameter value of the prescribed modulation rule; and a recording section for recording the data modulated in accordance with the prescribed modulation rule on the recording medium.

Abstract: A disk device in which at the recovery job of a focus pull-in operation, a CPU supplies servo control means with the respective correction values of the rotational speed of an optical disk and the moving speed of a lens which are described in the data table of a RAM, and performs the focus pull-in operation and determines whether or not the focus pull-in operation is successfully performed at the respective adjustment steps, and if the focus pull-in operation is successfully performed, the servo control means changes the amount of movement of the lens in response to a surface swing of the optical disk.

Abstract: A method, an optical disk drive and a calibration system for modifying a 2T write strategy to improve recording quality. The method includes driving the optical disk drive for burning a test odd mark and a test even mark on an optical disk, detecting signal waveforms associated with the test odd mark and the test even mark, adjusting a plurality of writing periods used for forming an even mark according to the signal waveform of the test even mark, and adjusting a plurality of writing periods used for forming an odd mark according to the signal waveform of the test odd mark without utilizing the adjusted writing periods for the even mark.

Abstract: The method for reproducing records for the optical recording medium detects and compensates for detrack, tilt and defocus, having advantages in that: (1) the magnitude and the direction of detrack, tilt and defocus can be detected from a difference signal (for example, a read channel 2 signal or a tracking error signal obtained by processing the read channel 2 signal) between optical reflecting signals detected at the header fields staggered on the basis of the tract center, and compensates for detrack, tilt and defocus, thereby preventing deterioration of data quality caused by detrack, tilt and defocus during a recording/reproducing operation and enabling the stable operation of the system; and (2) the focus servo is rapidly stabilized to enable real-time recording as well as the stable operation of the system.

Abstract: The amount of light reflected from a disk is detected, and it is determined according to the amount of reflected light whether the disk is a recordable disk or a rewritable disk. The disk is controlled according to the result of determination such that it is rotated at a constant angular velocity (CAV) or at a constant linear velocity (CLV) and recording is executed. Further, rotation driving control of the disk is selected according to factors other than the type of the disk, such as according to whether random recording is allowed or not, according to a recording state in the disk, according to whether an alternative area is provided or not, according to a recording start position, or according to whether initialization is required or not. CLV control or CAV control is appropriately selected for a disk at recording to suppress a reduction in accessibility and a reduction in data transmission rate.

Abstract: The amount of light reflected from a disk is detected, and it is determined according to the amount of reflected light whether the disk is a recordable disk or a rewritable disk. The disk is controlled according to the result of determination such that it is rotated at a constant angular velocity (CAV) or at a constant linear velocity (CLV) and recording is executed. Further, rotation driving control of the disk is selected according to factors other than the type of the disk, such as according to whether random recording is allowed or not, according to a recording state in the disk, according to whether an alternative area is provided or not, according to a recording start position, or according to whether initialization is required or not. CLV control or CAV control is appropriately selected for a disk at recording to suppress a reduction in accessibility and a reduction in data transmission rate.

Abstract: The amount of light reflected from a disk is detected, and it is determined according to the amount of reflected light whether the disk is a recordable disk or a rewritable disk. The disk is controlled according to the result of determination such that it is rotated at a constant angular velocity (CAV) or at a constant linear velocity (CLV) and recording is executed. Further, rotation driving control of the disk is selected according to factors other than the type of the disk, such as according to whether random recording is allowed or not, according to a recording state in the disk, according to whether an alternative area is provided or not, according to a recording start position, or according to whether initialization is required or not. CLV control or CAV control is appropriately selected for a disk at recording to suppress a reduction in accessibility and a reduction in data transmission rate.

Abstract: A drive current or a drive voltage is controlled corresponding to change of load by sampling the drive current or drive voltage of a motor to move an optical pickup and then detecting change of the sampling signal as change of the optical pickup when it is moved. Moreover, change of the sampling signal is obtained from a difference of the sampling signals by comparing these sampling signals at the first and second points. Comparison of these sampling signals is conducted in unit of drive pulse.

Abstract: A method for recording data to optical media is provided. A selection of files to record from a source to a destination optical media is received, and an enumeration of the data files to record to the destination optical media is generated. The enumeration of data files includes the determining of whether any source file is in the enumeration of data files to record to the destination optical media more than one time. A destination file path node is mapped for each data file to be recorded to the destination optical media, and the selection of data files is recorded to the destination optical media. The recording includes only one occurrence of any source file in the enumeration of data files to record to the destination optical media.

Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.

Abstract: A diffractive optical element, comprises a first diffractive structure to generate n11-th order diffracted ray when a first light flux having ?1 (nm) of a wavelength comes in and to generate n21-th order diffracted ray (n11.?n21) when a second light flux having ?2 (nm) (?2>?1) comes in; and a second diffractive structure to generate n12-th order diffracted ray when the first light flux comes in and to generate n22-th order diffracted ray (n12.?n22) when the second light comes in. The diffractive optical element satisfies the following formula: ??A12???B12, where ??A12={n11·?1/(N11?1)}/{n21·?2/(N21?1)}, and ??B12={n12·?1/(N12?1)}/{n22·?2/(N22?1)}, wherein N11, N21 are refractive index of the first diffractive structure respectively for ?1 and ?2, and N12, N22 are refractive index of the second diffractive structure respectively for ?1 and ?2.

Abstract: The present invention is applicable to a recording apparatus of a CD or DVD, a recording method thereof and a recording medium, and an object of the present invention is to clearly record a second information such as characters and figures between two recording levels in an optical disk. The second information is recorded in a predetermined area in a radius direction and a angular direction on the optical information recording medium, and further, the second information is recorded according to a change of a pit width based on a change of power of the laser beam, a change of a pit length based on an on/off control of the laser beam, or a change of depression or bulge of the pit based on a change in the vicinity of the on/off control of the laser beam. Whereby it is possible to record the second information such as a watermark pattern or a visible image, which is capable of being confirmed by seeing a disk.

Abstract: On an information recording medium, an entire stream including a plurality of portion streams, each of which is provided with content information including still picture information, is multiplexed-and-recorded by a unit of packet. The information recording medium is provided with a file for storing object data, which is provided with a plurality of packets, each of which stores therein a piece of the content information. The information recording medium is further provided with a file for storing information which defines a reproduction sequence of the object data. The object data includes packets, each packet storing therein a piece of respective one of still picture information sets, the still picture information set including still picture information and control information thereof. A display control to the still picture information included in one still picture information set is described by the control information included in another still picture information set.

Abstract: A modulation channelization, demodulation and error-control system based on orthogonal bipolar spreading vectors is provided that permits a variable information rate to be transmitted without inducing envelope fluctuations and which permits multiple access without requiring the transmitter amplifier to support the combined information rate of all users. The modulation system uses the Hadamard matrix vectors to form communication channels. The information rate on any channel may be doubled by using half the vector length to transmit information. The vector that is not orthogonal-in-the-half to the rate-doubled vector is deactivated. Similarly, higher information rates may be provided through truncation of the transmission vector and the elimination of the resultant non-orthogonal vectors. The system provides biorthogonal coding in addition to multirate communication.

Abstract: A method of mode detection for OFDM signals. The method comprises the steps of delaying the OFDM signal for a first and second number of samples, multiplying the two delayed signals by coefficient signals, and deriving a sum of the two products, deriving an error signal by subtracting the sum of the two products from the OFDM signal, extracting amplitudes of the coefficient signals, and accordingly deriving step size signals, updating the coefficient signals according to the error signal and step size signals, detecting edges of the amplitudes of the coefficient signals, and determining the guard interval length and transmission mode according to the detected edges.

Abstract: Provided is a frame synchronization pattern design and synchronization method by which in a transmitter of a communications system employing an orthogonal frequency division multiplexing (OFDM), a frame synchronization pattern is inserted into the starting part of a symbol frame, and by detecting the frame synchronization pattern in a receiver, synchronization of the OFDM transmitter and receiver is performed. Also, provided are a transmitter synchronization apparatus including an OFDM symbol frame generation unit, a frame synchronization pattern insertion unit, and an OFDM transmission signal conversion unit, and a receiver synchronization apparatus comprising a frame synchronization pattern inserted OFDM symbol frame conversion unit, a frame synchronization pattern detection unit, and a source data generation unit.