Abstract: The invention describes a method to diagnose the autoimmune disease activity by detecting the presence of an autoimmune specific MHC-peptide complex in a patient suffering from an autoimmune disease. The MHC-peptide complex is associated with rheumatoid arthritis. Monoclonals antibodies to be used for this method are also described. The antibodies can also be used for therapeutic purposes.

Abstract: The invention relates to a method for assaying the teichoic acids present, most commonly in residual form, in a preparation of Gram+ bacterial antigens. This method requires, first of all, a controlled hydrolysis with hydrofluoric acid at a temperature of less than or equal to 40° C., in order to release the oligosaccharides specific for teichoic acids. The assaying of the specific oligosaccharides can then be carried out by various techniques, in particular by high performance chromatography coupled with pulsed amperometric detection (HPAEC-PAD). The method according to the invention can in particular be used to assay the residual amounts of teichoic acids present in preparations containing capsular polysaccharides of Streptococcus pneumoniae, which may be useful as vaccines.

Abstract: HCV assays are described. The assays utilize a 24 kd protein capable of binding the E2 envelope protein of hepatitis C virus (HCV), or functionally equivalent variants or fragments of the 24 kd protein.

Abstract: A method is described for improving the nutritional value of a foodstuff comprising a source of myo-inositol hexakisphosphate by feeding the foodstuff in combination with a phytase expressed in yeast. The method comprises the step of feeding the animal the foodstuff in combination with a phytase expressed in yeast wherein the phytase can be selected from the group consisting of AppA1, AppA2 and a site-directed mutant of AppA. The invention also enables reduction of the feed to weight gain ratio and an increase bone mass and mineral content of an animal. A foodstuff and a feed additive comprising AppA2 or a site-directed mutant of AppA are also described.

Abstract: The present invention relates to a DNA encoding a polypeptide with dihydroorotase (EC 3.5.2.3) activity. Also, the invention relates to the use of this nucleic acid for the generation of an assay system.

Abstract: The present invention concerns a further development and use of biological assays to determine the amount or concentration of an active ingredient present in a sample. The enzyme assay of the present invention determines the amount or concentration of protease inhibitors, including retroviral protease inhibitors such as HIV inhibitors.

Abstract: The invention relates to a method of determining the binding site specificity of an analyte to a ligand having at least two different binding sites, which method comprises immobilizing the ligand to a solid support, mixing the analyte with a reversibly binding reference analyte which has a dissociation behaviour that differs significantly from that of the analyte, contacting the mixture with the ligand to determine dissociation characteristics for the mixture, and determining therefrom the binding site specificity of the analyte in relation to the reference analyte. The invention also relates to an analytical system for carrying out the method, and to a computer program, computer program product and computer system for performing the method.

Abstract: A gene encoding a polypeptide having an activity to support proliferation or survival of hematopoietic stem cells or hematopoietic progenitor cells is isolated by comparing expressed genes between cells which support proliferation or survival of hematopoietic stem cells or hematopoietic progenitor cells which do not support the proliferation or survival. Proliferation or survival of hematopoietic stem cells or hematopoietic progenitor cells is supported by using stromal cells in which the isolated gene is expressed or a gene product of the isolated gene.

Abstract: Provided are Nocardia farcinica-specific primers comprising the nucleotide sequence of SEQ ID NO:1-39. Provided is a polynucleotide represented by SEQ ID NO:41 and SEQ ID NO:40. Further provided is a method of identifying a Nocardia farcinica infection in a subject with the primer identified by SEQ ID NO:1-39, or detecting the presence of a polynucleotide consisting of the nucleotide sequence represented by SEQ ID NO:40 or SEQ ID NO:41. Also provided is a method of identifying Nocardia farcinica infection in a subject by amplifying DNA from the subject using a Nocardia farcinica-specific primer comprising a nucleotide sequence selected from the group consisting of SEQ ID NO:1-39. Further provided is a kit for identifying Nocardia farcinica comprising a Nocardia farcinica-specific primer comprising SEQ ID: NO:1-39 and a kit for identifying Nocardia farcinica comprising a Nocardia farcinica specific primer capable of amplifying SEQ ID NO:41.

Abstract: The invention relates to a process for the preparation of L-amino acids, in particular L-threonine, which comprises overexpressing a ptsG gene coding for the glucose-specific IIBC component of the phosphotransferase system in Enterobacteriaceae.

Abstract: The invention aims at providing a process for producing coenzyme Q10 efficiently in microorganisms by utilizing a coenzyme Q10 side chain synthesis gene derived from a fungal species belonging to the genus Aspergillus and genus Leucosporidium. The present invention relates to a DNA having a DNA sequence described under SEQ ID NO:1 and 2 or derived from the above sequence by deletion, addition, insertion and/or substitution of one or several bases and encoding a protein having decaprenyl diphosphate synthase activity.

Abstract: A process for forming a color and odor stable polycarboxylic acid or polyhydroxy acid is provided. The process is carried out by fermenting a mixture containing a substrate which can be converted by fermentation into a polycarboxylic acid or a polyhydroxy acid, an organism capable of transforming the substrate by fermentation in a fermentation medium containing a source of carbon and energy, a source of inorganic nitrogen, a source of phosphate, a metal, a biotin which is substantially free of particulate matter and bacteria.

Abstract: A method of perforating a membrane 10 is presented. The method comprises: bringing a membrane-denaturing substance into contact with or close proximity to at least a site of said membrane 10, said substance inducing a membrane-denaturing reaction by a stimulus; providing said stimulus to said substance so as to denature said membrane 10; perforating said membrane with a membrane-destroying member 1. The stimulus is carried through said membrane-destroying member 1. The present invention eliminates the influence of membrane-denaturing agent to the substance to be injected into the cell. The present invention also enables applying the stimulus locally, with a simple construction.

Abstract: The present invention provides a novel ?-glucosidase nucleic acid sequence, designated bgl4, and the corresponding BGL4 amino acid sequence. The invention also provides expression vectors and host cells comprising a nucleic acid sequence encoding BGL4, recombinant BGL4 proteins and methods for producing the same.

Abstract: The invention relates to novel alkaline protease variants. These variants have, when enumerating the alkaline protease from Bacillus lentus, variations in amino acid position 61, positions 199 and/or 211 and, optionally, at least one modification that contributes to the stabilization of the molecule, said modification preferably being point mutations in positions 3 and/or 4. Particularly preferred are variants S3T/V41/G61A/V199] and S3T/V41/G61A/V1991/L211D of B. lentus alkaline protease. The invention also relates to the possible use of these enzymes in diverse technical processes and, in particular, to detergents and cleansers containing these novel alkaline protease variants.

Abstract: A pure polypeptide containing an amino acid sequence at least 80% identical to SEQ ID NO:5. The polypeptide, when expressed in a cell, increases susceptibility of the cell to hepatitis C virus infection.

Abstract: A device and a method for the cultivation of cells is disclosed that utilizes external pneumatic pressure responsive to liquid level sensors to gently recirculate and cause turbulence in cell growth medium to promote cell growth without any shearing action and without a stir motor or mechanical manipulation means.

Abstract: Amphiphilic lipopeptide compositions for gene delivery are disclosed. An illustrative amphiphilic lipopeptide composition includes a human protamine 2 peptide conjugated to a hydrophobic moiety. Illustrative hydrophobic moieties include sterols, bile acids, and fatty acids. The amphiphilic lipopeptide composition is mixed with a nucleic acid such that the nucleic acid binds to the peptide portion of the lipopeptide. This mixture is placed in contact with mammalian cells to effect transfection of the cells with the nucleic acid. A method of making such amphiphilic lipopeptides is also described.

Abstract: Disclosed are methods for isolating sperm cells from an aqueous sample and kits for isolating sperm cells from an aqueous sample.

Abstract: The present invention relates to methods for producing plants having enhanced disease resistance. NRC1 proteins and nucleic acid sequences encoding these are provided, as well as transgenic plants producing NRC1 proteins.

Abstract: Methods are disclosed which separate and identify lipoproteins in biological samples. An ultracentrifuge density gradient is used to separate lipoprotein fractions. The fractions are visualized, resulting in a lipoprotein profile. The fractions can be further analyzed by a wide array of laboratory and clinical methods. The lipoprotein profile can be used in clinical diagnoses and other medical applications.

Abstract: The present invention concerns methods and kits for diagnosing a disease condition characterized by non-physiological levels of hepcidin, comprising obtaining a tissue or fluid sample from a subject; contacting the sample with an antibody or fragment thereof that specifically binds to a polypeptide corresponding to the mid-portion or C terminus of a hepcidin protein, and quantifying the hepcidin level using an assay based on binding of the antibody and the polypeptide; wherein the non-physiological level of hepcidin is indicative of the disease condition. The present invention also concerns diagnostic methods and kits for applications in genetic technological approaches, such as for overexpressing or downregulating hepcidin. The present invention further concerns therapeutic treatment of certain diseases by treatment of subjects with hepcidin and agonists or antagonists of hepcidin.

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.

Abstract: Electronic devices are disclosed that may be used for infrared radiation detection. An example electronic device includes a substrate, a transistor included in the substrate and a silicon-germanium (Si—Ge) structural layer coupled with the transistor. The structural layer has a stress in a predetermined range, where the predetermined range for the stress is selected prior to deposition of the structural layer. Also, the structural layer is deposited on the substrate subsequent to formation of the transistor such that deposition of the structural layer does not substantially adversely affect the operation of the transistor.

Abstract: A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

Abstract: A semiconductor laser device of the present invention includes: an active layer formed on a substrate; a first semiconductor layer formed on the active layer and made of a nitride semiconductor of a first conductivity type; a multilayer film formed on the first semiconductor layer and having a groove; and a second semiconductor layer formed on the multilayer film to fill the groove and made of a nitride semiconductor of the first conductivity type. The multilayer film is composed of a plurality of thin films containing a nitride semiconductor of a second conductivity type, and one of the thin films formed as the uppermost film is made of gallium nitride.

Abstract: A method of forming a micro-display includes forming a device that includes forming a partially reflecting layer on a first substrate and forming a plate overlying the partially reflecting layer, and adhering the device to a second substrate.

Abstract: Before cutting a gang-printed substrate having a multiplicity of liquid crystal display panel regions provided thereon into individual liquid crystal display panels, a voltage is applied to all of the multiplicity of liquid crystal display panel regions to inspect display defects, polymerize a monomer in the liquid crystal component, and control alignment of the liquid crystal, which allows the time required for a voltage applying step to be reduced and allows a reduction in the manufacturing cost. A dispenser injection process is used to allow a liquid crystal to be injected between mother boards that have not been cut into individual display panels, and a voltage is applied after the pair of glass substrates are combined and before they are cut into individual display panels to perform a test on display defects (dynamic operating test), pretilt control, and an aligning process.

Abstract: A fabrication method for a chip packaging structure disclosed herein is utilizing the method of plating metal to connect different layers so as to replace the traditional method that drill hole firstly and then plate metal in the hole. In the present invention, the metal in the conductive through hole is solid metal so as can provide good ability of heat sinking. Besides, the present fabrication method utilizes the existing manufacturing processes without extra process or equipment so as can decrease the PCB processes and lower the package cost.

Abstract: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Abstract: A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one side of the member to close one end of each aperture. After devices are inserted into the apertures with their first ends “up” and their second ends “down,” a second removable cover is attached to the other side of the member to close the other end of each aperture. After inverting the assembly, removal of the first cover presents the devices in the apertures with their second ends “up” and their first ends “down.

Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract: A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

Abstract: Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions. A first gate electrode is provided on the first active region. The first gate electrode has a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region. A second gate electrode is provided on the second active region. An insulating layer is provided on the first, second and third active regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode. The first gate electrode is free of a gate contact hole on the first portion of the first gate electrode. A second gate contact hole is provided on the second active region that exposes at least a portion of the second gate electrode.

Abstract: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes are supported at least in part with a retaining structure which engages the sidewalls, with the retaining structure comprising a fluid previous material. A capacitor dielectric material is deposited over the capacitor electrodes through the fluid previous material of the retaining structure effective to deposit capacitor dielectric material over portions of the sidewalls received below the retaining structure. Capacitor electrode material is deposited over the capacitor dielectric material through the fluid previous material of the retaining structure effective to deposit capacitor electrode material over at least some of the capacitor dielectric material received below the retaining structure. Integrated circuitry independent of method of fabrication is also contemplated.

Abstract: A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower portion of the trench; forming a dielectric layer of the trench capacitor; and forming a second electrode of the trench capacitor in the trench. The buried isolation layer intersects with the trench and has one or more gaps for providing body contact between a first substrate area above the buried isolation layer and a second substrate area below the buried isolation layer.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to form at least one memory cell stack. The memory device is cleaned to remove the mask. A silicide region is formed within the second layer in the at least one memory cell stack, where the silicide region in each memory cell stack is bounded by the spacers.

Abstract: The present invention relates to a method of manufacturing a flash memory device. According to the method of manufacturing the flash memory device, a gate line is formed to have a structure in which a tunnel oxide film, a polysilicon layer for floating gate, dielectric films and a polysilicon layer for a control gate are stacked, etch damages are compensated for by means of an oxidization process, and a metal layer formed on the polysilicon layer for control gate is formed by means of a damascene process. Accordingly, it is possible to sufficiently compensate for etch damages, prevent generation of abnormal oxidization in a metal layer, and improve the reliability of a process and electrical characteristics of a device accordingly.

Abstract: When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer.

Abstract: Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. A PSG (HDP-PSG: Phospho Silicate Glass) film containing a conductive impurity is formed as an interlayer insulating film for burying the gate electrode structures at film-formation temperature of 650° C. or lower by a high-density plasma CVD (HDP-CVD) method.

Abstract: A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Abstract: A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenches; forming a gate conductive layer on the entire surface of the resulting structure so that the trenches are buried; forming a silicon-rich amorphous metal silicide layer and a gate hard mask on the gate conductive layer; etching the resulting structure until upper portions of the gate conductive layer are removed by a predetermined thickness, upon first patterning for gate stacks, and forming a metal layer on the entire surface of the resulting structure; forming lateral metal capping layers on sides of the silicon-rich amorphous metal silicide layer by blanket etching, completing formation of gate stacks; and thermally processing the silicon-rich amorphous metal silicide layer to form a crystallized metal silicide layer.

Abstract: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

Abstract: A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.

Abstract: An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second bipolar transistor has a second collector region of this first conductivity type grown by this epitaxial layer. The first collector region also has a first collector drift zone, and the second collector region has a second collector drift zone. Whereby, the first collector drift zone is shortened as compared to the second collector drift zone by partial etching of the epitaxial layer.