Patents Issued in January 22, 2008
  • Patent number: 7320923
    Abstract: A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching the stack, to expose the substrate and keep the stack in the form of a line; forming insulating spacers on the lateral walls of the line; performing an epitaxial growth of a single-crystal semiconductor on the substrate, on either side of the line; selectively removing the third insulating layer to partially expose the second insulating layer at a predetermined location; and depositing and etching a conductive material to fill the cavity formed by the previous removal of the third insulating layer.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 22, 2008
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Bertrand Borot, Philippe Coronel
  • Patent number: 7320924
    Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 22, 2008
    Assignees: NEC TOKIN Corporation, NEC TOKIN Toyama, Ltd.
    Inventors: Fumio Kida, Makoto Nakano
  • Patent number: 7320925
    Abstract: A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region. A method for the production of an SOI substrate, includes forming on the surface of a semiconductor substrate made of a silicon single crystal a protective film designated to serve as a mask for ion implantation, forming an opening part of a stated pattern in the protective film, implanting oxygen ions into the surface of the semiconductor substrate in a direction not perpendicular thereto, and heat treating the semiconductor substrate thereby forming a buried oxide film in the semiconductor substrate, and inducing at the step of implanting oxygen ions into the surface of the semiconductor substrate the impartation of at least two angles to be formed between the projection of the flux of implantation of oxygen ions and a specific azimuth of the main body of the substrate.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 22, 2008
    Assignee: Siltronic AG
    Inventors: Tsutomu Sasaki, Seiji Takayama, Atsuki Matsumura
  • Patent number: 7320926
    Abstract: A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: January 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Min-Hwa Chi
  • Patent number: 7320927
    Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: January 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Juanita DeLoach, Brian A. Smith
  • Patent number: 7320928
    Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, David Staintes, Shriram Ramanathan
  • Patent number: 7320929
    Abstract: In order to adjust thickness of a bonded silicon single crystal film 15 depending of thickness of an SOI layer 5 to be obtained, depth of formation d1+tx of a separatory ion implanted layer 4, measured from a first main surface J, in the separatory ion implanted layer formation step is adjusted through energy of the ion implantation. Dose of the ion implantation is set smaller as the depth of formation measured from the first main surface J becomes smaller. A smaller dose results in a smaller surface roughness of the separation surface, and makes it possible to reduce polishing stock removal of the separation surface of the bonded silicon single crystal film in the planarization step. Uniformity in the thickness of the SOI layer can consequently be improved even for the case where a thin SOI layer has to be formed.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: January 22, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Kiyoshi Mitani
  • Patent number: 7320930
    Abstract: Wafer scale and substrate processing device singulation methods, and devices made by the methods, for singulation of discrete devices from a processed wafer or laminated structures, involves formation of separation scribes or saw cuts at multiple elevations in intersecting scribe streets or lines so that a separation cut in one direction is at a different depth than a separation cut in a different and intersecting direction. Separation or fracture of the wafer or laminated structure along one of the separation cuts does not transfer to the separation line of the intersecting separation cut due to the difference in depth of the intersecting cuts or scribes, and due to the difference in elevation of the bottom surfaces of the cuts or scribes within the scribe streets, resulting in cleaner edges on the separated devices.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: January 22, 2008
    Assignee: HANA Microdisplay Technologies, Inc.
    Inventor: Dean Eshleman
  • Patent number: 7320931
    Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: January 22, 2008
    Assignee: Freescale Semiconductor Inc.
    Inventors: Shawn G. Thomas, Vida Ilderem, Papu D. Maniar
  • Patent number: 7320932
    Abstract: A semiconductor device of the present invention is furnished with (a) a first protection film, formed on a substrate, having an opening section on an electrode pad, (b) a protrusion electrode, connected on the electrode pad at the opening section, whose peripheral portion is formed to overlap the first protection film, (c) a second protection film, formed to cover at least a gap at a boundary portion of the first protection film and the protrusion electrode, having an opening on a top area of the protrusion electrode except a portion around the boundary portion of the first protection film and the protrusion electrode, and (d) a coating layer formed to cover a surface of the protrusion electrode at the opening of the second protection film. With this arrangement, it is possible to provide a semiconductor device wherein the protrusion electrode is formed with an electroless plating method, capable of preventing the lowering of the adhesion strength of the protrusion electrode to the electrode pad.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: January 22, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinji Yamaguchi, Takuro Asazu, Atsushi Ono
  • Patent number: 7320933
    Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: January 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Kian Chai Lee, Sian Yong Khoo
  • Patent number: 7320934
    Abstract: A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: January 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Nicolas Nagel, Dominik Olligs
  • Patent number: 7320935
    Abstract: The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Jihperng Leu, Christopher D. Thomas
  • Patent number: 7320936
    Abstract: An insulating layer (5) and a conductive seed layer (6) are applied to a substrate (1) in a simple process. A photo resist with palladium chloride are provided in a bath for electrophoretic deposition onto the substrate. The photo resist is an insulator and the palladium chloride is a catalyst. The layer is heated with UV to cure it. The layer is plasma etched to expose more of the palladium chloride, which acts as a catalyst for electrodes plating of the conductive seed layer. A thicker conductive layer (7) is then electroplated onto the seed layer. These steps may be repeated for successive insulating and/or conductive layers.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: January 22, 2008
    Assignee: University College Cork - National University of Ireland, Cork
    Inventors: Magall Brunet, Andrew Mark Connell, Paul McCloskey, Terence O'Donnell, Stephen O'Reilly, Sean Cian O'Mathuna
  • Patent number: 7320937
    Abstract: The present invention is a reliable method of electroless-plating integrated circuit die that achieves high yield. Die are attached to a holder using a polyimide adhesive to eliminate voltage differences on bond pads which would otherwise interfere with the plating. The die are aggressively cleaned using multiple cleaning solutions, one heated to a user-defined temperature. Each cleaning is followed by an aggressive rinse in de-ionized water. Die are immersed into multiple metal solutions at user-definable temperatures. Each immersion is followed by an aggressive rinse in de-ionized water, one with heated de-ionized water.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: January 22, 2008
    Assignee: The United States of America as represented by the National Security Agency
    Inventors: Rathindra N. Pal, Kingsley R. Berlin
  • Patent number: 7320938
    Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: January 22, 2008
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Robert J. Purtell, Yun-Yu Wang, Keith Kwong Hon Wong
  • Patent number: 7320939
    Abstract: A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: January 22, 2008
    Assignees: Interuniversitair Microelektronica Centrum (IMEC), Koninklijke Philips Electronics N.V.
    Inventors: Robert Lander, Marcus Johannes Henricus van Dal, Jacob Christopher Hooker
  • Patent number: 7320940
    Abstract: In a method for manufacturing an acceleration sensor device, a lid for covering an opening of a package body is prepared by stamping. The lid is plated and plating films are formed on surfaces of the lid. The burrs formed on the surfaces of the lid in the plating process are removed by chemical polishing. A semiconductor sensor chip is inserted in the package body through the opening and fixed. Then, the lid 70 is attached to the package body.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 22, 2008
    Assignees: DENSO CORPORATION, Yoshikawa Kogyo Co., Ltd.
    Inventors: Tomohito Kunda, Tsukasa Fukurai
  • Patent number: 7320941
    Abstract: There is disclosed a plasma technique in which a plasma generation technique frequently used in various fields including a semiconductor manufacturing process is used, and generation of plasma instability (high-speed impedance change of a plasma) can efficiently be suppressed and controlled in order to manufacture stable products. In a method of disposing an object in a chamber and generating the plasma to treat the object, the chamber is sealed by a surrounding member so as to have an inner space, at least a part of the member includes a dielectric material, an RF induction coil is disposed outside the dielectric member, and a direct-current electric field is supplied into the inner space by a method of passing a direct current through the RF induction coil or another method, so that the plasma is stabilized.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: January 22, 2008
    Assignee: Lam Research Corporation
    Inventors: Takumasa Nishida, Shu Nakajima
  • Patent number: 7320942
    Abstract: A method for removal of metallic residue from a substrate after a plasma etch process in a semiconductor substrate processing system by cleaning the substrate in a hydrogen fluoride solution.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: January 22, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Xiaoyi Chen, Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Ralph C. Kerns, Ying Rui, Chun Yan, Guowen Ding, Wai-Fan Yau
  • Patent number: 7320943
    Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 22, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kee-Jeung Lee
  • Patent number: 7320944
    Abstract: A method of forming a phosphosilicate glass, includes flowing a pre-deposition gas comprising an inert gas into a deposition chamber containing a substrate, where the temperature of the substrate is at a pre-deposition temperature of at least 400° C; continuously increasing the temperature of gas in the chamber to a deposition temperature and simultaneously continuously increasing a flow rate of phosphine and silane until a phosphine:silane deposition ratio is achieved; and depositing the phosphosilicate glass on the substrate at the deposition temperature and at the phosphine:silane deposition ratio.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 22, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Michal Efrati Fastow, Ryan Holler
  • Patent number: 7320945
    Abstract: A thin film dielectric layer comprises a top portion and a bottom portion and has density and permittivity characteristics that vary substantially uniformly from the top portion to the bottom portion. Control over the density and/or permittivity is accomplished through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lih-Ping Li, Syun-Ming Jang
  • Patent number: 7320946
    Abstract: A dynamic mask module is disclosed, which comprises a microcomputer system, a mask pattern generator and a light source. The mask pattern generator is disposed over a substrate and electrically connected to the microcomputer system. The microcomputer system transmits an image signal to the mask pattern generator. The light source is disposed over the mask pattern generator to a photo-resist layer on the substrate. The mask pattern generated by the dynamic mask module is a dynamic image and the mask pattern can be changed on anytime. In addition, the manufacturing cost can be and the manufacturing time can be reduced.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: January 22, 2008
    Assignee: National Taiwan University of Science and Technology
    Inventors: Jeng-Ywan Jeng, Jia-Chang Wang, Chang-Ho Shen
  • Patent number: 7320947
    Abstract: The present invention relates generally to a static dissipative textile having an electrically conductive surface achieved by coating the textile with an electrically conductive coating in a variety of patterns. The electrically conductive coating is comprised of a conducting agent and a binding agent, and optionally a dispersing agent and/or a thickening agent. The static dissipative textile generally comprises a fabric which may be screen printed or otherwise coated with a conductive coating on the backside of the fabric so that the conductive coating does not interfere with the appearance of the face of the fabric. The economically produced fabric exhibits relatively permanent static dissipation properties and conducts electric charge at virtually any humidity, while the conductive coating does not detrimentally affect the overall appearance or tactile properties of the fabric.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: January 22, 2008
    Assignee: Milliken & Company
    Inventors: Andrew D. Child, Alfred R. Deangelis
  • Patent number: 7320948
    Abstract: An extensible laminate having improved set and hysteresis is disclosed. The extensible laminate includes an extensible nonwoven web laminated to an elastomeric sheet that have been mechanically stretched in the cross direction after lamination. A method for making the extensible laminate includes laminating an extensible nonwoven web to an elastomeric sheet to form a laminate and mechanically stretching the laminate in a cross direction by at least about 50 percent.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 22, 2008
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Michael Tod Morman, Sjon-Paul Lee Conyer, Gregory Todd Sudduth, Randall James Palmer, David Michael Matela, Prasad Shrikrishna Potnis
  • Patent number: 7320949
    Abstract: An optical glass suitable for precision mold pressing has a refractive index (nd) of 1.88 or over and an Abbe number (? d) within a range from 22 to 28, comprises, in mass %, SiO2 15-25%? B2O3 0-5%? La2O3 0-5%? TiO2 5-15% ZrO2 0-10% Nb2O5 more than 30% and less than 50% WO3 0-5%? CaO 0-10% BaO 0-10% Li2O 3-12% Na2O 0-10% K2O 0-10% Bi2O3 0-15% Ta2O5 0-7%? and has a glass transition point (Tg) within a range from 500° C. to 580° C. The optical glass preferably has a yield point (At) within a range from 550° C. to 640° C.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 22, 2008
    Assignee: Kabushiki Kaisha Ohara
    Inventor: Susumu Uehara
  • Patent number: 7320950
    Abstract: The propylene polymer of the present invention satisfies (1) a 25° C. hexane soluble content (H25) of 0-80 wt %; and (2) either no melting temperature (Tm) measurable by differential scanning calorimetry (DSC), or a melting temperature (Tm) satisfying, if measurable by DSC, the following relationship: ?H?3×(Tm?120) wherein ?H is a melting endotherm (J/g). The propylene homopolymer of the present invention satisfies (1) a meso pentad fraction (mmmm) of 30-60 mol %; (2) a racemic pentad fraction (rrrr) satisfying the following relationship: [rrrr/(1?mmmm)]?0.1; (3) a fraction (W25) eluted at a temperatures up to 25° C. by temperature-programmed chromatography, of from 20-100 wt %; and, (4) a pentad fraction (rmrm) of more than 2.5 mol %. The propylene copolymer of the present invention satisfies (1) a stereoregularity index (P) of 55-90 mol % as determined by 13C-NMR measurement; and (2) a fraction (W25) eluted at a temperatures up to 25° C. by temperature-programmed chromatography, of from 20-100 wt %.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 22, 2008
    Assignee: Idemitsu Kosan Co., Ltd,
    Inventors: Takuji Okamoto, Takashi Kashiwamura, Noriyuki Tani, Yutaka Minami, Masami Kanamaru, Koji Kakigami
  • Patent number: 7320951
    Abstract: The drilling mud with a lowered coefficient of friction having a silicate-based mud and a lubricant selected from the group consisting of: glycosides, alkylpolyalkoxyalcohols, alcohol ester polymers, amine phosphates, starch and combinations thereof.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: January 22, 2008
    Assignee: Shell Oil Company
    Inventors: Michele Scott Albrecht, Kenneth Michael Cowan, Robert Irving McNeil, III, Eric Van Oort, Ronald Lee Rock, Sr.
  • Patent number: 7320952
    Abstract: Composition and method for shortening the shear recovery time of cationic, zwitterionic, and amphoteric viscoelastic surfactant fluid systems by adding an effective amount of a co-gelling agent selected from triblock oligomeric compounds having hydrophilic (for example polyether) and hydrophobic (for example alkyl) portions. The co-gelling agent also increases fluid viscosity and very low co-gelling agent concentration is needed. Preferred surfactants are betaines and quaternary amines. The fluids are useful in oilfield treatments, for example fracturing and gravel packing.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: January 22, 2008
    Assignee: Schlumberger Technology Corporation
    Inventors: Yiyan Chen, Jesse C. Lee
  • Patent number: 7320953
    Abstract: A cleansing article is provided which includes a fibrous web of continuous network bonded fibers and a solid or semi-solid foamable composition joinably penetrating the web. The web has a first and second major surface each being on opposite faces of the web. The composition and web are present in a relative weight ratio ranging from about 30:1 to about 2000:1. At least a major portion of the first major surface of the web preferably being exposed above the foamable composition, and a majority of surfaces defining an exterior of the article are formed of the foamable composition.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: January 22, 2008
    Assignee: Unilever Home & Personal Care USA, division of Conopco, Inc.
    Inventors: Gregory Aaron Grissett, Diane Marie Keenan, Filomena Augusta Macedo, David Robert Williams
  • Patent number: 7320954
    Abstract: A pentafluorobutane composition includes, with respect to 100 parts by weight of 1,1,1,3,3-pentafluorobutane: 0.1 to 5.0 parts by weight of at least one of nitromethane and nitroethane; and 0.1 to 5.0 parts by weight of at least one of 1,3-dioxolane, trimethoxymethane, trimethoxyethane, and 1,2-butylene oxide.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: January 22, 2008
    Assignee: Kaneko Chemical Co., Ltd.
    Inventor: Akiyasu Kaneko
  • Patent number: 7320955
    Abstract: The present invention relates to compositions comprising (A) a complex of cyclodextrin and at least one laundry treatment active wherein the complex is prepared by the steps of: (a) combining cyclodextrin and at least one laundry treatment active wherein the cyclodextrin and the laundry treatment active is dissolved, dispersed, suspended, or emulsified in at least one solvent; and (b) removing at least partially the solvent; (B) further comprising at least one laundry adjunct material selected from the group consisting of surfactants; stabilizers; builders; perfumes; enzymes; chelating agents; suds suppressors; colors; opacifiers; anti-oxidants; bactericides; neutralizing agents; buffering agents; phase regulants, dye-transfer inhibitors, hydrotropes, thickeners and mixtures thereof. The present invention is further directed to the process of preparing such compositions and to methods of treating substrates with such compositions.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: January 22, 2008
    Assignee: The Procter & Gamble Company
    Inventors: Adam Thomas Yates, Alan Thomas Brooker, Sylvestre Canceil, Jean-Luc Bettiol, Andrew Russell Graydon, Paul Lapham
  • Patent number: 7320956
    Abstract: A cleaning and treating compositions for fibrous substrates, such as carpets is described. The compositions may be used to remove stains and impart anti-soiling and optionally stain release properties to the substrates.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: January 22, 2008
    Assignee: 3M Innovative Properties Company
    Inventors: Mitchell T. Johnson, Vinu Patel
  • Patent number: 7320957
    Abstract: Rinse-aid composition comprising a polyalkoxylated trisiloxane surfactant and a non-ionic solubilising system having a cloud point above room temperature and an acidifying agent wherein the rinse-aid composition has a pH of from about 1 to about 4.5.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: January 22, 2008
    Assignee: The Procter & Gamble Company
    Inventors: Anju Deepali Massey Brooker, Harold Emmerson, Andrew Paul Nelson, Eric San Jose Robles, Brian Xiaoqing Song
  • Patent number: 7320958
    Abstract: Disclosed are novel insecticidal polypeptides, and compositions comprising these polypeptides, peptide fragments thereof, and antibodies specific therefor. Also disclosed are vectors, transformed host cells, and transgenic plants that contain nucleic acid segments that encode the disclosed ?-endotoxin polypeptides. Also disclosed are methods of identifying related polypeptides and polynucleotides, methods of making and using transgenic cells comprising these polynucleotide sequences, as well as methods for controlling an insect population, such as Colorado potato beetle, southern corn rootworm and western corn rootworm, and for conferring to a plant resistance to a target insect species.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: January 22, 2008
    Assignee: Monsanto Technology LLC
    Inventors: Mark J. Rupar, William P. Donovan, Chih-Rei Chu, Elizabeth Pease, Yuping Tan, Annette C. Slaney, Thomas M. Malvar, James A. Baum
  • Patent number: 7320959
    Abstract: The present invention provides a method for treating structural heart disease in a subject, comprising administering an effective amount of an inhibitor of CaMKII to the subject, whereby the administration of the inhibitor treats the structural heart disease in the subject. Also provided are transgenic animal models for treating structural heart disease. Further provided is a means of screening for a compound that can treat structural heart disease.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 22, 2008
    Assignee: Vanderbilt University
    Inventor: Mark Anderson
  • Patent number: 7320960
    Abstract: Disclosed are compounds which bind VLA-4. Certain of these compounds also inhibit leukocyte adhesion and, in particular, leukocyte adhesion mediated by VLA-4. Such compounds are useful in the treatment of inflammatory diseases in a mammalian patient, e.g., human, such as asthma, Alzheimer's disease, atherosclerosis, AIDS dementia, diabetes, inflammatory bowel disease, rheumatoid arthritis, tissue transplantation, tumor metastasis and myocardial ischemia. The compounds can also be administered for the treatment of inflammatory brain diseases such as multiple sclerosis.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: January 22, 2008
    Assignees: Elan Pharmaceuticals, Inc., Wyeth
    Inventors: Eugene D. Thorsett, Christopher M. Semko, Dimitrios Sarantakis, Michael A. Pleiss, Anthony Kreft, Andrei W. Konradi, Francine S. Grant, Darren B. Dressen, Susan Ashwell, Reinhardt Bernhard Baudy, Louis John Lombardo
  • Patent number: 7320961
    Abstract: The present invention is directed to a method for inducing UGT1A1 isoform expression for treatment of a disease, disorder or adverse effect caused by an elevated serum concentration of an UGT1A1 substrate comprising the step of administering to a subject an effective amount of ritonavir. In particular, the present invention is directed to a method of treating unconjugated hyperbilirubinemia by UGT1A1 induction comprising the step of administering to a subject an effective amount of ritonavir.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: January 22, 2008
    Assignee: Abbott Laboratories
    Inventors: Dale J. Kempf, Richard J. Bertz, Jeffrey F. Waring
  • Patent number: 7320962
    Abstract: Dried hemoactive materials comprise both a cross-linked biologically compatible polymer and a non-cross-linked biologically compatible polymer. The cross-linked polymer is selected to form a hydrogel when exposed to blood. The non-cross-linked polymer is chosen to solubilize relatively rapidly when exposed to blood. The non-cross-linked polymer serves as a binder for holding the materials in desired geometries, such as sheets, pellets, plugs, or the like. Usually, the cross-linked polymer will be present in a particulate or fragmented form. The materials are particularly suitable for hemostasis and drug delivery.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: January 22, 2008
    Assignees: Baxter International Inc., Baxter Healthcare S.A.
    Inventors: Cary J. Reich, A. Edward Osawa, Helen Tran
  • Patent number: 7320963
    Abstract: Methods and compositions for delivering pharmaceutical agents into cells, in particular urothelial cells of the bladder, are provided. In the methods and compositions of the invention, a solubilized cholesterol composition is used to facilitate delivery of pharmaceutical agents. Preferably, the cholesterol is solubilized by a cyclodextrin (e.g., methyl-?-cyclodextrin) and the pharmaceutical agent comprises a polynucleotide and either a cationic lipid, a cationic polymer or a dendrimer. Improved methods for transfecting polynucleotides into cells thus are also provided, using cationic lipids, cationic polymers or dendrimers and solubilized cholesterol, wherein the transfection efficiency is enhanced compared to use of cationic lipids, cationic polymers or dendrimers alone.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: January 22, 2008
    Assignee: Genecure Pte Ltd
    Inventors: Kesavan Esuvaranathan, Ratha Mahendran, Carmel Lawrencia
  • Patent number: 7320964
    Abstract: The invention relates to decoy oligonucleotides and antisense oligonucleotides comprising a nucleic acid sequence according to SEQ ID NO: 1 to 43, in addition to the use of said nucleotides as medicaments.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: January 22, 2008
    Assignee: Avontec GmbH
    Inventors: Markus Hecker, Andreas H. Wagner
  • Patent number: 7320965
    Abstract: The invention relates to a double-stranded ribonucleic acid (dsRNA) for inhibiting the expression of the Huntingtin gene (HD gene), comprising an antisense strand having a nucleotide sequence which is less than 25 nucleotides in length and which is substantially complementary to at least a part of the HD gene. The invention also relates to a pharmaceutical composition comprising the dsRNA together with a pharmaceutically acceptable carrier; methods for treating diseases caused by the expression of the HD gene, or a mutant form thereof, using the pharmaceutical composition; and methods for inhibiting the expression of the huntingtin gene in a cell.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 22, 2008
    Assignee: Alnylam Pharmaceuticals, Inc.
    Inventors: Dinah Wen-Yee Sah, Philipp Hadwiger, Ingo Roehl, Birgit Bramlage, Pamela Tan, Hans-Peter Vornlocher, David Bumcrot
  • Patent number: 7320966
    Abstract: Synergistic and residual pesticidal compositions containing synergistic and residual mixtures of plant essential oils and/or their constituents, plant essential oils and/or their constituents in admixture with known active pesticidal compounds or plant essential oils and/or their constituents in admixture with other compounds not previously used as active ingredients in pesticidal formulations, such as, for example, so called signal transduction modulators. In addition, the present invention is directed to a method for controlling pests by applying a pesticidally effective amount of the above synergistic and residual pesticidal compositions to a locus where pest control is desired.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: January 22, 2008
    Assignee: Ecosmart Technologies, Inc.
    Inventors: Steven M. Bessette, Myron A. Beigler
  • Patent number: 7320967
    Abstract: The invention relates to a cosmetic composition containing at least one 15-hydroxy-prostaglandin dehydrogenase inhibitor and cosmetically acceptable excipients. It also relates to a method of cosmetic treatment for promoting the growth and/or preventing or delaying the loss of hair, and the use of a 15-hydroxyprostaglandin dehydrogenase inhibitor for the preparation of a composition intended for controlling hair loss and/or for promoting hair regrowth.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: January 22, 2008
    Assignee: L'Oreal
    Inventors: Jean-François Michelet, Bruno Bernard, Roger Rozot, Christophe Boulle
  • Patent number: 7320968
    Abstract: A pharmaceutical composition comprising: (A) an androgen; (B) a cyclic enhancer of the type used in the compositions and methods claimed by U.S. Pat. No. 5,023,252 to Hsieh; and (C) a thickening agent; including, for example, a composition in which the cyclic enhancer is a macrocyclic ester or a macrocyclic ketone; the use of the composition to treat a condition, for example, male hypogonadism, in a patient by applying the composition to the membrane of the patient; and a method for making the composition.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: January 22, 2008
    Assignee: Bentley Pharmaceuticals, Inc.
    Inventor: Robert J. Gyurik
  • Patent number: 7320969
    Abstract: This invention relates to a method of preventing pregnancy and treating PMS including PMDD. More particularly, the invention relates to a method, which involves administering one of several combination oral contraceptive regimens in combination with an antidepressant and a kit containing the same.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: January 22, 2008
    Assignee: Duramed Pharmaceuticals, Inc.
    Inventors: Robert G. Bell, Carole Ben-Maimon, Beata Iskold
  • Patent number: 7320970
    Abstract: A hormone replacement therapy, comprising a plurality of daily doses of a pharmaceutical preparation, the doses being administered continuously and consecutively in alternating phases of three daily doses, a relatively dominant estrogenic activity phase comprising three daily doses of a substance exhibiting estrogenic activity equivalent to about 1 mg per day of 17?-estradiol per day, and a relatively dominant progestagenic activity phase of a combination of a substance exhibiting estrogenic activity equivalent to about 1 mg per day of 17?-estradiol and a substance exhibiting progestogenic activity equivalent to about 90 ?g per day of norgestimate.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: January 22, 2008
    Assignees: Duramed Pharmaceutials, Inc., Jencap Research Ltd.
    Inventors: Robert F. Casper, Gary A. Shangold, Militza K. Ausmanas
  • Patent number: 7320971
    Abstract: 2? oxo-voruscharin compound and derivatives thereof are disclosed as well as pharmaceutical compositions which include 2? oxo-voruscharin compound or derivatives thereof. The disclosed 2? oxo-voruscharin compound and its derivatives are useful for cancer treatment. Methods of treating cancer using the disclosed compounds are also disclosed.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: January 22, 2008
    Assignee: Unibioscreen S.A.
    Inventors: Eric Van Quaquebeke, Jean-Claude Braekman, Gentiane Simon, Pierre Guissou, Odile Germaine Nacoulma, Janique Dewelle, Francis Darro, Robert Kiss
  • Patent number: 7320972
    Abstract: 4-Biarylyl-1-phenylazetidin-2-ones useful for the treatment of hypercholesterolemia are disclosed. The compounds are of the general formula in which represents an aryl or heteroaryl residue; Ar represents an aryl residue; U is a two to six atom chain; and the R's represent substituents.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: January 22, 2008
    Assignee: Microbia, Inc.
    Inventors: Eduardo Martinez, John J. Talley, Stephen Antonelli, Timothy C. Barden, Regina Lundrigan-Soucy, Wayne C. Schairer, Jing-Jing Yang, Daniel P. Zimmer, Brian Cali, Mark G. Currie, Peter S. Yorgey