Abstract: A radiation detector operating at high temperatures is shown comprising a LuAP scintillating material for producing light when excited by incident radiation, a photocathode, and an electron multiplier. The photocathode is deposited directly onto the surface of the scintillating material that is oriented toward the electron multiplier. In a preferred embodiment, a metal flange is hermetically sealed to the scintillating material and this is fusion welded to the electron multiplier to create a vacuum envelope. This invention is particularly useful in high temperature noisy environments such as downhole operations to detect radiation within a well hole.

Abstract: The invention is directed to a corrector for correcting energy-dependent first-order aberrations of the first degree as well as third-order spherical aberrations of electron-optical lens systems. The corrector includes at least one quadrupole septuplet (S1) having seven quadrupoles (Q1 to Q7). The quadrupoles are mounted symmetrically to a center plane (ZS) so as to permit excitation along a linear axis. The corrector furthermore includes at least five octopoles (O1 to O7) which can be excited within the quadrupole septuplet. In an advantageous embodiment, two quadrupole septuplets are mounted in series one behind the other. The quadrupole fields of the two quadrupole septuplets are excited antisymmetrically to a center plane lying between the two quadrupole septuplets.

Abstract: A voltage-isolating passageway for providing high voltage isolation between a component maintained at high DC voltage and a component maintained at a substantially lower voltage is described. The voltage-isolating passageway incorporates a transverse magnetic field across its passageway, which reduces the potential energy of charged particles (e.g., electrons) passing through the passageway. The reduction in electron potential energy reduces the energy of collisions between electrons and molecules and therefore reducing the likelihood of avalanche ionization. The voltage-isolating passageway includes a passageway and at least two magnets. The passageway has two openings and the two magnets are positioned along opposite and exterior surfaces of the passageway wherein the first and second magnets impose a magnetic field in a transverse direction with respect to a lengthwise axis of the passageway.

Abstract: There is provided a projection exposure system operable in a scanning mode along a scanning direction. The projection exposure system includes a collector that receives light having a wavelength ?193 nm and illuminates a region in a plane. The plane is defined by a local coordinate system having a y-direction parallel to the scanning direction and an x-direction perpendicular to the scanning direction. The collector includes (a) a first mirror shell, (b) a second mirror shell within the first mirror shell, and (c) a fastening device for fastening the first and second mirror shells. The mirror shells are substantially rotational symmetric about a common rotational axis. The fastening device has a support spoke that extends in a radial direction of the mirror shells, and the support spoke, when projected into the plane, yields a projection that is non-parallel to the y-direction.

Abstract: The invention provides an optical reflector element (1) for a beam of X-rays (RX) or of gamma-rays or of high-energy particles at grazing incidence, the element being constituted by a stack of superposed silicon plates (10-12). Each plate (10-12) has a reflecting top face (101-121) possibly coated with a metallic film, a multilayer or a dispersive grating and a bottom face carrying ribs (100-120) forming spacers between two successive plates (10-11, 11-12), and defining determined spacing between two successive reflecting faces (101-121). The invention also provides optical instruments comprising several such elements, in particular a type I Wolter telescope comprising two mirrors in tandem having respective paraboloid and hyperboloid surfaces of revolution or a conical approximation thereof or a Kirkpatrick-Beaz system.

Abstract: The invention relates to a container (1) for radioactive materials comprising a main hollow body (2) as well as a cover (6) made of at least one first metallic material, the cover being capable of being fixed on the main hollow body by means of sealing means (26) made of a second metallic material poured into a groove (24) defined by the cover and the main hollow body of the container. According to the invention, the cover (6) and the main hollow body (2) are made solid with the sealing means (26) by means of a bonding zone (28), formed by chemical reaction between the first and second metallic materials. The invention likewise concerns a process for closing of such a container (1).

Abstract: A deposition system and film thickness monitoring device thereof. The film thickness monitoring device for monitoring thickness of a thin film coated on an optical substrate includes a laser light source, a retro-reflector, and a light receiver. The laser light source and the retro-reflector are disposed on opposite sides of the optical substrate. First, a light beam is emitted by the laser light source and then passes through the thin film along a first path. Second, the light beam is reflected by the retro-reflector and then passes through the thin film again along a second path parallel to the first path. Third, the light beam is received by the light receiver.

Abstract: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.

Abstract: Experiments suggest that the mathematically weakest non-abelian TQFT may be physically the most robust. Such TQFT's—the ?=5/2 FQHE state in particular—have discrete braid group representations, so one cannot build a universal quantum computer from these alone. Time tilted interferometry provides an extension of the computational power (to universal) within the context of topological protection. A known set of universal gates has been realized by topologically protected methods using “time-tilted interferometry” as an adjunct to the more familiar method of braiding quasi-particles. The method is “time-tilted interferometry by quasi-particles.” The system is its use to construct the gates {g1, g2, g3}.

Abstract: A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Abstract: Regio-regular polythiophenes used in diodes which are not light emitting or photovoltaic. High quality, processable thin film polymer films can be made. The thin film can have a thickness of about 50 nm to about one micron, and the conductive thin film can be applied by spin casting, drop casting, screening, ink-jetting, transfer or roll coating. The polythiophenes can be homopolymers or copolymers. The regio-regular poly(3-substitutedthiophene) can be derivatized so that the 3-substituent is an alkyl, aryl, or alkyl/aryl moiety with a heteroatom substitution in either the ?- or beta-position of the 3-substituent.

Abstract: An organic electroluminescent display device according to an embodiment includes a connection electrode on a first substrate; and a luminescent element on a second substrate opposite to the first substrate, the luminescent element being connected to the connection electrode, the luminescent element having a contact part at least partially surrounded by a separator, wherein a first electrode, a second electrode and an organic common layer between the first electrode and the second electrode are located in the contact part.

Abstract: The claimed invention is directed to a flat panel display having R, G, and B unit pixels. At least one of the R, G, and B unit pixels includes at least two or more transistors, each having source and drain regions. At least one drain region in the source/drain regions of at least one transistor in the transistors has a resistance value different from a resistance value of at least a drain region of the other transistor. The difference in resistance values may be accomplished by doping each drain region with a different concentration of dopant or by shaping each drain region differently.

Abstract: An RGB light emitting diode package with improved color mixing properties includes red, green, and blue light emitting diode chips provided on a reflector. A photomixing material and a filler resin scatters rays so as to uniformly mix the rays emitted from the light emitting diode chips. The photomixing material and filler resin are applied onto upper sides of the light emitting diode chips while being mixed with each other, and the photomixing material is uniformly dispersed in the filler resin.

Abstract: The invention concerns an asymmetric diac comprising a highly-doped substrate (21) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity on the upper surface of the substrate (21), a highly-doped region (24) of the first type of conductivity on the side of the upper surface of the epitaxial layer, a region (23) of the second type of conductivity more doped than the epitaxial layer beneath the region (24) of the first type of conductivity and not overlapping relative thereto, a channel retaining ring (25) of the second type of conductivity more doped than the epitaxial layer, outside the first region, and a wall (26) of the first type of conductivity outside said ring, joining the substrate.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed between the barrier layer and the bonding pad. For copper metallization, the adhesion layer may contain titanium or tantalum; for aluminum metallization, it may be aluminum. The nickel silicon alloy may be deposited by magnetron sputtering. Commercially available NiSi4.5% sputter targets have provided a superior under-bump metallization (UBM) with lead-free tin solder bumps. Dopants other than silicon/may be used to reduce the magnetic permeability and provide other advantages of the invention.

Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

Abstract: An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.

Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

Abstract: A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the nonvolatile memory cell, the band structure engineering is used to alter the band structure between a bulk part of the device and another part of the device supporting the measurement current.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A device including a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor is provided. The device also includes a cell transistor including diffused regions formed in a surface of a semiconductor substrate; a trench capacitor formed in said semiconductor substrate for configuring a DRAM cell together with said cell transistor; a buried strap formed in said semiconductor substrate to connect said diffused region to said trench capacitor; and a collar insulation film formed on sides of said buried strap.

Abstract: The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at a first temperature. The temperature is increased to a second temperature at least 40° C. higher than the first temperature while flowing at least one hydrogen isotope into the chamber. After the temperature reaches the second temperature, the layer is seeded with seed crystals. The seeded layer is then annealed to form a rugged silicon-containing surface. The rugged silicon-containing surface can be incorporated into a capacitor construction. The capacitor construction can be incorporated into a DRAM cell, and the DRAM cell can be utilized in an electronic system.

Abstract: A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

Abstract: A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage, the third and fourth active zones being mutually connected via an electrically conducting connection external to the substrate. The value of the binary data item is defined by an implantation of a chosen type in a predetermined part of the substrate region or in the third and fourth active zones.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

Abstract: A device for manufacturing a capacitive pressure measurement includes an insulated base electrode, a mechanically deflectable counterelectrode composed of a layer made of at least one of a monocrystalline and polycrystalline semiconductor material, a contact arrangement for electrically connecting the electrodes, and at least one semiconductor component, all integrated onto a semiconductor substrate. The connection for the base electrode is formed by an electrically insulated conductive polycrystalline semiconductor layer. The method for manufactured the device includes the step of arranging a conductive polycrystalline semiconductor layer between two insulating layers on the semiconductor substrate for forming a base electrode.

Abstract: A method of fabricating a CoSb3-based thermoelectric device is disclosed. The method includes providing a high-temperature electrode, providing a buffer layer on the high-temperature electrode, forming composite n-type and p-type layers, attaching the buffer layer to the composite n-type and p-type layers, providing a low-temperature electrode on the composite n-type and p-type layers and separating the composite n-type and p-type layers from each other to define n-type and p-type legs between the high-temperature electrode and the low-temperature electrode.

Abstract: In a method of manufacturing a variable capacitance diode according to the present invention, a mask is formed on a semiconductor substrate of a first conductive type having a low impurity concentration, a semiconductor region of the first conductive type having an intermediate impurity concentration is formed on the semiconductor substrate by means of ion implantation via an opening portion of the mask, a semiconductor region of a second conductive type having a high impurity concentration is formed in the semiconductor substrate on a surface side thereof relative to the semiconductor region of the first conductive type having the intermediate impurity concentration via the same opening portion of the mask, and the semiconductor region of the first conductive type having the intermediate impurity concentration and the semiconductor region of the second conductive type having the high impurity concentration are activated by applying a heat treatment to the semiconductor substrate.

Abstract: Methods for fabricating an assembly having functional blocks coupling to a substrate. The method includes providing the substrate with receptor sites wherein each of the receptor sites is designed to couple to one of the functional blocks. Electrodes are coupled to the substrate. The electrodes cover the receptor sites such that portions of the receptor sites are coated with the electrodes. Applying a voltage source to the electrodes using a first electrical circuit such that each electrode has a voltage different from another electrode. The electrodes form an electric field. The functional blocks having electronic devices and being in a slurry solution are dispensed over the substrate. Each functional block is fabricated out of materials having a high dielectric constant such that said functional blocks are attracted to the higher field strength regions and are guided to the receptor sites.

Abstract: A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame semiconductor device assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: An LED package includes a datum reference feature that is external to the insulating body of the LED package and has a known, fixed relationship to the heat sink. The LED die is mounted to the heat sink such that the LED die has a fixed relationship to the heat sink. Accordingly, the reference datum feature provides a frame of reference to the position of the LED die within the LED package. The reference datum feature may be mounted to the heat sink or integrally formed from the heat sink. A pick-and-place head holds the LED package by engaging the datum reference feature, e.g., with an alignment pin. In addition, the LED package may include a lead that extends laterally into the insulating body, and extends towards the LED die to reduce the vertical distance between the lead and the LED die.

Abstract: A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

Abstract: A semiconductor device includes a first circuit element chip including a first surface on which a plurality of first electrodes are arranged, and a second circuit element chip including a first surface on which a plurality of second electrodes are arranged. The second circuit element chip is mounted on the first circuit element chip. The semiconductor device further includes an insulating film disposed on a side surface of the second circuit element chip and disposed between the first surfaces of the first and second circuit element chips. The semiconductor device still further includes a resin layer covering the second circuit element chip and the insulating film. Also, there is provided a manufacturing method of the semiconductor device which includes forming the insulating film after the second circuit element chip is mounted on the first circuit element chip.

Abstract: A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the carriers, at least one dielectric layer formed on the active surface of the semiconductor chip and the surface of the carrier, at least a conductive structure formed in the opening of the dielectric layer, and at least a circuit layer formed on the surface of the dielectric layer wherein the circuit layer is electrically connected to the electrode pad by the conductive structure, so as to form a three-dimensional module to increase the storage capacity dramatically and integrate the semiconductor chips in the carriers for efficiently reducing the size of the module, so that the combinations can be changed flexibly to form the required storage capacity according to the demands.

Abstract: In a semiconductor device in which a plurality of substrates each mounting a semiconductor chip are stacked, one ends of the leads formed on the substrates are connected to the semiconductor chip and the other ends thereof are connected to connection terminals of the substrates. At least one of the leads are branched into two or more in the vicinity of the connection terminals, and one ends of the branched leads are connected to the connection terminals. A technique for sorting good products is performed in a state in which the chips are mounted on the substrates.

Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.

Abstract: In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Abstract: A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Abstract: A semiconductor device includes a protrusion group composed of a plurality of first protrusions arranged on a mounting surface with predetermined gaps; a plurality of second protrusions for burying spaces between the neighboring first protrusions; and conductive members provided on protruding surfaces of the plurality of first protrusions.

Abstract: A high frequency semiconductor device includes a semiconductor substrate, a high frequency semiconductor element on the semiconductor substrate, a high frequency signal transmission line connected at a first end to the high frequency semiconductor element, a high frequency signal input/output pad connected to a second end of the high frequency signal transmission line, the high frequency signal input/output pad extending perpendicular to the length direction of the high frequency signal transmission line, and ground potential pads on opposite longitudinal sides of the high frequency signal input/output pad.

Abstract: A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

Abstract: A streetlight for illuminating a portion of an adjacent roadway. The streetlight includes three vertical support members with a rotatable axle mounted intermediate thereto. Superposed on the vertical support members is a light assembly. A plurality of wind receptacles, having a hub, at least one support arm and at least one cup shaped wind-capturing device are operatively connected to the axle. The wind receptacles act to harness air current and rotate the axle, which is operatively connected to an electrical generator. The electrical current from the generator is stored in a power storage unit. The streetlight further includes photovoltaic cells for supplying power to the light assembly.