Abstract: A method of increasing methionine and/or methionine related metabolites in a plant is provided. The method is effected by expressing within the plant a cystathionine ?-synthase encoded by a polynucleotide mutated in, or lacking, a region encoding an N-terminal portion of said cystathionine ?-synthase, said region being functional in downregulating an activity of said cystathionine ?-synthase in the plant.

Abstract: The invention discloses maize bZIP transcriptional factors, namely, ABP2, ABP4 and ABP9, the genes encoding these factors, and the use thereof. The transcriptional factors are proteins having an amino acid sequence set forth in SEQ ID NO: 2, 4, or 6, or proteins derived therefrom by substitution, deletion or addition of one or more amino acid residues of SEQ ID NO: 2, 4, or 6, and having the same activity as a protein shown by SEQ ID NO: 2, 4, or 6. The ABP2, ABP4 and ABP9 genes encoding these factors, respectively, are the DNA sequences having an identity of more than 90% with a sequence shown by SEQ ID NO: 1, 3 or 5 and the encoded proteins having such same functions. These genes are important for breeding plant varieties with an enhanced tolerance to abiotic stresses and for improving plant tolerance to abiotic stresses.

Abstract: The production of a purified extracellular bacterial signal called autoinducer-2 is regulated by changes in environmental conditions associated with a shift from a free-living existence to a colonizing or pathogenic existence in a host organism. Autoinducer-2 stimulates LuxQ luminescence genes, and is believed also to stimulate a variety of pathogenesis related genes in the bacterial species that produce it. A new class of bacterial genes is involved in the biosynthesis of autoinducer-2.

Abstract: A stable isotopic identification comprising a mathematical array of concentrations of isotopes found in a product, said mathematical array being presented in a machine readable form and comparable to analytical results whereby the product can be distinguished from other similar products, said machine readable form also being indexed through stored product information. The stored product information may be displayed when desired. By the stable isotopic identification of the invention, a product may be securely traced through manufacturing of a product, marketing of a product and the use of a product.

Abstract: A method for determination for a given oil the relative stability of a water-in-oil emulsion that will be formed by that oil with water comprises measuring for the given oil the weight fraction of the oil that is most strongly adsorbed on a silica gel column successively eluted with n-hexane, toluene and methylene chloride-methanol mixture solvents and determining whether said weight fraction is greater than about 0.05; with a value above 0.05 being determinative of an emulsion more stable than one with a value less than 0.05.

Abstract: An analytical system is provided for determining nitrogen monoxide, nitrogen dioxide and ozone concentrations in air samples. An ultraviolet light source 4 is used to alter the equilibrium between nitrogen dioxide and oxygen on the one hand and nitrogen monoxide and ozone on the other. Dynamic measurement of ozone concentration with time while ultraviolet irradiation is pulsed enables each gas concentration to be calculated without requiring input gases to be scrubbed. An aApparatus 101 is further provided to provide a controlled flow of gas to a sensor 103 attached to a high altitude balloon while sheltering it from the elements and allowing for affects of temperature, said apparatus comprising a shield 104 and a gas conducting means which uses the venturi effect to control air flow or has a hole to allow water to drain without affecting air flow past the sensor.

Abstract: A method is provided for the quantitative analysis of the contents, in nitrogen, of hydrogen and methane by ionic mobility spectrometry. The method includes the steps of: a) performing a measurement of the apparent hydrogen concentration in the nitrogen to be analyzed; b) performing a measurement of the apparent hydrogen concentration in a flow of the same sample of nitrogen, purified of all impurities but methane; and c) comparing the two measurements. A system of branched lines is also provided for carrying out the method.

Abstract: The present invention relates to a microfluidic device comprising a microchannel (2, 4) providing for solvent contact between an open microarea (MA) carrying a microvolume (1) of a solvent and a reservoir (3) for the solvent, said reservoir (3) and said microchannel (2, 4) being adapted so that solvent evaporated from said microarea (MA) is continuously replaced by solvent from the reservoir (3) through said microchannel (2, 4). It further relates to method for replacing solvents evaporating from a microvolume (1) of solvent placed in an open microarea (MA) of a microfluidic device, wherein replacement is continuously taking place via a microchannel (2, 4) that transports solvent to the microarea (MA) from a solvent reservoir (vessel) (3). The device and method are suitable for preventing the desiccation of samples.

Abstract: The invention relates to methods and compositions for identifying pregnant subjects having, or predisposed to having, gestational diabetes, preeclampsia, and gestational hypertension. The methods are applicable to urine and/or blood samples and can be conducted prior to the third trimester of pregnancy, and as early as the first trimester.

Abstract: A biosensor surface with a low density of ligand-carrying tether molecules on a base layer. Also, surface plasmon resonance (SPR) devices have the biosensor surface attached to a thin gold layer with backside angle-spread incident radiation for resonance excitation and reflective detection.

Abstract: A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.

Abstract: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

Abstract: A method of making and using thin film calibration features is described. To fabricate a calibration standard according to the invention raised features are first formed from an electrically conductive material with a selected atomic number. A conformal thin film layer is deposited over the exposed sidewalls of the raised features. The sidewall material is selected to have a different atomic number and is preferably an nonconductive such as silicon dioxide or alumina. After the nonconductive material deposition, a controlled directional RIE process is used to remove the insulator layer deposited on the top and bottom surface of the lines and trenches. The remaining voids between the sidewalls of the raised features are filled with a conductive material. The wafer is then planarized with chemical mechanical planarization (CMP) to expose the nonconductive sidewall material on the surface. The nonconductive sidewall material will be fine lines embedded in conductive material.

Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

Abstract: A light waveguide element is made by forming only an upper clad layer (40) and a core layer (32) without etching an optical axis height-adjusting sections. By using plasma chemical vapor deposition (CVD) which is good at controlling the film thickness, it is possible to provide without difficulty a light waveguide element with a height-adjusting section that has a precise film thickness, making it possible to provide precise optical axis vertical alignment upon mounting. By forming alignment markers in the same photolithography as that of the core formation, it is possible to provide precise horizontal optical axis alignment.

Abstract: A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.

Abstract: The present invention provides a method of manufacturing MEMS devices, comprising the steps of forming MEMS device bodies in a first substrate, defining concave portions around the MEMS device bodies over the first substrate, forming convex portions coincident with the concave portions in a second substrate, fitting the convex portions in the concave portions, respectively, to join the first substrate and the second substrate to each other, thereby forming a third substrate, sticking the third substrate to a UV sheet on the second substrate side, and dicing the third substrate to separate the MEMS device bodies from one another.

Abstract: A method of forming a microelectronic device (300) including the steps of forming a sensor component (100) and a capping component (200). The sensor component (100) includes a sensor structure (150, 152) and a conductive trace (160, 162) formed on a first SOI semiconductor wafer (110). The capping component (200) includes a plurality of capping layers (230, 232) formed on a second SOI semiconductor wafer (210). During fabrication the capping component (200) is bonded to the sensor component (100) prior to fabrication of a through hole (260) in the capping component (200). Subsequent to bonding the two components together, wafer thinning removes a handle layer (112) of the first SOI semiconductor wafer (110) and a handle layer (212) of the second SOI semiconductor wafer (210).

Abstract: Disclosed is a method of producing an LnCuOX single-crystal thin film (wherein Ln is at least one selected from the group consisting of lanthanide elements and yttrium, and X is at least one selected from the group consisting of S, Se and Te), which comprises the steps of growing a base thin film on a single-crystal substrate, depositing an amorphous or polycrystalline LnCuOX thin film on the base thin film to form a laminated film, and then annealing the laminated film at a high temperature of 500° C. or more.

Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.

Abstract: A method of sizing a load plate for an Application Specific Integrated Circuit (ASIC) assembly includes compressing the load plate prior to installation in the ASIC assembly. The compression is adjusted to cause the load plate to provide a target load when installed in the ASIC assembly.

Abstract: A mounting method for a semiconductor component. The method includes application of solder material to the semiconductor component, application of at least one contact/mounting element made of semiconductor material and/or metal and/or insulator material to the solder material, heating of at least one part of the semiconductor component to a temperature lying above the melting point of the solder material by impressing an electrical power into the semiconductor component, as a result of which corresponding soldering connections arise between the semiconductor component and the at least one contact/mounting element, and cooling of the connection complex that comprises the semiconductor component and at least one contact/mounting element and was produced in the preceding step.

Abstract: High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.

Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Abstract: A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this first station has a first entrance (101a) and a first exit 101b). A second work station (102) is operable to perform a second manufacturing action on the product parts; this second station has a second entrance (102a) and a second exit (102b). A transport line (103) between the first exit and the second entrance is operable to move the product parts under computer control. A chamber (104) encloses a portion of the line and is constructed so that the transport achieves a balanced throughput from the first station to the second station, while the product parts are exposed to computer-controlled environmental conditions (110) during transport through the chamber. The balanced throughput in the chamber is achieved by waiting lines for the product with computer-controlled monitors (105a) for product parts' positions and times in the chamber.

Abstract: A integrated circuit housing includes a first clamping hardware, a second clamping hardware operatively connected to the first clamping hardware, and an integrated circuit stack comprising a top portion and a bottom portion, wherein the first clamping hardware contacts the top portion and the second clamping hardware contacts the bottom portion, and wherein a first shim is interposed between the bottom portion and the second clamping hardware.

Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof, in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; punching through from a surface side having the terminals in the wiring substrate, thereby cutting the terminals along a boundary between the first region and the second region; and punching through from the surface side having the reinforcing member in the wiring substrate, thereby continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: It is an object of the present invention to apply a technique for removing the adverse effect of a substrate shrinkage due to a heat treatment, and further forming a fine and high-quality insulating film, and a semiconductor device that can realize high-performance and high-reliability by using the same, to a transistor formed by laminating a semiconductor film or an insulating film over a glass substrate. A heat treatment that is necessary in a step of forming a thin film element by laminating a semiconductor film or an insulating film over a glass substrate is performed without thermally-damaging the substrate. For the purpose, a light-absorbing layer that can absorb pulsed light over a particular portion of the substrate in which the thin film element is formed is locally formed, and the heat treatment is performed.

Abstract: Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers. The etching protective layers cover the exposed scan lines exposed by the patterned dielectric layer and the patterned semiconductor layer, and are electrically connected to the scan lines. A passivation layer is formed, and then the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes are removed to expose the patterned transparent conductive layer. The patterned semiconductor layer over the scan lines between the etching protective layers and the data lines is removed to expose the patterned dielectric layer over the scan lines.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: Shorting bars are provided for electrostatic discharge protection as a portion of trace deposition in a photodiode array. During normal processing for etching of the metal layers, the shorting bars are removed without additional processing requirements. Additional shorting elements are provided by employing FET silicon layers having traces in contact with the array traces to provide extended ESD protection until removal of those shorting elements during normal processing for opening vias for photodiode bottom contact.

Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

Abstract: Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

Abstract: A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.

Abstract: In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Abstract: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.

Abstract: An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

Abstract: A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.

Abstract: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Abstract: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation film; forming a first insulation film covering the gate electrode and at least a part of the semiconductor substrate; charging the first insulation film; and forming a second insulation film for charge storage on the first insulation film.

Abstract: A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barrier oxide films on lateral faces of the trenches by an atomic layer deposition method, and forming bit lines within the trenches.

Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 ? gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

Abstract: A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques.