Abstract: A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.

Abstract: The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

Abstract: A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.

Abstract: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region; forming a groove portion in the element separation structure forming region; forming a groove portion oxide film in the groove portion; forming a pre-filling oxide film for filling the groove portion; removing the pre-filling oxide film; forming a resist layer on the silicon nitride film and the pre-filling oxide film; forming a resist mask on the element separation structure forming region; removing the silicon nitride film and the first thermal oxide film; forming a second thermal oxide film on the substrate; and removing the second thermal oxide film and leveling the pre-filling oxide film to form a filling portion.

Abstract: The present invention concerns methodologies for the mass production of solid state components, in particular capacitors, although other component types including, but not limited to, diodes and resistors may be produced. According to one aspect of the method of manufacturing first and second substrates are provided with a plurality of first and second solid state electronic component elements formed on a surface of each substrate. The first and second substrates are aligned so that respective first and second component elements are each mutually aligned, and the first and second substrates are fixed together, so that the first and second elements are operatively connected one to another, thereby forming a substrate sandwich. The substrate sandwich may be divided to form a plurality of individual components, each comprising a first component element cooperatively connected to a second component element.

Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.

Abstract: A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

Abstract: A method of manufacturing a crystalline wafer that includes implanting first atomic species in a donor substrate to form a region of weakness at a first depth therein and configured to facilitate detachment of a first layer of the donor substrate from a remaining portion of the donor substrate. The first layer and remaining portion are disposed on opposite sides of the region of weakness. The method also includes implanting second atomic species in the donor substrate to form a gettering region at a second depth therein that is different than the first depth to reduce or minimize migration of the implanted first atomic species past the gettering region. This reduces or minimizes an increase in roughness of a surface produced on the first layer after detachment thereof from the remaining portion at the region of weakness.

Abstract: One embodiment of the present invention is a method for cleaning an electron beam treatment apparatus that includes: (a) generating an electron beam that energizes a cleaning gas in a chamber of the electron beam treatment apparatus; (b) monitoring an electron beam current; (c) adjusting a pressure of the cleaning gas to maintain the electron beam current at a substantially constant value; and (d) stopping when a predetermined condition has been reached.

Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

Abstract: A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern, and depositing a carbon-containing hard mask layer on the substrate by (a) introducing a carbon-containing process gas into the chamber, (b) generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone overlying the workpiece by coupling plasma RF source power to an external portion of the reentrant path, and (c) coupling RF plasma bias power or bias voltage to the workpiece. The method further includes photolithographically defining the predetermined pattern in the carbon-containing hard mask layer, and etching the target layer in the presence of the hard mask layer.

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: A field effect transistor (FET) and related manufacturing method are disclosed, wherein an active region of a semi-conductor substrate is embossed by a first trench structure. A second trench structure and filling shallow trench insulator laterally defines the active region. Sidewalls of the trenches forming the first trench structure descend to a bottom face with a positive sloped, such that the intersection of the respective sidewalls with the bottom face form an obtuse angle.

Abstract: A method of forming a package is disclosed, which includes steps of forming a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal traces are formed. The solder mask covers at least a portion of the surface of the substrate. And the first aperture through the solder mask exposes a plurality of the metal traces.

Abstract: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.

Abstract: Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0<x<y<1, and R is selected from C4-C24 alkyl, C4-C24 alkenyl, C4-C24 alkoxy, C8-C24 alkenoxy, substituted C4-C24 hydrocarbon, non-substituted C1-C4 hydrocarbon or substituted C1-C4 hydrocarbon; and, partially etching the filler filling the via and an interlayer dielectric to form a trench, which is connected to the via in the region where the dual damascene interconnections are to be formed. Then, the filler remaining in the via is removed, and the trench and the via are filled with an interconnection material to complete the dual damascene interconnections.

Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

Abstract: In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.

Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.

Abstract: An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring initial concentration of a specific ion in a phosphoric acid solution contained in a reactor, b) dipping a silicon nitride-formed substrate into the phosphoric acid solution in the reactor, c) measuring instantaneous concentration of the specific ion in stripping solution extracted from the reactor when silicon nitride stripping is processed in the reactor, and d) finishing the silicon nitride stripping process if variation rate of the measured instantaneous concentration is not exceeding a predetermined standard, or returning to the step c) if the variation rate is more than the predetermined standard.

Abstract: According to one aspect of the invention, an improved process for preparing a surface of substrate is provided wherein the surface of the substrate is prepared for a chemical mechanical polishing (CMP) process, the CMP process is performed on the surface of the substrate, and the surface of the substrate is finished to clear the substrate surface of any active ingredients from the CMP process. Also, an improved substrate produced by the method is provided. According to one aspect of the invention, particular polishing materials and procedures may be used that allow for increased quality of AlN substrate surfaces.

Abstract: An objective of the present invention is to provide a polishing pad for a semiconductor wafer and a laminated body for polishing of a semiconductor wafer equipped with the same which can perform optical endpoints detection without lowering the polishing performance as well as methods for polishing of a semiconductor wafer using them. The polishing pad of the present invention comprises a substrate 11 for a polishing pad provided with a through hole penetrating from surface to back, a light transmitting part 12 fitted in the through hole, the light transmitting part comprises a water-insoluble matrix material (1,2-polybutadiene) and a water-soluble particle (?-cyclodextrin) dispersed in the water-insoluble matrix material, and the water-soluble particle is less than 5% by volume based on 100% by volume of the total amount of the water-insoluble matrix material and the water-soluble particle.

Abstract: Polishing compositions and methods for removing conductive materials from a substrate surface are provided. In one aspect, a method is provided for processing a substrate to remove conductive material disposed over narrow feature definitions formed in a substrate at a higher removal rate than conductive material disposed over wide feature definitions formed in a substrate by an electrochemical mechanical polishing technique, and then polishing the substrate by at least a chemical mechanical polishing technique.

Abstract: The present invention provides a method of forming recesses on a substrate, the method including forming on the substrate a patterning layer having first features; trim etching the first features to define trimmed features having a shape; and transferring an inverse of the shape into the substrate.

Abstract: The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

Abstract: A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

Abstract: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract: The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cerium oxide and titanium oxide. The dielectric materials can be incorporated into any suitable semiconductor devices, including, for example, capacitor devices, transistor devices, and flash memory devices. The invention also includes methods of utilizing atomic layer deposition to form laminates of cerium oxide and titanium oxide.

Abstract: A method for producing a non-chemically crosslinked hyaluronan is provided which involves contacting a sample of hyaluronan with an acidic solvent/water mixture for a period of time and at a temperature sufficient to effect crosslinking, wherein the acidic solvent/water mixture has a content of a solvent sufficient to prevent dissolution of said hyaluronan and wherein the solvent is miscible with water, and an amount of an acid sufficient to effect crosslinking of the hyaluronan, and the crosslinked, water resistant non-woven hyaluronan resulting therefrom.

Abstract: A family of glasses from the SiO2—Al2O3—P2O5 ternary system exhibiting high strain point, transparency, and low coefficient of thermal expansion. The glasses have the following composition, expressed in mol percent and calculated from the glass batch on an oxide basis: 55-80 SiO2, 12-30 Al2O3, and 2-15 P2O5.

Abstract: A short optical glass is disclosed which is particularly suited for the applications imaging, projection, telecommunication, optical information technology and/or laser technology, also particularly suited for fiber applications (light guides or imaging guides). Preferably, the glass has a refractive index of 1.54?nd?1.62 and an Abbe coefficient of 48?vd=57. It further has good attenuating and ion exchange characteristics, good chemical stability and good crystallization stability. The glass comprises 35 to 50 wt.-% SiO2, 0.1 to 6 wt.-% B2O3, 0.1 to 7 wt.-% Al2O3, 0.1 to 4 wt.-% P2O5, 4 to 24 wt.-% R2O (alkali oxides), 6 to 14.5 wt.-% BaO, 0 to 12 wt.-% other RO (alkaline earth oxides), 14 to 25 wt.-% ZnO, 0 to 5 wt.-% La2O3, 0 to 10 wt.-% ZrO2, wherein R2O is an alkali oxide, RO is an alkaline earth oxide other than BaO, wherein Li2O is 6 wt.

Abstract: A highly reliable ceramic electronic device having an excellent temperature characteristic of a capacitance and a low IR temperature dependency, comprising a dielectric layer: wherein the dielectric layer includes a main component expressed by a composition formula of BamTiO2+m, wherein “m” satisfies 0.995?m?1.010 and a ratio of Ba and Ti satisfies 0.995?Ba/Ti?1.010, and, as subcomponents, an oxide of Al and an oxide of Si or an oxide of R (note that R is at least one kind selected from Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu); and includes a secondary phase composed of at least a part of the oxide of Al and at least a part of the oxide of Si or the oxide of R and being different from a main phase mainly composed of the main component; and the production method are provided.

Abstract: A method for pacifying the spent bed material resulting from the synthesis of organohalosilanes and halosilanes by mixing clay with spent bed material. Clay compositions containing at least 10 weight % of clay and spent bed material, as well as ceramic compositions containing spent bed material, are also provided.

Abstract: We disclose a method for preparing a catalyst for converting toluene to xylenes.

Abstract: The present application discloses a catalyst for olefin polymerization, comprising a product of the following components: (A) solid titanium-containing catalyst component comprising magnesium, titanium and halogen as essential components; (B) organo-aluminum compound catalyst component, and (C) silicon ether compound catalyst component, the silicon ether compound being represented by a general formula (I): wherein R1-R12 and A are as defined in the description.

Abstract: A catalyst assembly comprising a substrate, nanofilaments which have a nanometer-size diameter and are formed on the substrate, and particles which have a nanometer-size diameter, at least one of the nanofilaments and the particles having a catalytic function, is provided to use a catalyst more efficiently and to provide a catalytic function more efficiently. Interstices between the nanofilaments serve as distribution channels of a reactive gas, and the reactive gas spreads sufficiently not only around the ends of nanofilaments but also inside a catalyst assembly. A combination of nanofilaments and particles enables dispersion of a catalyst at a distance of not more than about 100 nanometers.

Abstract: The invention relates to R-(?)-1-[2-(7-Chloro-benzo[b]thiophen-3-yl-methoxy)-2-(2,4-dichloro-phenyl)-ethyl]-1H-imidazole and the salts thereof. The invention also relates to compositions thereof and their use either for treating fungal infections in humans and animals or combating crop diseases. A process for their preparation is also described.

Abstract: An electropositive and water-based production well treating fluid system exhibits electropositivity by using a cationic viscosifier meanwhile matched with a cationic fluid loss additive and, optionally, contains a mud-building agent, an electrical stabilizing agent, a colloid-stabilizing agent, lubricant, an oil layer protective agent and/or a weighting agent. The electropositive production well treating fluid can beffer solve the contradiction of technical requirements between “treating fluid stability” and “bore hole stability”, and features a strong ability to inhibit the dispersion of clay, a good effect of protecting oil-gas reservoirs, fast drilling speeds, regular shape of bore holes and good resistance to salt.

Abstract: Fluorinated oligourethanes, having number average molecular weight lower than or equal to 9,000, having a branched structure, formed of the following monomers and macromers: a) aliphatic, cycloaliphatic or aromatic polyisocyanates, b) heterofunctional hydrogenated monomers having general formula: X0—(CR1AR2A)b—Y0 ??(Ib) one or more of the following compounds: c) bifunctional hydroxyl (per)fluoropolyethers (PFPE diols) having number average molecular weight in the range 400-3,000, e) monofunctional hydroxyl (per)fluoropolyethers or monofunctional hydroxyl (per)fluoroalkanes (e?), having number average molecular weight in the range 300-1,000, and optionally the following compounds: d) heterofunctional monomers, dI) hydrogen-active compounds, capable to form bonds with the NCO functions stable at the hydrolysis but weak at heat.

Abstract: An adduct that has an acidic solution of sparingly-soluble Group IIA complexes (“AGIIS”) and at least one additive. The AGIIS can be prepared by mixing a mineral acid (such as sulfuric acid), and a Group IIA hydroxide (such as calcium hydroxide) or a Group IIA salt of a dibasic acid (such as calcium sulfate), or a mixture of the two Group IIA compounds, followed by removing the solid formed. The additives can be an alcohol, an organic acid or a surface active agent. The composition has various uses, including cleaning, food production, decontamination, bioremediation, agricultural application, medical application, and detoxification of substances.

Abstract: The invention provides a process for producing a bleaching activator composition, which includes removing a solvent and/or water from a mixture of a bleaching activator and a surfactant dispersed in a non-aqueous solvent, a bleaching activator composition produced by the process and a bleaching activator granule obtained by further granulating the bleaching activator composition.