Patents Issued in January 29, 2008
  • Patent number: 7323689
    Abstract: Attenuation correction in SPECT studies such as cardiac function imaging is carried out using an iterative statistically-based transmission projection reconstruction algorithm that is capable of modeling overlapping transmission beams from a line source array of radiation emitters. Downscatter between emission and transmission photons is additively corrected for in the algorithm. Optimal line source spacing techniques and source collimation angle selection are derived to improve performance and reduce cost.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 29, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventor: Eric G. Hawman
  • Patent number: 7323690
    Abstract: A compact SPECT imaging device generally includes a base assembly, a control tower assembly, a linkage assembly and a pair of detectors. The base assembly includes a plurality of fastening and/or anchoring assemblies such that the base assembly can be detachably fastenably secured between a gantry of an existing CT imaging device and a subject table. Preferably, the detectors of the compact SPECT imaging device are oriented with respect to one another at an angle of 90°. Preferably, the compact SPECT imaging device includes at least one input/output for communicatively connecting a peripheral device, such as a computer that is also connected to an existing CT imaging device.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: January 29, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Markus Lusser, Michael Reitermann
  • Patent number: 7323691
    Abstract: Methods and apparatus provide for determining whether X-rays produced by a computer tomography (CT) scanner have infiltrated a single photon emission computed tomography (SPECT) scanner and shutting down at least one of a power source to one or more photo-multiplier tubes (PMTs) of the SPECT scanner, and an X-ray source of the CT scanner, when the determination is affirmative.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: January 29, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: James Frank Caruba, Roger E. Arseneau
  • Patent number: 7323692
    Abstract: The present invention is an indirect AMFPI wherein a phosphor such as a structured cesium iodide (CsI) is used to convert x-ray energy to optical photons or a charge, which is then detected by a two-dimensional array of either thin-film transistors (TFTs) such as an amorphous a-Se TFTs or a photodiode array. A scanning control circuit generates pulses to turn on the TFTs one row at a time, and thus the charge in the individual arrays is transferred from the TFT to one or more external charge-sensitive amplifiers. The charge-sensitive amplifiers are shared by all the pixels in the same column. The two-dimensional array can be read in real time.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: January 29, 2008
    Assignees: Research Foundation of State University of New York, Sunnybrook and Woman's College Health Sciences Center
    Inventors: John A. Rowlands, Wei Zhao
  • Patent number: 7323693
    Abstract: A reaction curable resin is irradiated with ultraviolet light having wavelengths of 250 to 380 nm. A screen image of luminance value, which is obtained by extracting only a specific wavelength component of the reflected ultraviolet light, is recorded, and the cured state of an ultraviolet curable resin is quantified from a captured image and displayed. At the same time, the spectral characteristics of reflected light are measured by an ultraviolet spectroscope and a cured state is quantified in accordance with the change rate of absorbances obtained from a change of spectral characteristics by combining the spectral characteristic with a luminance value image and displayed.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: January 29, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsushi Sanuki, Naoko Miura
  • Patent number: 7323694
    Abstract: A radiation source module comprising a support member, a radiation source assembly connected to the support member, the radiation source assembly comprising at least one elongate radiation source having a source longitudinal axis and a module-to-surface seal disposed on a first elongate surface of the module, the first elongate surface comprising a first longitudinal axis transverse to the source longitudinal axis, the seal operable to provide a substantially fluid tight seal between the first surface and a second surface which is adjacent to the first surface. A fluid treatment system employ the radiation source module is also described.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: January 29, 2008
    Assignee: Trojan Technologies Inc.
    Inventors: George A. Traubenberg, Steven M. Bakker, Kuang-Ping Chiu
  • Patent number: 7323695
    Abstract: A reciprocating drive system, method, and apparatus for scanning a workpiece are provided, wherein a motor comprising a rotor and stator operable to individually rotate about a first axis is operable to reciprocally translate the workpiece with respect to a stationary reference. A shaft rotatably driven by the rotor extends along the first axis, and a scan arm is operably coupled to the shaft, wherein the scan arm is operable to support the workpiece thereon. Cyclical counter rotations of the shaft by the motor are operable to rotate the scan arm, therein scanning the workpiece through the ion beam along a first scan path, wherein the stator acts as a reaction mass to the rotation of the rotor. A controller is further operable to control an electromagnetic force between the rotor and the stator, therein generally determining a rotational position of the rotor and the stator.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: January 29, 2008
    Assignee: Axcelis Technologies, Inc.
    Inventors: John W. Vanderpot, John D. Pollock, Donald W. Berrian
  • Patent number: 7323696
    Abstract: Beads coded with phosphor particles and methods of making and using them are provided.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: January 29, 2008
    Assignee: Applera Corporation
    Inventors: Charles S. Vann, Charles R. Connell, Aldrich N. K. Lau, Meng C. Taing, Steven M. Menchen
  • Patent number: 7323697
    Abstract: A gradient charged particle beam apparatus capable of moving highly accurately to a specific position by eliminating influences of warp inside a wafer surface is provided. A portion 46 having a mark 47 for aligning visual field alignment positioned in advance to the same horizontal and the same height as a stage plane as a reference point is arranged on a wafer holder. A height of an observation point on a sample is adjusted to the height of the mark 47 and the visual field of a gradient column is brought into conformity with the visual field of a vertical column by use of a known offset between the gradient column and the vertical column at that time.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: January 29, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyasu Kaga, Hiroyuki Suzuki, Yutaka Hojyo
  • Patent number: 7323698
    Abstract: A subsystem for an exposure apparatus has a thermophoretic plate and at least one shielding layer covering a first surface of the thermophoretic plate. The at least one shielding layer controls thermally induced distortions of the exposure apparatus by reducing heat transfer between the exposure apparatus and the thermophoretic plate. The shielding layer includes an insulation layer and a reflective layer, where the reflective layer has a surface with a low emissivity. In one implementation, the reflective surface may be a surface of the thermophoretic plate. The reflective surface should be facing the exposure apparatus, but is not a requirement. More than one shielding layer may be used, in which each outermost shielding layer will have a higher temperature.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: January 29, 2008
    Assignee: Nikon Corporation
    Inventor: Michael Sogard
  • Patent number: 7323699
    Abstract: A method and apparatus includes positioning a reactant on a surface in specific location and then directing an energy source from a device at the reactant such that it modifies the surface to either remove material or add material.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 29, 2008
    Assignee: Rave, LLC
    Inventors: Barry F. Hopkins, David J. Ray, Jeffrey E. LeClaire, Roy White
  • Patent number: 7323700
    Abstract: A method and apparatus for controlling ion beam scanning in an ion implanter is disclosed. Before an implant process is commenced, a scan waveform to create a uniform distribution along a magnetic scan axis is determined, using a travelling Faraday detector (24). Charge data from the travelling Faraday (24) is collected into a small, finite number of channels and this is used to create a histogram of collected charge vs. beam crossing time. This is in turn used to correct a target scan velocity to compensate for any dose non-uniformity. The target scan velocity is used as a first input to a fast feedback loop. A second input is obtained by digitizing the output of an inductive pickup in the magnet of the magnetic scanner in the ion implanter. Each input is separately integrated and Fast Fourier Transformed Error coefficients Ferror are obtained by dividing. Fourier coefficients from the target scan velocity by Fourier coefficients from the inductive pickup signal.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: January 29, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Robert Joseph Ledoux, Raymond Paul Boisseau, William Philip Nett
  • Patent number: 7323701
    Abstract: A gas discharge lamp for the wavelength range of extreme ultraviolet radiation and/or soft X-ray radiation has at least two electrodes for providing a radiaton-emitting plasma in the intervening discharge space. One of the electrodes has a continuous opening to an adjoining outer region where charge carriers can be generated which can be transported through the opening in to the discharge space. The electrode opening narrows in the direction of the outer region.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: January 29, 2008
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Dominik Vaudrevange, Klaus Bergmann
  • Patent number: 7323702
    Abstract: A handheld or display assembly device which allows a user to obtain UV light in varying wavelengths from a single standard short-wave (SW) ultraviolet lamp. A standard SW ultraviolet lamp that has no phosphor coating is used, and the conversion sheets with different mixtures (or compounds) of phosphor are applied to convert the SW light into a medium-wave or long-wave light. One aspect of the present invention comprises an ultraviolet lamp, a housing for said lamp, a set of conversion sheets, and holding elements for removably mounting the conversion sheets adjacent the lamp. Another embodiment comprises a continuous sheet of the conversion sheets which is configured to roll across the front of the UV lamp, thereby converting the SW light into medium-wave or long-wave light.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: January 29, 2008
    Inventor: Donald Ellis Newsome
  • Patent number: 7323703
    Abstract: An apparatus and method is described which may comprise a plasma produced extreme ultraviolet (“EUV”) light source multilayer collector which may comprise a plasma formation chamber; a shell within the plasma formation chamber in the form of a collector shape having a focus; the shell having a sufficient size and thermal mass to carry operating heat away from the multilayer reflector and to radiate the heat from the surface of the shell on a side of the shell opposite from the focus. The material of the shell may comprise a material selected from a group which may comprise silicon carbide, silicon, Zerodur or ULE glass, aluminum, beryllium, molybdenum, copper and nickel. The apparatus and method may comprise at least one radiative heater directed at the shell to maintain the steady state temperature of the shell within a selected range of operating temperatures.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: January 29, 2008
    Assignee: Cymer, Inc.
    Inventors: I. Roger Oliver, William N. Partlo, Igor V. Fomenkov, Alexander I. Ershov, Norbert Bowering, John Viatella, David W. Myers
  • Patent number: 7323704
    Abstract: A chip type LED which is capable of laterally emitting light from the light emitting diode chip and having a relatively small thickness is provided. The chip type LED includes an insulating substrate 12, a light emitting diode chip 15 mounted on the upper surface of the insulating substrate, and a transparent package 16 provided on the upper surface of the insulating substrate to hermetically seal the light emitting diode chip. The light emitting diode chip 15 is mounted on the upper surface of the insulating substrate with the anode electrode 15f of the light emitting diode chip oriented downward and the cathode electrode 15a oriented upward.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: January 29, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Junichi Itai
  • Patent number: 7323705
    Abstract: The present application relates to an apparatus and method for measuring liquid levels in small-volume wells.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: January 29, 2008
    Assignee: Applera Corporation
    Inventors: Douwe D. Haga, Michael R. Flatbush, Michael Mosseau, Tony S. Yan, Willy Wiyatno, Mark T. Reed
  • Patent number: 7323706
    Abstract: A first time stamp T1 indicative of the time of irradiation of an object and a second time stamp T2 indicative of the time of exposure of an image detector by the radiation image of the object, are generated. Meta-data relating to the object are associated with the radiation image of the object if T1 equals T2 or if T1 approximates T2 within a predefined limit.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 29, 2008
    Assignee: AGFA Healthcare, N.V.
    Inventors: Walter Exelmans, Eric De Broeck, Peter Durt, Patrick Lambrechts, Bart Tytgat
  • Patent number: 7323707
    Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Patent number: 7323708
    Abstract: A phase change memory device includes a lower electrode and a porous dielectric layer having fine pores on the lower electrode. A phase change layer is provided in the fine pores of the porous dielectric layer. An upper electrode is provided on the phase change layer. Related manufacturing methods are also described.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Ho Lee, Young-Nam Hwang
  • Patent number: 7323709
    Abstract: The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted with an insulator layer, preferably aluminum oxide, disposed between the collector and emitter electrodes. The present invention additionally comprises a method for enhancing tunneling of higher energy electrons from an emitter electrode to a collector electrode, the method comprising the step of contacting the collector electrode with an insulator, preferably aluminum oxide, and placing the insulator between the collector electrode and the emitter electrode.
    Type: Grant
    Filed: November 27, 2003
    Date of Patent: January 29, 2008
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Leri Tsakadze
  • Patent number: 7323710
    Abstract: A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Pil Kim, Sun-Ghil Lee, Si-Young Choi
  • Patent number: 7323711
    Abstract: A high-temperature superconductive device is disclosed, including a ramp-edge junction. The ramp-edge junction includes a first electrode layer (5) that defines the size of the ramp-edge junction and a second electrode layer (6). The width of the second electrode layer (6) is greater than the width of the first electrode layer (5). The first electrode layer (5) and the second electrode layer (6) touch in part, and are separated via a first insulation layer (7) in remaining part. Because the ramp-edge junction includes the first electrode layer (5) and the second electrode layer (6), the inductance of the ramp-edge junction can be reduced with the critical current density Jc being kept at a high level.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: January 29, 2008
    Assignees: FUJITSU Limited, International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Hideo Suzuki, Masahiro Horibe, Keiichi Tanabe
  • Patent number: 7323712
    Abstract: An anisotropically conductive connector, by which positioning, and holding and fixing to a wafer to be inspected can be conducted with ease even when the wafer has a large area, contains a frame plate having a plurality of anisotropically conductive film-arranging holes formed corresponding to regions of electrodes to be inspected of a wafer, and a plurality of elastic anisotropically conductive films arranged in the respective anisotropically conductive film-arranging holes and supported by the inner peripheral edge thereabout.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: January 29, 2008
    Assignee: JSR Corporation
    Inventors: Terukazu Kokubo, Koji Seno, Masaya Naoi, Kazuo Inoue
  • Patent number: 7323713
    Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 29, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Ishiga, Takuji Yoshida, Yuichi Masutani, Shingo Nagano
  • Patent number: 7323714
    Abstract: In a semiconductor device with a reflective passive matrix liquid crystal display mounted thereto, the area for mounting a logic circuit is reduced, the product is reduced in size, and further the reliability is improved. A semiconductor device with a reflective passive matrix liquid crystal display mounted thereto is reduced in size by forming all or some of externally-mounted logic circuits in a region overlapping a pixel region on a substrate where a reflective electrode is formed. The present invention can also reduce the number of IC chips and the like mounted to a substrate greatly and the reliability in mounting IC chips and the like to a substrate can be improved.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: January 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tadafumi Ozaki, Kohei Mutaguchi
  • Patent number: 7323715
    Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: January 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7323716
    Abstract: This invention provides a manufacturing method for fabricating on the same substrate both high voltage thin film transistors suitable for driving liquid crystal and low voltage drive high performance thin film transistors. In addition, this invention provides a thin film transistor substrate where the area occupied by a storage capacitor in each pixel is reduced to raise the aperture ratio of the display unit. One aspect of this invention provides a manufacturing method characterized in that the impurity regions of both high voltage thin film transistors and high performance thin film transistors which differ in the thickness of gate insulation are formed by implanting a dopant through the same two-layered film. Another aspect of this invention reduces the area occupied by the drive circuit in the display unit by utilizing an extension of one layer of the insulation film included in each thin film transistor.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: January 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Satou, Toshihiko Itoga, Takeo Shiba
  • Patent number: 7323717
    Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary, wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: January 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 7323718
    Abstract: A readout pixel of an input display is provided. The readout pixel includes the fundamental elements as the normal pixel, and further includes a photo sensing element with a second switching element and a third switching element for generating a photo signal. The second switching element includes a second gate electrode connecting to a gate line, a second drain electrode, and a second source electrode connecting to a readout line. The third switching element includes a third gate electrode and a third drain electrode both connecting to a reference voltage, and a third source electrode connecting to the second drain electrode.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 29, 2008
    Assignee: Hannstar Display Corporation
    Inventors: Po-Yang Chen, Po-Sheng Shih, Wei-Chou Chen, Kei-Hsiung Yang
  • Patent number: 7323719
    Abstract: The group III-V nitride series semiconductor substrate has good-product yield when the band-edge peak light-emission intensity ratio ?=N1/N2 is ?<1, where N1 is a band-edge peak light-emission intensity at an arbitrary photoluminescence measurement position on the front side of the substrate, and N2 is a band-edge peak light-emission intensity on the back side of the substrate corresponding to the photoluminescence measurement position.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: January 29, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventor: Yusuke Kawaguchi
  • Patent number: 7323720
    Abstract: A light-emitting device includes a substrate having a plurality of light-emitting elements and a light emission region arranged on one surface thereof, light being emitted from one surface of the light emission region; and an integrated circuit chip that generates signals for controlling the plurality of light-emitting elements. The integrated circuit chip is connected to the substrate so as to overlap a portion of or the entire light emission region, as viewed from the other surface of the substrate.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: January 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Shinsuke Fujikawa
  • Patent number: 7323721
    Abstract: A monolithic, multi-color semiconductor light emitting diode (LED) is formed with a multi-bandgap, multi-quantum well (MQW) active light emitting region which emits light at spaced-apart wavelength bands or regions ranging from UV to red. The MQW active light emitting region comprises a MQW layer stack including n quantum barriers which space apart n?1 quantum wells. Embodiments include those wherein the MQW layer stack includes quantum wells of at least two different bandgaps for emitting light of two different wavelengths, e.g., in the blue or green regions and in at least one other region, and the intensities of the emissions are adjusted to provide a preselected color of combined light emission, preferably white light.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: January 29, 2008
    Assignee: Blue Photonics Inc.
    Inventors: Shirong Liao, Jinlin Ye, Theeradetch Detchprohm, Jyh-Chia Chen, Yea-Chuan Milton Yeh
  • Patent number: 7323722
    Abstract: In a semiconductor optical device, a first conductive type semiconductor region is provided on a surface of GaAs. The first conductive type semiconductor region has a first region and a second region. An active layer is provided on the first region of the first conductive type semiconductor region. The active layer has a pair of side surfaces. A second conductive type semiconductor region is provided on the sides and top of the active layer, and the second region of the first conductive type semiconductor region. The bandgap energy of the first conductive type semiconductor region is greater than that of the active layer. The bandgap energy of the second conductive type semiconductor region is greater than that of the active layer. The second region of the first conductive type semiconductor region and the second conductive type semiconductor region constitute a pn junction.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: January 29, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun-ichi Hashimoto, Tsukuru Katsuyama
  • Patent number: 7323723
    Abstract: A semiconductor light-emitting device includes substrate (3), a plurality of light-emitting-element-layers (10a, 10b, 10c, . . . ) of semiconductor material formed on the substrate (3) so as to be isolated from each other and having a wider band gap than the substrate (3), and phosphors (15a, 15b, 15c, . . . ) converting wavelengths of light from the light-emitting-element-layers (10a, 10b, 10c, . . . ) into other wavelengths.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: January 29, 2008
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Ohtsuka, Hitoshi Murofushi
  • Patent number: 7323724
    Abstract: A nitride semiconductor device includes a semiconductor layer, a first electrode for establishing an ohmic contact disposed on the semiconductor layer, and a second electrode on the first electrode, having a different shape from that of the first electrode. A joint region is formed with the upper layer of the first electrode and the lower layer of the second electrode. The joint region comprises an element of the platinum group.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 29, 2008
    Assignee: Nichia Corporation
    Inventors: Yasunobu Sugimoto, Akinori Yoneda
  • Patent number: 7323725
    Abstract: The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer disposed between the emitter layer and the base layer; a collector electrode, a base electrode and the emitter layer all connected to an emitter electrode; the quantum dot barrier layer having a plurality of quantum dots being sandwiched between first and second barrier layers from the emitter layer side and the base layer side, respectively and each having a portion that is convex to the base layer; a base layer side interface in the second barrier layer, and collector layer side and emitter layer side interfaces in the base layer having curvatures that are convex to the collector layer corresponding to the convex portions of the quantum dots.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeo Yoshii, Nobuyuki Otsuka, Koichi Mizuno, Asamira Suzuki
  • Patent number: 7323726
    Abstract: A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopants of the source and drain regions diffuse laterally to overlap. The overlapping diffusion regions conduct and couple the drain region to a source region. Beneficially, the drain region is coupled to the metal Vss line. As a beneficial result, source contacts may be formed along a line of drain contacts in associated rows of drain contacts, and coupled to a common source line via the novel overlapping diffusion regions. A plurality of word lines may be formed without any bending in the word lines to accommodate source contacts that are larger than the source line.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: January 29, 2008
    Assignee: Spansion LLC
    Inventors: Kuo-Tung Chang, Yu Sun
  • Patent number: 7323727
    Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: January 29, 2008
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
  • Patent number: 7323728
    Abstract: Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconductor layer and having a material having a first band gap, a second n-type semiconductor layer formed on the p-type semiconductor layer, being smaller than the p-type semiconductor layer in area and having a material having a second band gap larger than the first band gap, an implant portion formed to penetrate the p-type semiconductor layer, the first n-type semiconductor layer, and the n+-type semiconductor layer in a region where the second n-type semiconductor layer is not formed and to divide these layers into two regions, and an electrode formed on a region of the p-type semiconductor layer where the second n-type semiconductor layer is not formed, so as to bridge over the implant portion.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: January 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Sugiyama
  • Patent number: 7323729
    Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: January 29, 2008
    Assignee: Promos Technologies Inc.
    Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao
  • Patent number: 7323730
    Abstract: The invention relates to a semiconductor device comprising at least two electrodes and at least one nanotube or nanowire, in particular a carbon nanotube or nanowire, the device including at least one semiconductive nanotube or nanowire having at least one region that is covered at least in part by at least one layer of molecules or nanocrystals of at least one photosensitive material, an electrical connection between said two electrodes being made by at least one nanotube, namely said semiconductive nanotube or nanowire and optionally by at least one other nanotube or nanowire.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: January 29, 2008
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Julien Borghetti, Jean-Philippe Bourgoin, Pascale Mordant, Vincent Derycke, Arianna Filoramo, Marcelo Goffman
  • Patent number: 7323731
    Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 29, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Yuzurihara, Ryuichi Mishima, Takanori Watanabe, Takeshi Ichikawa, Seiichi Tamura
  • Patent number: 7323732
    Abstract: An MRAM array having enhanced magnetoresistance includes a spin filtering element connected by a spin hold element to the MRAM cell structures. A spin filtering element may serve several MRAM cell structures, by connecting the spin filtering element to a series of MRAM cell structures by a spin hold wire, or a spin filtering element and a spin hold element may be formed as adjacent layers in each MRAM cell stack.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: January 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Hsiang-Lan Lung
  • Patent number: 7323733
    Abstract: A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiO3 and the resistor layer includes doped SrZrO3.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: January 29, 2008
    Assignee: Winbond Electronics Corp.
    Inventors: Tseung-Yuen Tseng, Chih-Yi Liu, Pei-Hsun Wu
  • Patent number: 7323734
    Abstract: A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area can be a sidewall of one of the electrodes, or a perimeter edge of a contact opening through the electrode. Thus, when the thickness of the electrode is relatively thin, the contact area between the electrode and the phase changeable material pattern is relatively very small. As a result, it is possible to reduce power consumption of the phase changeable memory device and to form reliable and compact phase changeable memory cells.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongho Ha, Jihye Yi, Hyunjo Kim
  • Patent number: 7323735
    Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Naotaka Hashimoto, Yutaka Hoshino, Shuji Ikeda
  • Patent number: 7323736
    Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: January 29, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pradeep Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen, Purakh Verma
  • Patent number: 7323737
    Abstract: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, F. Daniel Gealy, Gurtej S. Sandhu
  • Patent number: 7323738
    Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Garo J. Derderian